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Merge pull request #2741 from fpistm/stm32cubef7_update
chore(f7): update to latest STM32CubeF7 v1.17.3
2 parents 9e0d259 + 8df1389 commit 2f4536d

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‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12824,7 +12824,7 @@ typedef struct
1282412824

1282512825
/******************* Bit definition for TIM_CCR5 register *******************/
1282612826
#define TIM_CCR5_CCR5_Pos (0U)
12827-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
12827+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1282812828
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1282912829
#define TIM_CCR5_GC5C1_Pos (29U)
1283012830
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12846,7 +12846,7 @@ typedef struct
1284612846

1284712847
/******************* Bit definition for TIM_CCR5 register *******************/
1284812848
#define TIM_CCR5_CCR5_Pos (0U)
12849-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
12849+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1285012850
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1285112851
#define TIM_CCR5_GC5C1_Pos (29U)
1285212852
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13069,7 +13069,7 @@ typedef struct
1306913069

1307013070
/******************* Bit definition for TIM_CCR5 register *******************/
1307113071
#define TIM_CCR5_CCR5_Pos (0U)
13072-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13072+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1307313073
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1307413074
#define TIM_CCR5_GC5C1_Pos (29U)
1307513075
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13047,7 +13047,7 @@ typedef struct
1304713047

1304813048
/******************* Bit definition for TIM_CCR5 register *******************/
1304913049
#define TIM_CCR5_CCR5_Pos (0U)
13050-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13050+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1305113051
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1305213052
#define TIM_CCR5_GC5C1_Pos (29U)
1305313053
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13069,7 +13069,7 @@ typedef struct
1306913069

1307013070
/******************* Bit definition for TIM_CCR5 register *******************/
1307113071
#define TIM_CCR5_CCR5_Pos (0U)
13072-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13072+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1307313073
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1307413074
#define TIM_CCR5_GC5C1_Pos (29U)
1307513075
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13926,7 +13926,7 @@ typedef struct
1392613926

1392713927
/******************* Bit definition for TIM_CCR5 register *******************/
1392813928
#define TIM_CCR5_CCR5_Pos (0U)
13929-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
13929+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1393013930
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1393113931
#define TIM_CCR5_GC5C1_Pos (29U)
1393213932
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14274,7 +14274,7 @@ typedef struct
1427414274

1427514275
/******************* Bit definition for TIM_CCR5 register *******************/
1427614276
#define TIM_CCR5_CCR5_Pos (0U)
14277-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14277+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1427814278
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1427914279
#define TIM_CCR5_GC5C1_Pos (29U)
1428014280
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14567,7 +14567,7 @@ typedef struct
1456714567

1456814568
/******************* Bit definition for TIM_CCR5 register *******************/
1456914569
#define TIM_CCR5_CCR5_Pos (0U)
14570-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14570+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1457114571
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1457214572
#define TIM_CCR5_GC5C1_Pos (29U)
1457314573
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14567,7 +14567,7 @@ typedef struct
1456714567

1456814568
/******************* Bit definition for TIM_CCR5 register *******************/
1456914569
#define TIM_CCR5_CCR5_Pos (0U)
14570-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14570+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1457114571
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1457214572
#define TIM_CCR5_GC5C1_Pos (29U)
1457314573
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14508,7 +14508,7 @@ typedef struct
1450814508

1450914509
/******************* Bit definition for TIM_CCR5 register *******************/
1451014510
#define TIM_CCR5_CCR5_Pos (0U)
14511-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14511+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1451214512
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1451314513
#define TIM_CCR5_GC5C1_Pos (29U)
1451414514
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14902,7 +14902,7 @@ typedef struct
1490214902

1490314903
/******************* Bit definition for TIM_CCR5 register *******************/
1490414904
#define TIM_CCR5_CCR5_Pos (0U)
14905-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
14905+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1490614906
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1490714907
#define TIM_CCR5_GC5C1_Pos (29U)
1490814908
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14997,7 +14997,7 @@ typedef struct
1499714997

1499814998
/******************* Bit definition for TIM_CCR5 register *******************/
1499914999
#define TIM_CCR5_CCR5_Pos (0U)
15000-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
15000+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1500115001
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1500215002
#define TIM_CCR5_GC5C1_Pos (29U)
1500315003
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15195,7 +15195,7 @@ typedef struct
1519515195

1519615196
/******************* Bit definition for TIM_CCR5 register *******************/
1519715197
#define TIM_CCR5_CCR5_Pos (0U)
15198-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
15198+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1519915199
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1520015200
#define TIM_CCR5_GC5C1_Pos (29U)
1520115201
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15290,7 +15290,7 @@ typedef struct
1529015290

1529115291
/******************* Bit definition for TIM_CCR5 register *******************/
1529215292
#define TIM_CCR5_CCR5_Pos (0U)
15293-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
15293+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */
1529415294
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1529515295
#define TIM_CCR5_GC5C1_Pos (29U)
1529615296
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -96,11 +96,11 @@
9696
#endif /* USE_HAL_DRIVER */
9797

9898
/**
99-
* @brief CMSIS Device version number V1.2.9
99+
* @brief CMSIS Device version number V1.2.10
100100
*/
101101
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
102102
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
103-
#define __STM32F7_CMSIS_VERSION_SUB2 (0x09) /*!< [15:8] sub2 version */
103+
#define __STM32F7_CMSIS_VERSION_SUB2 (0x0A) /*!< [15:8] sub2 version */
104104
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
105105
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
106106
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,16 @@ <h1 id="release-notes-for-stm32f7xx-cmsis"><strong>Release Notes for STM32F7xx C
3030
<div class="col-sm-12 col-lg-8">
3131
<h1 id="update-history"><strong>Update History</strong></h1>
3232
<div class="collapse">
33-
<input type="checkbox" id="collapse-section1_2_9" checked aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
33+
<input type="checkbox" id="collapse-section1_2_10" checked aria-hidden="true"> <label for="collapse-section1_2_10" aria-hidden="true"><strong>V1.2.10 / 25-April-2025</strong></label>
34+
<div>
35+
<ul>
36+
<li>Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.</li>
37+
<li>Fix Capture Compare register TIMx_CCR5 defintion.</li>
38+
</ul>
39+
</div>
40+
</div>
41+
<div class="collapse">
42+
<input type="checkbox" id="collapse-section1_2_9" aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
3443
<div>
3544
<ul>
3645
<li>Update GCC start-up files to call SystemInit() API <span class="citation" data-cites="Reset_Handler">@Reset_Handler</span> step: alignment with EWARM and MDK-ARM start-up files.</li>

‎system/Drivers/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -86,14 +86,14 @@
8686
#if defined(VECT_TAB_SRAM)
8787
#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field.
8888
This value must be a multiple of 0x200. */
89-
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
90-
This value must be a multiple of 0x200. */
9189
#else
9290
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
9391
This value must be a multiple of 0x200. */
94-
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
95-
This value must be a multiple of 0x200. */
9692
#endif /* VECT_TAB_SRAM */
93+
#if !defined(VECT_TAB_OFFSET)
94+
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
95+
This value must be a multiple of 0x200. */
96+
#endif /* VECT_TAB_OFFSET */
9797
#endif /* USER_VECT_TAB_ADDRESS */
9898
/******************************************************************************/
9999

@@ -199,7 +199,7 @@ void SystemInit(void)
199199
*/
200200
void SystemCoreClockUpdate(void)
201201
{
202-
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
202+
uint32_t tmp, pllvco, pllp, pllsource, pllm;
203203

204204
/* Get SYSCLK source -------------------------------------------------------*/
205205
tmp = RCC->CFGR & RCC_CFGR_SWS;

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
* STM32F2: 2.2.6
77
* STM32F3: 2.3.8
88
* STM32F4: 2.6.10
9-
* STM32F7: 1.2.9
9+
* STM32F7: 1.2.10
1010
* STM32G0: 1.4.4
1111
* STM32G4: 1.2.5
1212
* STM32H5: 1.4.0

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