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variant: WB: add generic WB5MMGH
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent bb5291f commit ab92e67

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‎README.md

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@@ -407,6 +407,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| Status | Device(s) | Name | Release | Notes |
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| :----: | :-------: | ---- | :-----: | :---- |
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| :green_heart: | STM32WB55CC<br>STM32WB55CE<br>STM32WB55CG | Generic Board | *2.0.0* | |
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| :yellow_heart: | STM32WB5MMG | Generic Board | **2.1.0** | |
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| :green_heart: | STM32WB55RC<br>STM32WB55RE<br>STM32WB55RG | Generic Board | *2.0.0* | |
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### Generic STM32WL boards

‎boards.txt

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@@ -4948,6 +4948,14 @@ GenWB.menu.pnum.GENERIC_WB55CGUX.build.board=GENERIC_WB55CGUX
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GenWB.menu.pnum.GENERIC_WB55CGUX.build.product_line=STM32WB55xx
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GenWB.menu.pnum.GENERIC_WB55CGUX.build.variant=STM32WBxx/WB55C(C-E-G)U
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# Generic WB5MMGHx
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GenWB.menu.pnum.GENERIC_WB5MMGHX=Generic WB5MMGHx
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GenWB.menu.pnum.GENERIC_WB5MMGHX.upload.maximum_size=827392
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GenWB.menu.pnum.GENERIC_WB5MMGHX.upload.maximum_data_size=196608
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GenWB.menu.pnum.GENERIC_WB5MMGHX.build.board=GENERIC_WB5MMGHX
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GenWB.menu.pnum.GENERIC_WB5MMGHX.build.product_line=STM32WB5Mxx
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GenWB.menu.pnum.GENERIC_WB5MMGHX.build.variant=STM32WBxx/WB5MMGH
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# Generic WB55RCVx
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GenWB.menu.pnum.GENERIC_WB55RCVX=Generic WB55RCVx
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GenWB.menu.pnum.GENERIC_WB55RCVX.upload.maximum_size=131072

‎variants/STM32WBxx/WB5MMGH/generic_clock.c

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@@ -12,6 +12,7 @@
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*/
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#if defined(ARDUINO_GENERIC_WB5MMGHX)
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#include "pins_arduino.h"
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#include "lock_resource.h"
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/**
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* @brief System Clock Configuration
@@ -20,8 +21,75 @@
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*/
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WEAK void SystemClock_Config(void)
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{
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/* SystemClock_Config can be generated by STM32CubeMX */
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#warning "SystemClock_Config() is empty. Default clock at reset is used."
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
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/* This prevents concurrent access to RCC registers by CPU2 (M0+) */
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hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
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hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
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| RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
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RCC_OscInitStruct.PLL.PLLN = 32;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
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| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
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RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the peripherals clocks
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*/
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_CLK48SEL
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| RCC_PERIPHCLK_USB | RCC_PERIPHCLK_RNG;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
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PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
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PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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Error_Handler();
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}
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LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
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LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
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LL_PWR_SMPS_Enable();
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/* Select HSI as system clock source after Wake Up from Stop mode */
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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hsem_unlock(CFG_HW_RCC_SEMID);
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}
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#endif /* ARDUINO_GENERIC_* */

‎variants/STM32WBxx/WB5MMGH/ldscript.ld

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/*
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******************************************************************************
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**
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** File : LinkerScript.ld
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**
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** Author : STM32CubeIDE
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**
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** Abstract : Linker script for STM32WB5MMG Device
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** 1024Kbytes FLASH
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** 256Kbytes RAM
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used.
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is without any warranty
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** of any kind.
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**
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*****************************************************************************
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** @attention
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**
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** <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
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** All rights reserved.</center></h2>
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**
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** This software component is licensed by ST under BSD 3-Clause license,
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** the "License"; You may not use this file except in compliance with the
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** License. You may obtain a copy of the License at:
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** opensource.org/licenses/BSD-3-Clause
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**
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*****************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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/* Highest address of the user mode stack */
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_estack = 0x20030000; /* end of RAM */
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/* Generate a link error if heap and stack don't fit into RAM */
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_Min_Heap_Size = 0x200 ; /* required amount of heap */
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_Min_Stack_Size = 0x400 ; /* required amount of stack */
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/* Specify the memory areas */
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
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RAM1 (xrw) : ORIGIN = 0x20000004, LENGTH = LD_MAX_DATA_SIZE - 4
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RAM_SHARED (xrw) : ORIGIN = 0x20030000, LENGTH = 10K
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}
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/* Define output sections */
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SECTIONS
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{
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/* The startup code goes first into FLASH */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >FLASH
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/* The program code and other data goes into FLASH */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >FLASH
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/* Constant data goes into FLASH */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >FLASH
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.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
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.ARM : {
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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} >FLASH
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.preinit_array :
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{
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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} >FLASH
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.init_array :
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{
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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} >FLASH
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.fini_array :
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{
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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} >FLASH
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections goes into RAM, load LMA copy after code */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >RAM1 AT> FLASH
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/* Uninitialized data section */
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. = ALIGN(4);
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.bss :
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{
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM1
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/* User_heap_stack section, used to check that there is enough RAM left */
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._user_heap_stack :
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{
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. = ALIGN(8);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} >RAM1
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/* Remove information from the standard libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
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MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
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MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
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}
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