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variant: WB: add STM32WB5MM-DK
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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‎README.md

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@@ -149,6 +149,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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| :green_heart: | STM32L475VG | [B-L475E-IOT01A](http://www.st.com/en/evaluation-tools/b-l475e-iot01a.html) | *1.0.1* | |
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| :green_heart: | STM32F413ZH | [32F413HDISCOVERY](https://www.st.com/en/evaluation-tools/32f413hdiscovery.html) | *1.9.0* | |
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| :green_heart: | STM32L4S5VI | [B-L4S5I-IOT01A](https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html) | *2.0.0* | |
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| :yellow_heart: | STM32WB5MMG | [STM32WB5MM-DK](https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html) | **2.1.0** | |
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### [Eval](https://www.st.com/en/evaluation-tools/stm32-eval-boards.html) boards
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‎boards.txt

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@@ -823,6 +823,19 @@ Disco.menu.pnum.B_L072Z_LRWAN1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
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Disco.menu.pnum.B_L072Z_LRWAN1.build.cmsis_lib_gcc=arm_cortexM0l_math
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Disco.menu.pnum.B_L072Z_LRWAN1.build.extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0
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# STM32WB5MM-DK board
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Disco.menu.pnum.STM32WB5MM_DK=STM32WB5MM-DK
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Disco.menu.pnum.STM32WB5MM_DK.node="DIS_WB5MMG"
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Disco.menu.pnum.STM32WB5MM_DK.upload.maximum_size=827392
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Disco.menu.pnum.STM32WB5MM_DK.upload.maximum_data_size=196608
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Disco.menu.pnum.STM32WB5MM_DK.build.mcu=cortex-m4
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Disco.menu.pnum.STM32WB5MM_DK.build.flags.fp=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
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Disco.menu.pnum.STM32WB5MM_DK.build.board=STM32WB5MM_DK
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Disco.menu.pnum.STM32WB5MM_DK.build.series=STM32WBxx
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Disco.menu.pnum.STM32WB5MM_DK.build.product_line=STM32WB5Mxx
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Disco.menu.pnum.STM32WB5MM_DK.build.variant=STM32WBxx/WB5MMGH
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Disco.menu.pnum.STM32WB5MM_DK.build.cmsis_lib_gcc=arm_cortexM4lf_math
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# Upload menu
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Disco.menu.upload_method.MassStorage=Mass Storage
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Disco.menu.upload_method.MassStorage.upload.protocol=

‎variants/STM32WBxx/WB5MMGH/variant_STM32WB5MM_DK.cpp

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/*
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*******************************************************************************
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* Copyright (c) 2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_STM32WB5MM_DK)
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#include "pins_arduino.h"
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#include "lock_resource.h"
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// Digital PinName array
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const PinName digitalPin[] = {
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PC_0, // D0/A9
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PB_5, // D1
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PD_12, // D2
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PD_14, // D3
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PE_4, // D4
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PB_10, // D5
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PE_0, // D6
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PB_2, // D7
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PD_13, // D8
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PD_15, // D9
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PA_4, // D10/A10
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PA_7, // D11/A11
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PB_4, // D12
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PA_1, // D13/A12
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PA_10, // D14
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PB_8, // D15
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PC_3, // D16/A0
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PA_2, // D17/A1
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PA_5, // D18/A2
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PC_1, // D19/A3
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PC_4, // D20/A4
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PC_5, // D21/A5
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PD_0, // D22
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PA_6, // D23/A6
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PD_4, // D24
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PC_2, // D25/A7
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PD_1, // D26
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PB_12, // D27
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PB_15, // D28
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PB_14, // D29
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PE_3, // D30
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PD_8, // D31
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PA_0, // D32/A8
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PA_15, // D33
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PC_11, // D34
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PC_10, // D35
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PC_12, // D36
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PC_13, // D37
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PB_6, // D38
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PB_7, // D39
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PA_11, // D40
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PA_12, // D41
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PD_3, // D42
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PA_3, // D43
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PB_9, // D44
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PD_5, // D45
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PD_6, // D46
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PD_7, // D47
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PA_8, // D48
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PA_9, // D49
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PC_6, // D50
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PC_7, // D51
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PD_10, // D52
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PD_11, // D53
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PC_8, // D54
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PC_9, // D55
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PH_0, // D56
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PB_11, // D57
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PB_13, // D58
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PD_2, // D59
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PD_9, // D60
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PE_1, // D61
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PA_13, // D62
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PA_14, // D63
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PB_3, // D64
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PE_2, // D65
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PH_1, // D66
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PH_3 // D67
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};
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// Analog (Ax) pin number array
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const uint32_t analogInputPin[] = {
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16, // A0, PC3
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17, // A1, PA2
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18, // A2, PA5
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19, // A3, PC1
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20, // A4, PC4
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21, // A5, PC5
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23, // A6, PA6
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25, // A7, PC2
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32, // A8, PA0
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0, // A9, PC0
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10, // A10, PA4
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11, // A11, PA7
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13 // A12, PA1
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};
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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief System Clock Configuration
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* @param None
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* @retval None
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*/
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WEAK void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
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/* This prevents concurrent access to RCC registers by CPU2 (M0+) */
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hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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/** Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
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hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
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| RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
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RCC_OscInitStruct.PLL.PLLN = 8;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
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| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2;
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RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the peripherals clocks
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*/
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/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP
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| RCC_PERIPHCLK_CLK48SEL | RCC_PERIPHCLK_USB
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| RCC_PERIPHCLK_RNG;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
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PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
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PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
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PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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Error_Handler();
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}
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LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
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LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
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LL_PWR_SMPS_Enable();
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/* Select HSI as system clock source after Wake Up from Stop mode */
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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hsem_unlock(CFG_HW_RCC_SEMID);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ARDUINO_STM32WB5MM_DK */

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