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[G0] Update STM32G0xx CMSIS to v1.3.0
Included in STM32CubeG0 FW V1.3.0 Note: Trailing spaces have been cleaned. Signed-off-by: Frederic.Pillon <frederic.pillon@st.com>
1 parent b00a077 commit cd0ccb6

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9 files changed

+101
-158
lines changed

9 files changed

+101
-158
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g030xx.h

Lines changed: 6 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ typedef enum
9595
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
9696
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
9797
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
98-
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
98+
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
9999
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
100100
USART1_IRQn = 27, /*!< USART1 Interrupt */
101101
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -146,6 +146,7 @@ typedef struct
146146

147147

148148

149+
149150
/**
150151
* @brief CRC calculation unit
151152
*/
@@ -517,7 +518,6 @@ typedef struct
517518
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
518519
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
519520
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
520-
521521
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
522522

523523
/*!< Peripheral memory map */
@@ -577,7 +577,6 @@ typedef struct
577577

578578
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
579579
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
580-
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
581580

582581
/*!< IOPORT */
583582
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -618,7 +617,6 @@ typedef struct
618617
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
619618
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
620619
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
621-
622620
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
623621
#define CRC ((CRC_TypeDef *) CRC_BASE)
624622
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -637,7 +635,6 @@ typedef struct
637635
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
638636
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
639637
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
640-
641638
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
642639
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
643640
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -652,7 +649,6 @@ typedef struct
652649

653650
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
654651
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
655-
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
656652

657653
#define DBG ((DBG_TypeDef *) DBG_BASE)
658654

@@ -1729,27 +1725,6 @@ typedef struct
17291725
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
17301726
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
17311727

1732-
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
1733-
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
1734-
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
1735-
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
1736-
1737-
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
1738-
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
1739-
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
1740-
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
1741-
1742-
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
1743-
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
1744-
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
1745-
1746-
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
1747-
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
1748-
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
1749-
1750-
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
1751-
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
1752-
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
17531728
/******************************************************************************/
17541729
/* */
17551730
/* External Interrupt/Event Controller */
@@ -2265,7 +2240,6 @@ typedef struct
22652240
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
22662241

22672242

2268-
22692243
/******************************************************************************/
22702244
/* */
22712245
/* FLASH */
@@ -3865,6 +3839,7 @@ typedef struct
38653839
#define PWR_PUCRD_PU3_Pos (3U)
38663840
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
38673841
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
3842+
38683843
/******************** Bit definition for PWR_PDCRD register *****************/
38693844
#define PWR_PDCRD_PD0_Pos (0U)
38703845
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
@@ -4348,10 +4323,10 @@ typedef struct
43484323
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
43494324
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
43504325
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
4351-
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
4326+
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
43524327
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
43534328
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
4354-
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
4329+
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
43554330
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
43564331
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
43574332
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -5071,7 +5046,6 @@ typedef struct
50715046
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
50725047
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
50735048

5074-
50755049
/******************************************************************************/
50765050
/* */
50775051
/* Tamper and backup register (TAMP) */
@@ -5243,7 +5217,6 @@ typedef struct
52435217
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
52445218
#define TAMP_BKP4R TAMP_BKP4R_Msk
52455219

5246-
52475220
/******************************************************************************/
52485221
/* */
52495222
/* Serial Peripheral Interface (SPI) */
@@ -6935,7 +6908,6 @@ typedef struct
69356908
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
69366909

69376910

6938-
69396911
/******************************************************************************/
69406912
/* */
69416913
/* Window WATCHDOG */
@@ -7075,7 +7047,6 @@ typedef struct
70757047
((INSTANCE) == GPIOC) || \
70767048
((INSTANCE) == GPIOD) || \
70777049
((INSTANCE) == GPIOF))
7078-
70797050
/******************************* GPIO AF Instances ****************************/
70807051
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
70817052

@@ -7101,6 +7072,7 @@ typedef struct
71017072
/******************************** SPI Instances *******************************/
71027073
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
71037074
((INSTANCE) == SPI2))
7075+
71047076
/******************************** SPI Instances *******************************/
71057077
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
71067078

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g031xx.h

Lines changed: 6 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ typedef enum
9999
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
100100
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
101101
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
102-
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
102+
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
103103
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
104104
USART1_IRQn = 27, /*!< USART1 Interrupt */
105105
USART2_IRQn = 28, /*!< USART2 Interrupt */
@@ -151,6 +151,7 @@ typedef struct
151151

152152

153153

154+
154155
/**
155156
* @brief CRC calculation unit
156157
*/
@@ -550,7 +551,6 @@ typedef struct
550551
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
551552
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
552553
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
553-
554554
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
555555

556556
/*!< Peripheral memory map */
@@ -615,7 +615,6 @@ typedef struct
615615

616616
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
617617
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
618-
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
619618

620619
/*!< IOPORT */
621620
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
@@ -661,7 +660,6 @@ typedef struct
661660
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
662661
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
663662
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
664-
665663
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
666664
#define CRC ((CRC_TypeDef *) CRC_BASE)
667665
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
@@ -680,7 +678,6 @@ typedef struct
680678
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
681679
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
682680
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
683-
684681
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
685682
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
686683
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
@@ -695,7 +692,6 @@ typedef struct
695692

696693
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
697694
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
698-
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
699695

700696
#define DBG ((DBG_TypeDef *) DBG_BASE)
701697

@@ -1772,27 +1768,6 @@ typedef struct
17721768
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
17731769
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
17741770

1775-
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
1776-
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
1777-
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
1778-
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
1779-
1780-
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
1781-
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
1782-
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
1783-
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
1784-
1785-
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
1786-
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
1787-
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
1788-
1789-
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
1790-
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
1791-
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
1792-
1793-
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
1794-
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
1795-
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
17961771
/******************************************************************************/
17971772
/* */
17981773
/* External Interrupt/Event Controller */
@@ -2347,7 +2322,6 @@ typedef struct
23472322
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
23482323

23492324

2350-
23512325
/******************************************************************************/
23522326
/* */
23532327
/* FLASH */
@@ -4042,6 +4016,7 @@ typedef struct
40424016
#define PWR_PUCRD_PU3_Pos (3U)
40434017
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
40444018
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
4019+
40454020
/******************** Bit definition for PWR_PDCRD register *****************/
40464021
#define PWR_PDCRD_PD0_Pos (0U)
40474022
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
@@ -4563,10 +4538,10 @@ typedef struct
45634538
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
45644539
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
45654540
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
4566-
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
4541+
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
45674542
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
45684543
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
4569-
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
4544+
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
45704545
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
45714546
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
45724547
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
@@ -5315,7 +5290,6 @@ typedef struct
53155290
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
53165291
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
53175292

5318-
53195293
/******************************************************************************/
53205294
/* */
53215295
/* Tamper and backup register (TAMP) */
@@ -5487,7 +5461,6 @@ typedef struct
54875461
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
54885462
#define TAMP_BKP4R TAMP_BKP4R_Msk
54895463

5490-
54915464
/******************************************************************************/
54925465
/* */
54935466
/* Serial Peripheral Interface (SPI) */
@@ -7396,7 +7369,6 @@ typedef struct
73967369
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
73977370
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
73987371

7399-
74007372
/******************************************************************************/
74017373
/* */
74027374
/* VREFBUF */
@@ -7569,7 +7541,6 @@ typedef struct
75697541
((INSTANCE) == GPIOC) || \
75707542
((INSTANCE) == GPIOD) || \
75717543
((INSTANCE) == GPIOF))
7572-
75737544
/******************************* GPIO AF Instances ****************************/
75747545
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
75757546

@@ -7595,6 +7566,7 @@ typedef struct
75957566
/******************************** SPI Instances *******************************/
75967567
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
75977568
((INSTANCE) == SPI2))
7569+
75987570
/******************************** SPI Instances *******************************/
75997571
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
76007572

@@ -7841,7 +7813,6 @@ typedef struct
78417813
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
78427814
((INSTANCE) == USART2))
78437815

7844-
78457816
/******************** USART Instances : Synchronous mode **********************/
78467817
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
78477818
((INSTANCE) == USART2))

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