From 8089d77e7a454a3c49bc8419eec14c356708f75d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 14 Mar 2025 09:49:50 +0100 Subject: [PATCH 01/22] chore: update core version to 2.11.0-dev (0x021100F0) Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/inc/stm32_def.h | 6 +++--- platform.txt | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 920babfadd..82c8591178 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -6,15 +6,15 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x10U) /*!< [23:16] minor version */ -#define STM32_CORE_VERSION_PATCH (0x01U) /*!< [15:8] patch version */ +#define STM32_CORE_VERSION_MINOR (0x11U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: * 0: official release * [1-9]: release candidate * F[0-9]: development */ -#define STM32_CORE_VERSION_EXTRA (0x00U) /*!< [7:0] extra version */ +#define STM32_CORE_VERSION_EXTRA (0xF0U) /*!< [7:0] extra version */ #define STM32_CORE_VERSION ((STM32_CORE_VERSION_MAJOR << 24U)\ |(STM32_CORE_VERSION_MINOR << 16U)\ |(STM32_CORE_VERSION_PATCH << 8U )\ diff --git a/platform.txt b/platform.txt index ac80a8ab7a..651928558f 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.10.1 +version=2.11.0-dev # Define variables used multiple times in platform file @@ -17,7 +17,7 @@ busybox= busybox.windows={runtime.tools.STM32Tools.path}/win/busybox.exe toolchain_dir={runtime.tools.xpack-arm-none-eabi-gcc-14.2.1-1.1.path} -openocd_dir={runtime.tools.xpack-openocd-0.12.0-6.path} +openocd_dir={runtime.tools.xpack-openocd-0.12.0-5.path} tools_bin_path.windows={runtime.tools.STM32Tools.path}/win tools_bin_path.macosx={runtime.tools.STM32Tools.path}/macosx From e4b9bc87edf4c674a33e7d053ad8b1c210cac4b9 Mon Sep 17 00:00:00 2001 From: patricklaf Date: Fri, 14 Mar 2025 15:17:47 +0100 Subject: [PATCH 02/22] Update stm32_def.h Fix wrong STM32_CORE_VERSION_MINOR. Signed-off-by: patricklaf --- libraries/SrcWrapper/inc/stm32_def.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index 82c8591178..aaf37ad69a 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -6,7 +6,7 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x11U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_MINOR (0x0BU) /*!< [23:16] minor version */ #define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: From e3c33304dc8c618d802355537509ce6a34a1346c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 19 Mar 2025 08:41:06 +0100 Subject: [PATCH 03/22] fix(f7): PLLR value Fixes #2692. Signed-off-by: Frederic Pillon --- .../F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/generic_clock.c | 1 + .../variant_REMRAM_V1.cpp | 1 + .../STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/generic_clock.c | 1 + .../F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp | 1 + 4 files changed, 4 insertions(+) diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/generic_clock.c b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/generic_clock.c index a675f0dd34..13caca1302 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/generic_clock.c +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/generic_clock.c @@ -44,6 +44,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; + RCC_OscInitStruct.PLL.PLLR = 2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/variant_REMRAM_V1.cpp b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/variant_REMRAM_V1.cpp index f5cc7298c8..73e1425990 100644 --- a/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/variant_REMRAM_V1.cpp +++ b/variants/STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T)/variant_REMRAM_V1.cpp @@ -172,6 +172,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; + RCC_OscInitStruct.PLL.PLLR = 2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/generic_clock.c b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/generic_clock.c index 6a6389377e..738c40f096 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/generic_clock.c +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/generic_clock.c @@ -42,6 +42,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; + RCC_OscInitStruct.PLL.PLLR = 2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp index 4ccba6b65d..c0f7688f94 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp @@ -212,6 +212,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; + RCC_OscInitStruct.PLL.PLLR = 2; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } From 1ef1f862c81257c73d046a957194e3c541653988 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 19 Mar 2025 08:42:06 +0100 Subject: [PATCH 04/22] chore(f7): use HSE bypass for Nucleo-F767ZI instead of HSI. Signed-off-by: Frederic Pillon --- .../variant_NUCLEO_F767ZI.cpp | 23 +++---------------- 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp index c0f7688f94..b7edea0f36 100644 --- a/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp +++ b/variants/STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT/variant_NUCLEO_F767ZI.cpp @@ -171,23 +171,6 @@ extern "C" { /** * @brief System Clock Configuration - * The system Clock is configured as follow : - * System Clock source = PLL (HSI) - * SYSCLK(Hz) = 216000000 - * HCLK(Hz) = 216000000 - * AHB Prescaler = 1 - * APB1 Prescaler = 4 - * APB2 Prescaler = 2 - * HSE Frequency(Hz) = 16000000 - * PLL_M = 8 - * PLL_N = 216 - * PLL_P = 2 - * PLL_Q = 9 - * PLLSAI_N = 192 - * PLLSAI_P = 2 - * VDD(V) = 3.3 - * Main regulator output voltage = Scale1 mode - * Flash Latency(WS) = 7 * @param None * @retval None */ @@ -203,12 +186,12 @@ WEAK void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Initializes the CPU, AHB and APB busses clocks */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; RCC_OscInitStruct.HSICalibrationValue = 16; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 216; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; From 875fe4c29e20c37385d7e00fc3adee8e39f5712e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 25 Mar 2025 10:33:39 +0100 Subject: [PATCH 05/22] system(l0) update STM32L0xx HAL Drivers to v1.10.7 Included in STM32CubeL0 FW v1.12.3 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 152 ++++-- .../Inc/stm32l0xx_hal_cortex.h | 3 +- .../Inc/stm32l0xx_hal_crc.h | 2 +- .../Inc/stm32l0xx_hal_i2c.h | 2 - .../Inc/stm32l0xx_hal_i2s.h | 4 +- .../Inc/stm32l0xx_hal_lptim.h | 4 +- .../Inc/stm32l0xx_hal_pcd.h | 21 +- .../Inc/stm32l0xx_hal_pcd_ex.h | 1 - .../Inc/stm32l0xx_hal_rcc.h | 4 +- .../Inc/stm32l0xx_hal_rng.h | 6 +- .../Inc/stm32l0xx_hal_rtc.h | 2 +- .../Inc/stm32l0xx_hal_rtc_ex.h | 62 +-- .../Inc/stm32l0xx_hal_smbus.h | 2 - .../Inc/stm32l0xx_hal_spi.h | 46 +- .../Inc/stm32l0xx_hal_tim.h | 43 +- .../Inc/stm32l0xx_hal_uart.h | 8 +- .../Inc/stm32l0xx_hal_uart_ex.h | 2 +- .../Inc/stm32l0xx_hal_usart.h | 1 - .../Inc/stm32l0xx_hal_usart_ex.h | 2 +- .../Inc/stm32l0xx_ll_adc.h | 3 +- .../Inc/stm32l0xx_ll_cortex.h | 2 +- .../Inc/stm32l0xx_ll_crc.h | 20 +- .../Inc/stm32l0xx_ll_i2c.h | 9 +- .../Inc/stm32l0xx_ll_rng.h | 18 +- .../Inc/stm32l0xx_ll_rtc.h | 24 +- .../Inc/stm32l0xx_ll_spi.h | 153 +++--- .../Inc/stm32l0xx_ll_tim.h | 14 +- .../Inc/stm32l0xx_ll_usb.h | 31 +- .../Inc/stm32l0xx_ll_utils.h | 2 +- .../{License.md => LICENSE.md} | 0 .../STM32L0xx_HAL_Driver/Release_Notes.html | 199 +++++-- .../STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c | 2 +- .../Src/stm32l0xx_hal_adc.c | 13 +- .../Src/stm32l0xx_hal_adc_ex.c | 29 +- .../Src/stm32l0xx_hal_cortex.c | 90 ++-- .../Src/stm32l0xx_hal_crc.c | 2 +- .../Src/stm32l0xx_hal_crc_ex.c | 2 - .../Src/stm32l0xx_hal_cryp.c | 56 +- .../Src/stm32l0xx_hal_dac_ex.c | 53 +- .../Src/stm32l0xx_hal_exti.c | 4 +- .../Src/stm32l0xx_hal_flash.c | 8 +- .../Src/stm32l0xx_hal_flash_ex.c | 8 +- .../Src/stm32l0xx_hal_gpio.c | 2 +- .../Src/stm32l0xx_hal_i2c.c | 504 ++++++++++++++---- .../Src/stm32l0xx_hal_i2s.c | 82 ++- .../Src/stm32l0xx_hal_irda.c | 10 +- .../Src/stm32l0xx_hal_pcd.c | 103 ++-- .../Src/stm32l0xx_hal_pcd_ex.c | 2 - .../Src/stm32l0xx_hal_rcc.c | 10 +- .../Src/stm32l0xx_hal_rng.c | 21 +- .../Src/stm32l0xx_hal_rtc.c | 128 ++--- .../Src/stm32l0xx_hal_rtc_ex.c | 40 +- .../Src/stm32l0xx_hal_smartcard.c | 12 +- .../Src/stm32l0xx_hal_smbus.c | 51 +- .../Src/stm32l0xx_hal_smbus_ex.c | 2 + .../Src/stm32l0xx_hal_spi.c | 473 ++++++++-------- .../Src/stm32l0xx_hal_tim.c | 80 +-- .../Src/stm32l0xx_hal_uart.c | 264 +++++---- .../Src/stm32l0xx_hal_uart_ex.c | 91 ++-- .../Src/stm32l0xx_hal_usart.c | 26 +- .../Src/stm32l0xx_ll_crc.c | 2 +- .../Src/stm32l0xx_ll_rng.c | 2 +- .../Src/stm32l0xx_ll_spi.c | 9 +- .../Src/stm32l0xx_ll_tim.c | 3 +- .../Src/stm32l0xx_ll_usb.c | 120 +++-- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 66 files changed, 1942 insertions(+), 1206 deletions(-) rename system/Drivers/STM32L0xx_HAL_Driver/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index e910b93084..77f0ab3c8f 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2023 STMicroelectronics. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -279,7 +275,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -476,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -540,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -552,6 +554,16 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -595,6 +607,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -800,6 +821,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -854,6 +890,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -991,8 +1031,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1243,10 +1283,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1258,27 +1298,27 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1445,7 +1485,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1599,6 +1639,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1809,7 +1851,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1991,12 +2033,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2311,8 +2353,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2345,8 +2387,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2403,8 +2445,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2421,7 +2463,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2723,6 +2765,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3646,8 +3694,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3749,8 +3801,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3896,7 +3950,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || \ + defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3931,6 +3986,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -4183,6 +4245,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ @@ -4212,6 +4301,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h index ec7ca51517..8494671dc0 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h @@ -261,6 +261,8 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1U) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** @@ -361,4 +363,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); - diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h index 284740558e..d9544b4e23 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_crc.h @@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h index 0376a42b32..4f55b941bf 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h index 4e9cd3208b..16082d7153 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2s.h @@ -452,8 +452,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h index decdde9af5..38d8058f1e 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_lptim.h @@ -390,6 +390,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ @@ -732,9 +733,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h index f3bf6290fd..9a297f7188 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd.h @@ -339,7 +339,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); /** * @} */ @@ -348,7 +348,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions * @{ */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); /** * @} */ @@ -806,20 +806,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); \ *(pdwReg) &= 0x3FFU; \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h index 1bb4f2830f..0061e2a068 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h index ce181c1dd7..d0223c3126 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h @@ -1686,8 +1686,8 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h index f18f89b1d1..759c5451b7 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rng.h @@ -304,7 +304,7 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -317,8 +317,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h index 91f7654bb0..0a6ccb9355 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc.h @@ -813,7 +813,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_TIMEOUT_VALUE 1000U -#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 connected to the RTC Alarm event */ /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h index d1b03ef85b..7f5d2cfd85 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rtc_ex.h @@ -60,7 +60,7 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ uint32_t Filter; /*!< Specifies the RTC Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ @@ -641,11 +641,11 @@ typedef struct * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: Tamper global interrupt - * @arg RTC_IT_TAMP1: Tamper 1 interrupt + * @arg RTC_IT_TAMP1: Tamper 1 interrupt (*) * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @note RTC_IT_TAMP1 is not applicable to all devices. - * @note RTC_IT_TAMP3 is not applicable to all devices. + * @arg RTC_IT_TAMP3: Tamper 3 interrupt (*) + * + * (*) value not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) @@ -656,40 +656,26 @@ typedef struct * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TAMP: Tamper global interrupt - * @arg RTC_IT_TAMP1: Tamper 1 interrupt + * @arg RTC_IT_TAMP1: Tamper 1 interrupt (*) * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @note RTC_IT_TAMP1 is not applicable to all devices. - * @note RTC_IT_TAMP3 is not applicable to all devices. + * @arg RTC_IT_TAMP3: Tamper 3 interrupt (*) + * + * (*) value not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper 1 interrupt - * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @note RTC_IT_TAMP1 is not applicable to all devices. - * @note RTC_IT_TAMP3 is not applicable to all devices. - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) - /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: Tamper global interrupt - * @arg RTC_IT_TAMP1: Tamper 1 interrupt + * @arg RTC_IT_TAMP1: Tamper 1 interrupt (*) * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @note RTC_IT_TAMP1 is not applicable to all devices. - * @note RTC_IT_TAMP3 is not applicable to all devices. + * @arg RTC_IT_TAMP3: Tamper 3 interrupt (*) + * + * (*) value not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) @@ -699,11 +685,11 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Tamper flag to be checked. * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag (*) * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag - * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag - * @note RTC_FLAG_TAMP1F is not applicable to all devices. - * @note RTC_FLAG_TAMP3F is not applicable to all devices. + * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag (*) + * + * (*) value not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) @@ -713,11 +699,11 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag (*) * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag - * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag - * @note RTC_FLAG_TAMP1F is not applicable to all devices. - * @note RTC_FLAG_TAMP3F is not applicable to all devices. + * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag (*) + * + * (*) value not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) @@ -746,13 +732,13 @@ typedef struct * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. @@ -947,7 +933,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); * @{ */ /* Extended RTC features functions *******************************************/ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h index aea09a4bbe..cb37a09b3d 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h index 6f870f537a..ce8e4708be 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_spi.h @@ -107,7 +107,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -339,11 +339,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -444,7 +445,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -488,8 +489,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -505,7 +509,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -517,7 +521,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -627,7 +631,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -673,17 +677,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -709,8 +713,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h index 1f0a370e6d..f908f8e6fc 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h @@ -318,27 +318,26 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ } HAL_TIM_CallbackIDTypeDef; @@ -1567,12 +1566,13 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__);\ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__);\ + } while(0) /** * @} @@ -1750,7 +1750,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h index baf4bf75d9..252c9bd730 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ck) / ((huart->Init.BaudRate))) - where lpuart_ker_ck is the UART input clock - UART: - ===== + where lpuart_ker_ck is the UART input clock. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) - If oversampling is 8, diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h index 955e87011c..7998e5c576 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h @@ -136,7 +136,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /** diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h index f0a82e92e6..8173da4e1a 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart.h @@ -463,7 +463,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) - /** @brief Enable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. * @param __INTERRUPT__ specifies the USART interrupt source to enable. diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h index f199f1a175..c4475d6d48 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_usart_ex.h @@ -45,7 +45,7 @@ extern "C" { * @{ */ #define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ #define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h index 7e62d17679..5a598e09b2 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_adc.h @@ -3535,8 +3535,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) /** * @brief Get ADC group regular conversion data, range fit for * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). + * features extending data width (oversampling, data shift,...). * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h index c27df301a3..b355065ecf 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h @@ -537,7 +537,7 @@ __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisa /* Set base address */ WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); /* Configure MPU */ - WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); } /** diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h index b258254ccc..f2d1b02928 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crc.h @@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi * @arg @ref LL_CRC_POLYLENGTH_8B * @arg @ref LL_CRC_POLYLENGTH_7B */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); } @@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD * @arg @ref LL_CRC_INDATA_REVERSE_WORD */ -__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); } @@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT */ -__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); } @@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) * @param CRCx CRC Instance * @retval Value programmed in Programmable initial CRC value register */ -__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->INIT)); } @@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno * @param CRCx CRC Instance * @retval Value programmed in Programmable Polynomial value register */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->POL)); } @@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). */ -__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) { return (uint16_t)READ_REG(CRCx->DR); } @@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) { return (uint8_t)READ_REG(CRCx->DR); } @@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) { return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); } @@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @} diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h index d9d9e210d3..fe27c5cf73 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h @@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); + tmp); } /** diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h index 94bfd8da3d..ad5a0e4aa7 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rng.h @@ -146,7 +146,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -165,7 +165,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -176,7 +176,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -187,7 +187,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -198,7 +198,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -209,7 +209,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -275,7 +275,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -294,7 +294,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -307,7 +307,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h index 5f9f734f01..b44cd0eacc 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rtc.h @@ -414,8 +414,8 @@ typedef struct /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE * @{ */ -#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ -#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */ /** * @} */ @@ -1050,7 +1050,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1084,7 +1084,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1119,7 +1119,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1154,7 +1154,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1204,7 +1204,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1346,7 +1346,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll DR YT LL_RTC_DATE_GetYear\n @@ -1380,7 +1380,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1427,7 +1427,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll DR MT LL_RTC_DATE_GetMonth\n @@ -1469,7 +1469,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll DR DT LL_RTC_DATE_GetDay\n @@ -1531,7 +1531,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h index a3da1e18de..c44f3f5cc7 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -317,7 +330,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -347,7 +360,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -375,7 +388,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -404,7 +417,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -433,7 +446,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -473,7 +486,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -501,7 +514,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -538,7 +551,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -565,7 +578,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_8BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); } @@ -609,7 +622,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -644,7 +657,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -655,7 +668,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -666,7 +679,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -707,7 +720,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -728,7 +741,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -739,7 +752,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -750,7 +763,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -761,7 +774,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -772,7 +785,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -790,7 +803,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -801,7 +814,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -841,7 +854,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -857,7 +870,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -874,7 +887,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -908,7 +922,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -946,7 +961,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -957,7 +972,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -968,7 +983,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1009,7 +1024,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1042,7 +1057,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1053,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1130,7 +1145,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1398,7 +1413,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1431,7 +1446,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1458,7 +1473,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1493,7 +1508,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1524,7 +1539,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1547,7 +1562,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1574,7 +1589,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1607,7 +1622,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1641,7 +1656,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); } @@ -1661,7 +1676,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1672,7 +1687,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1683,7 +1698,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1694,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1705,7 +1720,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1716,7 +1731,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1730,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -1752,7 +1767,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1765,7 +1780,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -1852,7 +1867,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -1863,7 +1878,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -1874,7 +1889,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -1915,7 +1930,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -1948,7 +1963,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -1993,7 +2008,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h index 7bb11b4b25..8913e61db2 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h +++ b/system/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h @@ -364,10 +364,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!Purpose

Update History

- +

Main Changes

    @@ -49,6 +49,135 @@

    Main Changes

Contents

    +
  • HAL GPIO update +
      +
    • Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition.
      • +
    • +
  • HAL RCC update +
      +
    • Remove unnecessary uint64_t in HAL_RCC_GetSysClockFreq() API.
      • +
    • +
  • HAL FLASH update +
      +
    • Add UNUSED() macro to avoid the generation of a warning related to the unused argument ‘TypeProgram’.
      • +
    • Fix UNUSED_VALUE Coverity warnings.
      • +
    • +
  • HAL/LL CORTEX update +
      +
    • Update HAL_MPU_ConfigRegion() API to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
      • +
    • Add new HAL_MPU_EnableRegion()/ HAL_MPU_DisableRegion() APIs.
      • +
    • Add UNUSED() macro to avoid the generation of a warning related to the unused argument ‘SubPriority’.
      • +
    • Add missing parenthesis() in LL_MPU_ConfigRegion() API.
      • +
    • +
  • LL UTILS update +
      +
    • Fix a note about Ticks parameter.
      • +
    • +
  • HAL CRYP update +
      +
    • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment.
      • +
    • +
  • HAL/LL ADC update +
      +
    • Update LL_ADC_DeInit() API to remove useless action of conversion trigger change.
      • +
    • Add UNUSED() macro to avoid the generation of a warning related to the unused argument ‘SingleDiff’.
      • +
    • Update description field in HAL_ADCEx_EnableVREFINT() and HAL_ADCEx_EnableVREFINTTempSensor() APIs.
      • +
    • Update description of LL_ADC_REG_ReadConversionData32() API.
      • +
    • Fix “Unchecked return value” Coverity warnings.
      • +
    • +
  • HAL DAC update +
      +
    • Fix “Unchecked return value” Coverity warnings.
      • +
    • +
  • HAL/LL TIM update +
      +
    • Remove multiple volatile reads or writes in interrupt handler for better performance.
      • +
    • HAL TIM driver’s operational behavior improvement.
      • +
    • Update interrupt flag (UIF) is cleared when the update event is generated by software.
      • +
    • +
  • HAL/LL LPTIM update +
      +
    • Remove redundant IS_LPTIM_AUTORELOAD() macro.
      • +
    • +
  • HAL/LL RTC BKP update +
      +
    • Remove macro __HAL_RTC_TAMPER_GET_IT() as it is redundant with macro __HAL_RTC_TAMPER_GET_FLAG() and create an alias into the hal_legacy.h file.
      • +
    • Expand the cast of ‘RTC_CR_BYPSHAD’ to 32 bits when writing to the CR register in HAL_RTCEx_DisableBypassShadow() API to avoid overwriting its upper bits.
      • +
    • Correct misleading note about shadow registers.
      • +
    • +
  • HAL UART update +
      +
    • Update initialization sequence for TXINV, RXINV and TXRXSWAP settings.
      • +
    • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback()/HAL_UART_UnRegisterRxEventCallback() to allow user Rx Event Callback registration when a transmit is ongoing.
      • +
    • Avoid RTOF flag to be cleared by a transmit process in polling mode.
      • +
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode.
      • +
    • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() API use with Circular DMA, even if occurring just after TC event.
      • +
    • Correct references to HAL_UARTEx_WakeupCallback() API and to HAL_UART_WAKEUP_CB_ID define, according to series capabilities.
      • +
    • Provide accurate position in RxEventCallback() when ReceptionToIdle mode is used with DMA, when UART and DMA interrupts process is delayed.
      • +
    • +
  • HAL USART update +
      +
    • Improve the visibility of the SPI mode capability in HAL USART description.
      • +
    • +
  • HAL/LL I2C update +
      +
    • Update HAL I2C driver to prefetch data before starting the transmission: +
        +
      • Implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte.
        • +
      • +
    • Update HAL I2C driver to disable all interrupts after end of transaction.
      • +
    • Update HAL_I2C_Init() API to clear ADD10 bit in 7 bit addressing mode.
      • +
    • Update HAL_I2C_Mem_Write_IT() API to initialize XferSize at 0.
      • +
    • Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() to prevent the call of HAL_I2C_ListenCpltCallback() twice.
      • +
    • Update I2C_WaitOnRXNEFlagUntilTimeout() to check I2C_FLAG_AF independently from I2C_FLAG_RXNE.
      • +
    • Remove the unusable code in HAL_I2C_IsDeviceReady() API.
      • +
    • Update I2C_WaitOnFlagUntilTimeout() to handle error case.
      • +
    • Update the HAL I2C driver to implement the errata workaround “Last-received byte loss in reload mode”.
      • +
    • Update HAL_I2C_Slave_Transmit() API to check if the received NACK is the good one.
      • +
    • Update LL_I2C_HandleTranfer() API to prevent undefined behavior of volatile usage before updating the CR2 register.
      • +
    • Move the prefetch process in HAL_I2C_Slave_Transmit() API.
      • +
    • Add abort memory management to HAL_I2C_Master_Abort_IT() API.
      • +
    • Add a temporary variable to get the value to check before comparison.
      • +
    • +
  • HAL SMBUS update +
      +
    • Update HAL SMBUS driver to prefetch data before starting the transmission: +
        +
      • Implementation of errata sheet workaround I2C2-190208: Transmission stalled after first byte.
        • +
      • +
    • Update SMBUS_ITErrorHandler() to flush TXDR just in case of error.
      • +
    • +
  • HAL SPI update +
      +
    • Update HAL_SPI_TransmitReceive() API to set the bit CRCNEXT in case of one byte transaction.
      • +
    • Update IT API to enable interrupts after process unlock.
      • +
    • Add note to clarify HAL_SPI_Receive() API behavior in master mode.
      • +
    • Add units to physical measurements.
      • +
    • Add wait on flag TXE to be set at the end of transaction to be aligned with reference manual.
      • +
    • Check data size before changing state in reception API.
      • +
    • Fix “INTEGER_OVERFLOW” Coverity warning.
      • +
    • +
  • HAL I2S update +
      +
    • Remove ‘go to’ instruction to fix the Misra-C:2012 Advisory Rule15.1.
      • +
    • +
  • HAL USB_FS update +
      +
    • hal_pcd.c/ll_usb.c: fix added to support bulk transfer in double buffer mode.
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and enhancements implementation.
    • +
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
    • +
+

Contents

+
  • HAL/LL Generic update
    • Allow redefinition of macro UNUSED(x).
      • @@ -205,11 +334,11 @@

      Contents

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and enhancements implementation
      -

      Contents

      +

      Contents

      • HAL updates
          @@ -293,7 +422,7 @@

          Contents

          -

          Main Changes

          +

          Main Changes

          • General updates to fix known defects and enhancements implementation
          • Add new HAL EXTI driver
            • @@ -302,7 +431,7 @@

            Main Changes

          • Correct MISRA-C 2012: Rule-10.5, Rule-10.4_a, Rule-2.7 and Rule-21.1
          • Remove useless casts
          -

          Contents

          +

          Contents

          • HAL driver
              @@ -556,11 +685,11 @@

              Contents

              -

              Main Changes

              +

              Main Changes

              • General updates to fix known defects and enhancements implementation
              -

              Contents

              +

              Contents

              • HAL Generic update
                  @@ -604,13 +733,13 @@

                  Contents

                  -

                  Main Changes

                  +

                  Main Changes

                  Patch release

                  • Update of HAL driver to include latest corrections and ensure compatibility with legacy code.
                  • The V1.10.2 version contains all the updates implemented in V1.10.1 version. For more details, please refer to the History.
                  -

                  Contents

                  +

                  Contents

                  • HAL
                      @@ -626,12 +755,12 @@

                      Contents

                      -

                      Main Changes

                      +

                      Main Changes

                      Patch release

                      • Update of HAL FLASH, RCC and SPI drivers to include latest corrections
                      -

                      Contents

                      +

                      Contents

                      • HAL RCC
                          @@ -652,7 +781,7 @@

                          Contents

                          -

                          Main Changes

                          +

                          Main Changes

                          Major maintenance release

                          • Add support of new L0 Value Line devices
                            • @@ -660,7 +789,7 @@

                            Major maintenance release

                          • Add several enhancements implementation
                          • Fix known defects to be aligned with others STM32 series
                          -

                          Contents

                          +

                          Contents

                          • HAL/LL generic
                              @@ -944,16 +1073,16 @@

                              Contents

                              -

                              Main Changes

                              +

                              Main Changes

                              Internal release

                              -

                              Main Changes

                              +

                              Main Changes

                              Maintenance release

                              -

                              Contents

                              +

                              Contents

                              • HAL/LL generic
                                  @@ -985,9 +1114,9 @@

                                  Contents

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  Patch release

                                  -

                                  Contents

                                  +

                                  Contents

                                  • HAL LCD
                                      @@ -999,9 +1128,9 @@

                                      Contents

                                      -

                                      Main Changes

                                      +

                                      Main Changes

                                      Maintenance release

                                      -

                                      Contents

                                      +

                                      Contents

                                      • HAL generic
                                          @@ -1142,9 +1271,9 @@

                                          Contents

                                          -

                                          Main Changes

                                          +

                                          Main Changes

                                          Maintenance release

                                          -

                                          Contents

                                          +

                                          Contents

                                          • HAL/LL COMP update
                                              @@ -1177,7 +1306,7 @@

                                              Contents

                                              -

                                              Main Changes

                                              +

                                              Main Changes

                                              Maintenance release

                                              • First official release supporting the Low Level drivers for the STM32L0xx family: @@ -1187,7 +1316,7 @@

                                                Maintenance release

                                              • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32l0xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32l0xx_ll_ppp.h file must be included in user code.
                                            -

                                            Contents

                                            +

                                            Contents

                                            • Updates of the HAL
                                                @@ -1249,9 +1378,9 @@

                                                Contents

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                Maintenance release

                                                -

                                                Contents

                                                +

                                                Contents

                                                • Main HAL updates
                                                    @@ -1320,7 +1449,7 @@

                                                    Contents

                                                    -

                                                    Main Changes

                                                    +

                                                    Main Changes

                                                    Maintenance release

                                                    • This release includes the support of the support of STM32L011xx and STM32L021xx devices
                                                      • @@ -1332,7 +1461,7 @@

                                                      Maintenance release

                                                    • Timers available : TIM2,TIM21,LPTIM1 (instead of TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)
                                                  -

                                                  Contents

                                                  +

                                                  Contents

                                                  • HAL COMP update
                                                      @@ -1362,7 +1491,7 @@

                                                      Contents

                                                      -

                                                      Main Changes

                                                      +

                                                      Main Changes

                                                      Major maintenance release

                                                      • Major update of the HAL API : @@ -1379,7 +1508,7 @@

                                                        Major maintenance release

                                                      • Timers available : TIM2,TIM21,TIM22,LPTIM1 (instead of TIM2,TIM3,TIM6,TIM7,TIM21,TIM22,LPTIM1)
                                                    -

                                                    Contents

                                                    +

                                                    Contents

                                                    • HAL ADC update
                                                        @@ -1599,13 +1728,13 @@

                                                        Contents

                                                        -

                                                        Main Changes

                                                        +

                                                        Main Changes

                                                        Official release

                                                        • This release includes the support of the STM32L071xx, STM32L072xx, STM32L073xx, STM32L082xx, STM32L083xx devices
                                                        • Fix known defects and add several enhancements implementation
                                                        -

                                                        Contents

                                                        +

                                                        Contents

                                                        • HAL Flash** update
                                                            @@ -1644,9 +1773,9 @@

                                                            Known Limitations

                                                            -

                                                            Main Changes

                                                            +

                                                            Main Changes

                                                            Official release

                                                            -

                                                            Contents

                                                            +

                                                            Contents

                                                            • HAL generic** update
                                                                @@ -1858,7 +1987,7 @@

                                                                Contents

                                                                -

                                                                Main Changes

                                                                +

                                                                Main Changes

                                                                First official release

                                                                diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c index f1733d6528..2fe2915598 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c @@ -59,7 +59,7 @@ */ #define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32L0xx_HAL_VERSION_SUB1 (0x0AU) /*!< [23:16] sub1 version */ -#define __STM32L0xx_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ +#define __STM32L0xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ #define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\ |(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c index a02b8bd903..24fc1d275c 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc.c @@ -134,12 +134,6 @@ monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). - - (#) When device is in mode low-power (low-power run, low-power sleep or stop mode), - function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init(). - In case of internal temperature sensor to be measured: - function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly - *** Execution of ADC conversions *** ==================================== [..] @@ -382,11 +376,6 @@ static void ADC_DelayMicroSecond(uint32_t microSecond); * @note This function configures the ADC within 2 scopes: scope of entire * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". - * @note When device is in mode low-power (low-power run, low-power sleep or stop mode), - * function "HAL_ADCEx_EnableVREFINT()" must be called before function HAL_ADC_Init() - * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first). - * In case of internal temperature sensor to be measured: - * function "HAL_ADCEx_EnableVREFINTTempSensor()" must be called similarilly. * @param hadc ADC handle * @retval HAL status */ @@ -1552,7 +1541,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, ui __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c index 56a3fb7236..a9d225655d 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_adc_ex.c @@ -110,6 +110,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(SingleDiff); + /* Process locked */ __HAL_LOCK(hadc); @@ -192,6 +195,9 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(SingleDiff); + /* Return the ADC calibration value */ return ((hadc->Instance->CALFACT) & 0x0000007FU); } @@ -214,6 +220,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(SingleDiff); + /* Process locked */ __HAL_LOCK(hadc); @@ -246,11 +255,11 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32 /** * @brief Enables the buffer of Vrefint for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode) - * This function must be called before function HAL_ADC_Init() - * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first) + * However ADC is not functional in low-power mode, therefore these functions is not targeted for ADC (obsolete) * For more details on procedure and buffer current consumption, refer to device reference manual. * @note This is functional only if the LOCK is not set. - * @note This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel(). + * @note This API is obsolete. This equivalent configuration is done in HAL_ADC_ConfigChannel(). + bit fields in ADC_CCR and SYSCFG_CFGR3 control the same signals to VREFINT and TempSensor buffers * @retval None */ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void) @@ -282,7 +291,8 @@ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void) /** * @brief Disables the Buffer Vrefint for the ADC. * @note This is functional only if the LOCK is not set. - * @note This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel(). + * @note This API is obsolete. This equivalent configuration is done in HAL_ADC_ConfigChannel(). + bit fields in ADC_CCR and SYSCFG_CFGR3 control the same signals to VREFINT and TempSensor buffers. * @retval None */ void HAL_ADCEx_DisableVREFINT(void) @@ -292,12 +302,12 @@ void HAL_ADCEx_DisableVREFINT(void) } /** - * @brief Enables the buffer of temperature sensor for the ADC, required when device is in mode low-power (low-power run, low-power sleep or stop mode) - * This function must be called before function HAL_ADC_Init() - * (in case of previous ADC operations: function HAL_ADC_DeInit() must be called first) + * @brief Enables the buffer of temperature sensor, when device is in mode low-power (low-power run, low-power sleep or stop mode) + * However ADC is not functional in low-power mode, therefore these functions is not targeted for ADC (obsolete) * For more details on procedure and buffer current consumption, refer to device reference manual. * @note This is functional only if the LOCK is not set. - * @note This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel(). + * @note This API is obsolete. This equivalent configuration is done in HAL_ADC_ConfigChannel(). + bit fields in ADC_CCR and SYSCFG_CFGR3 control the same signals to VREFINT and TempSensor buffers * @retval None */ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void) @@ -329,7 +339,8 @@ HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void) /** * @brief Disables the VREFINT and Sensor for the ADC. * @note This is functional only if the LOCK is not set. - * @note This API is obsolete. This configuration is done in HAL_ADC_ConfigChannel(). + * @note This API is obsolete. This equivalent configuration is done in HAL_ADC_ConfigChannel(). + bit fields in ADC_CCR and SYSCFG_CFGR3 control the same signals to VREFINT and TempSensor buffers. * @retval None */ void HAL_ADCEx_DisableVREFINTTempSensor(void) diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c index ca92c22195..c36ae2b0bf 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c @@ -133,6 +133,10 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn,PreemptPriority); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(SubPriority); + } /** @@ -345,9 +349,41 @@ void HAL_MPU_Enable(uint32_t MPU_Control) } +/** + * @brief Enable the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disable the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + /** * @brief Initialize and configure the Region and the memory to be protected. - * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ @@ -356,42 +392,30 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) /* Check the parameters */ assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ - __DMB(); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); /* Set the Region number */ MPU->RNR = MPU_Init->Number; - if ((MPU_Init->Enable) == MPU_REGION_ENABLE) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - /* Set the base adsress and set the 4 LSB to 0 */ - MPU->RBAR = (MPU_Init->BaseAddress) & 0xfffffff0U; - - /* Fill the field RASR */ - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00U; - MPU->RASR = 0x00U; - } + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); } #endif /* __MPU_PRESENT */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c index 763cfc03ac..cb2cdcc4c0 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc.c @@ -403,7 +403,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t * @param hcrc CRC handle * @retval HAL state */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) { /* Return CRC handle state */ return hcrc->State; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c index 70f2890e3f..f5e130c6d5 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_crc_ex.c @@ -210,8 +210,6 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_ } - - /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c index 16e104a1a9..24d64a72b8 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cryp.c @@ -823,6 +823,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Get the last input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -831,8 +837,6 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -912,6 +916,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Get the last input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -920,8 +930,6 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1001,6 +1009,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Get the last input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -1009,8 +1023,6 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1087,6 +1099,12 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Get the last input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -1095,8 +1113,6 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1176,6 +1192,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Get the last input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -1184,8 +1206,6 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1265,6 +1285,12 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Get the last input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -1273,8 +1299,6 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; /* Return function status */ return HAL_OK; @@ -1922,6 +1946,12 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) /* Get the last Input data address */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ + hcryp->pCrypInBuffPtr += 16U; + hcryp->CrypInCount -= 16U; + /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; @@ -1930,8 +1960,6 @@ static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4U; hcryp->Instance->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16U; - hcryp->CrypInCount -= 16U; } return HAL_OK; } diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c index 4107d6b3cd..c87236ff39 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dac_ex.c @@ -389,6 +389,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { + HAL_StatusTypeDef status; uint32_t tmpreg = 0U; /* Check the parameters */ @@ -426,14 +427,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } - UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + UNUSED(tmpreg); /* avoid warning on tmpreg affectation */ } else { @@ -460,12 +459,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Get DHR12L2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L2; break; - case DAC_ALIGN_8B_R: + default: /* case DAC_ALIGN_8B_R */ /* Get DHR8R2 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R2; break; - default: - break; } } @@ -476,7 +473,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else { @@ -484,17 +481,23 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } - /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, Channel); - /* Process Unlocked */ __HAL_UNLOCK(hdac); + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -734,6 +737,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { + HAL_StatusTypeDef status; uint32_t tmpreg = 0U; /* Check the parameters */ @@ -769,30 +773,35 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u /* Get DHR12L1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR12L1; break; - case DAC_ALIGN_8B_R: + default: /* Get DHR8R1 address */ tmpreg = (uint32_t)&hdac->Instance->DHR8R1; break; - default: - break; } - UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + UNUSED(tmpreg); /* avoid warning on tmpreg affectation */ - /* Enable the DMA Stream */ /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, Channel); - /* Process Unlocked */ __HAL_UNLOCK(hdac); + if (status == HAL_OK) + { + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } + /* Return function status */ - return HAL_OK; + return status; } /** diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c index 958d97953b..4319b6253a 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c @@ -64,7 +64,7 @@ (++) Provide exiting handle as parameter. (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). (++) Provide exiting handle as parameter. (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). @@ -75,7 +75,7 @@ (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c index 4ccd33c04a..163a160584 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c @@ -227,7 +227,7 @@ static void FLASH_SetErrorCode(void); */ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; /* Process Locked */ __HAL_LOCK(&pFlash); @@ -236,6 +236,9 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(TypeProgram); + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); @@ -278,6 +281,9 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + /* Prevent unused argument(s) compilation warning */ + UNUSED(TypeProgram); + /* Enable End of FLASH Operation and Error source interrupts */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c index ad33fd132f..eb6c4f2744 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c @@ -165,7 +165,7 @@ static uint32_t FLASH_OB_GetWRP2(void); */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; uint32_t address = 0U; /* Process Locked */ @@ -229,7 +229,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; /* If procedure already ongoing, reject the next one */ if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) @@ -716,9 +716,9 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address) * @retval HAL_StatusTypeDef HAL Status */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status; /* Process Locked */ __HAL_LOCK(&pFlash); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c index 1aeae7465f..0bba1c13df 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c @@ -447,7 +447,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * @param GPIOx where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family. * Note that GPIOE is not available on all devices. * @param GPIO_Pin specifies the port bit to be locked. -* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * All port bits are not necessarily available on all GPIOs. * @retval None */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c index 1bff29d50a..99b7b63467 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c @@ -90,7 +90,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -156,7 +156,7 @@ HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() @@ -214,7 +214,7 @@ add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. @@ -608,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /* Configure I2Cx: Addressing Master mode */ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { - hi2c->Instance->CR2 = (I2C_CR2_ADD10); + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); } /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); @@ -1115,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1138,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount = Size; hi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_WRITE); + xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); } @@ -1261,7 +1288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -1352,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData uint32_t Timeout) { uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1378,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /* Enable Address Acknowledge */ hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - /* Preload TX data if no stretch enable */ if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { @@ -1399,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; } + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1410,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1422,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + return HAL_ERROR; } @@ -1445,31 +1486,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Wait until AF flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } - return HAL_ERROR; + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Wait until BUSY flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) { @@ -1672,7 +1730,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1732,7 +1809,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; xfermode = I2C_RELOAD_MODE; } else @@ -1895,6 +1972,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hi2c->State == HAL_I2C_STATE_READY) { @@ -1927,6 +2005,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t xfermode = I2C_AUTOEND_MODE; } + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + if (hi2c->XferSize > 0U) { if (hi2c->hdmatx != NULL) @@ -1942,8 +2034,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -1964,7 +2056,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { /* Send Slave Address */ /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + xfermode, I2C_GENERATE_START_WRITE); /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -2003,7 +2096,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ @@ -2065,7 +2158,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; xfermode = I2C_RELOAD_MODE; } else @@ -2159,11 +2252,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -2612,7 +2705,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); } @@ -2650,7 +2743,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + hi2c->XferSize = 1U; I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -2728,6 +2821,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->ErrorCode = HAL_I2C_ERROR_NONE; /* Prepare transfer parameters */ + hi2c->XferSize = 0U; hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -2849,11 +2943,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; } @@ -3259,22 +3353,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); } - /* Check if the maximum allowed number of trials has been reached */ - if (I2C_Trials == Trials) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - /* Increment Trials */ I2C_Trials++; } while (I2C_Trials < Trials); @@ -3313,6 +3391,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3344,6 +3423,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3365,7 +3459,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 } /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3405,6 +3506,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3436,6 +3538,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 xfermode = hi2c->XferOptions; } + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ /* Mean Previous state is same as current state */ @@ -3471,8 +3588,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); } else { @@ -3492,7 +3609,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hi2c->XferCount -= hi2c->XferSize; @@ -3531,8 +3655,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3795,11 +3925,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); } return HAL_OK; @@ -4434,7 +4564,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) } /** - * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param DevAddress Target device address: The device 7 bits address value @@ -4443,7 +4573,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { - if (hi2c->Mode == HAL_I2C_MODE_MASTER) + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) { /* Process Locked */ __HAL_LOCK(hi2c); @@ -4842,17 +4974,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin hi2c->XferSize--; hi2c->XferCount--; } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; + if (hi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - hi2c->XferSize--; - hi2c->XferCount--; + hi2c->XferSize--; + hi2c->XferCount--; + } } else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) @@ -4863,7 +5000,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } else @@ -5018,7 +5163,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 { if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -5039,6 +5192,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5046,7 +5205,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32 if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, @@ -5103,9 +5270,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, tmpITFlags); } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5268,7 +5434,15 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } xfermode = I2C_RELOAD_MODE; } else @@ -5405,6 +5579,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Enable only Error interrupt */ I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); @@ -5413,7 +5590,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); } @@ -5447,6 +5632,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { direction = I2C_GENERATE_START_READ; @@ -5454,7 +5645,15 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3 if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, @@ -5524,9 +5723,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Call I2C Slave complete process */ I2C_ITSlaveCplt(hi2c, ITFlags); } - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) { /* Check that I2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -6125,6 +6323,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ @@ -6141,6 +6340,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } else { /* Do nothing */ @@ -6207,6 +6411,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -6624,7 +6879,15 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) /* Set the XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { - hi2c->XferSize = MAX_NBYTE_SIZE; + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } } else { @@ -6735,6 +6998,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { @@ -6846,16 +7115,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) { /* Check if an error is detected */ if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) { - return HAL_ERROR; + status = HAL_ERROR; } /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) { /* Check if an RXNE is pending */ /* Store Last receive data if any */ @@ -6863,19 +7134,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { /* Return HAL_OK */ /* The Reading of data from RXDR will be done in caller function */ - return HAL_OK; + status = HAL_OK; } - else + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); @@ -6889,12 +7155,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; } } /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) { @@ -6904,11 +7174,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } /** @@ -7103,13 +7373,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7136,13 +7406,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; } if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } @@ -7158,7 +7428,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c index b694c49e22..fa9ec69f0e 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2s.c @@ -756,15 +756,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -876,15 +875,14 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -975,15 +973,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1002,6 +999,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->TxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1012,7 +1011,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1042,15 +1040,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1069,6 +1066,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u hi2s->RxXferCount = Size; } + __HAL_UNLOCK(hi2s); + /* Enable RXNE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); @@ -1079,7 +1078,6 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u __HAL_I2S_ENABLE(hi2s); } - __HAL_UNLOCK(hi2s); return HAL_OK; } @@ -1106,15 +1104,14 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1156,12 +1153,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Tx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) @@ -1170,7 +1162,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } @@ -1197,15 +1195,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if (hi2s->State != HAL_I2S_STATE_READY) { - __HAL_UNLOCK(hi2s); return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hi2s); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -1253,12 +1250,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, return HAL_ERROR; } - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } + __HAL_UNLOCK(hi2s); /* Check if the I2S Rx request is already enabled */ if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) @@ -1267,7 +1259,13 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } - __HAL_UNLOCK(hi2s); + /* Check if the I2S is already enabled */ + if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + { + /* Enable I2S peripheral */ + __HAL_I2S_ENABLE(hi2s); + } + return HAL_OK; } @@ -1608,7 +1606,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -1619,7 +1617,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c index 3f9aadb5d9..d124a362f6 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_irda.c @@ -142,7 +142,7 @@ [..] Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -159,10 +159,10 @@ [..] By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + reset to the legacy weak functions in the HAL_IRDA_Init() and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -179,7 +179,7 @@ [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim ****************************************************************************** @@ -461,7 +461,7 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /** * @brief Register a User IRDA Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c index a2b51f0f87..525cbd6d5d 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd.c @@ -1389,7 +1389,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1404,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1481,7 +1481,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u * @param ep_addr endpoint address * @retval Data Size */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) { return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; } @@ -1621,9 +1621,18 @@ HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) */ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(ep_addr); + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); return HAL_OK; } @@ -1672,7 +1681,7 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) * @param hpcd PCD handle * @retval HAL state */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) { return hpcd->State; } @@ -1761,6 +1770,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -1781,27 +1802,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) + { + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1867,7 +1888,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -1880,6 +1900,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } @@ -1921,7 +1942,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -1997,7 +2018,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2029,11 +2050,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2083,6 +2104,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2094,10 +2121,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2128,7 +2157,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2156,6 +2185,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2168,10 +2203,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2201,7 +2238,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2210,7 +2247,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2218,13 +2255,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c index 015420d21a..57cd078671 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pcd_ex.c @@ -242,7 +242,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +278,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c index 77c88e2e28..fbcb6225a5 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c @@ -333,7 +333,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) * first and then HSE On or HSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { uint32_t tickstart; uint32_t hsi_state; @@ -854,7 +854,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * (for more details refer to section above "Initialization/de-initialization functions") * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart; HAL_StatusTypeDef status; @@ -1242,17 +1242,17 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) { /* HSE used as PLL clock source */ - pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + pllvco = (uint32_t)((HSE_VALUE * pllm) / plld); } else { if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) { - pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld); + pllvco = (uint32_t)((((HSI_VALUE >> 2)) * pllm) / plld); } else { - pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + pllvco = (uint32_t)((HSI_VALUE * pllm) / plld); } } sysclockfreq = pllvco; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c index f7515a1c7f..2f354bd570 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rng.c @@ -52,7 +52,7 @@ [..] Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak (overridden) function. HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -66,10 +66,10 @@ [..] By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak (overridden) functions: example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -86,7 +86,7 @@ [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. @endverbatim ****************************************************************************** @@ -689,15 +689,16 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; /* RNG clock error interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; rngclockerror = 1U; } - else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) { /* Update the error code */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; @@ -728,7 +729,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } /* Check RNG data ready interrupt occurred */ - if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) { /* Generate random number once, so disable the IT */ __HAL_RNG_DISABLE_IT(hrng); @@ -760,7 +761,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval random value */ -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) { return (hrng->RandomNumber); } @@ -822,7 +823,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) * the configuration information for RNG. * @retval HAL state */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) { return hrng->State; } @@ -832,7 +833,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code */ -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ return hrng->ErrorCode; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c index d7558b8c60..55a434c71f 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc.c @@ -6,8 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: * + Initialization and de-initialization functions - * + RTC Calendar (Time and Date) configuration functions - * + RTC Alarms (Alarm A and Alarm B) configuration functions + * + Calendar (Time and Date) configuration functions + * + Alarms (Alarm A and Alarm B) configuration functions * + Peripheral Control functions * + Peripheral State functions * @@ -64,7 +64,7 @@ ##### Backup Domain Access ##### ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data registers + [..] After reset, the backup domain (RTC registers and RTC backup data registers) is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the @@ -122,6 +122,12 @@ *** Callback registration *** ============================================= [..] + When the compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all + callbacks are set to the corresponding weak functions. + This is the recommended configuration in order to optimize memory/code + consumption footprint/performances. + [..] The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. @@ -131,11 +137,13 @@ (+) AlarmBEventCallback : RTC Alarm B Event callback. (+) TimeStampEventCallback : RTC Timestamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. (*) (+) Tamper2EventCallback : RTC Tamper 2 Event callback. - (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. (*) (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. + + (*) value not applicable to all devices. [..] This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -149,33 +157,31 @@ (+) AlarmBEventCallback : RTC Alarm B Event callback. (+) TimeStampEventCallback : RTC Timestamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. (*) (+) Tamper2EventCallback : RTC Tamper 2 Event callback. - (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. (*) (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. + + (*) value not applicable to all devices. [..] By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, all callbacks are set to the corresponding weak functions: - examples AlarmAEventCallback(), WakeUpTimerEventCallback(). + examples AlarmAEventCallback(), TimeStampEventCallback(). Exception done for MspInit() and MspDeInit() callbacks that are reset to the - legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only - when these callbacks are null (not registered beforehand). + legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these + callbacks are null (not registered beforehand). If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit() keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand). [..] Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit()/MspDeInit() that can be registered/unregistered + Exception done for MspInit() and MspDeInit() that can be registered/unregistered in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state. Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the Init/DeInit. - In that case first register the MspInit()/MspDeInit() user callbacks - using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() - or HAL_RTC_Init() functions. - [..] - When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all - callbacks are set to the corresponding weak functions. + In that case first register the MspInit()/MspDeInit() user callbacks using + HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() or HAL_RTC_Init() + functions. @endverbatim ****************************************************************************** @@ -444,13 +450,13 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @note HAL_RTC_TAMPER1_EVENT_CB_ID is not applicable to all devices. - * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices. + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID (*) + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Event Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Event Callback ID (*) + * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID + * + * (*) value not applicable to all devices. * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -557,13 +563,13 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @note HAL_RTC_TAMPER1_EVENT_CB_ID is not applicable to all devices. - * @note HAL_RTC_TAMPER3_EVENT_CB_ID is not applicable to all devices. + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Event Callback ID (*) + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Event Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Event Callback ID (*) + * @arg @ref HAL_RTC_MSPINIT_CB_ID MSP Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID MSP DeInit callback ID + * + * (*) value not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -1072,7 +1078,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); @@ -1105,7 +1111,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t) sAlarm->AlarmMask)); @@ -1118,16 +1124,15 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A */ + /* Disable Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - /* Clear the Alarm flag */ + /* Clear Alarm A flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* Get tick */ @@ -1150,21 +1155,22 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } } + /* Configure Alarm A register */ hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Subseconds register */ + /* Configure Alarm A Subseconds register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm A */ __HAL_RTC_ALARMA_ENABLE(hrtc); } else { - /* Disable the Alarm B */ + /* Disable Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - /* Clear the Alarm flag */ + /* Clear Alarm B flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* Get tick */ @@ -1187,10 +1193,11 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } } + /* Configure Alarm B register */ hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Subseconds register */ + /* Configure Alarm B Subseconds register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm B */ __HAL_RTC_ALARMB_ENABLE(hrtc); } @@ -1269,7 +1276,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); @@ -1302,7 +1309,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t) sAlarm->AlarmMask)); @@ -1315,13 +1322,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Alarm register */ if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A */ + /* Disable Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* Clear the Alarm flag */ + /* Clear Alarm A flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ @@ -1342,20 +1348,21 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U); + /* Configure Alarm A register */ hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Subseconds register */ + /* Configure Alarm A Subseconds register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm A */ __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ + /* Enable Alarm A interrupt */ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); } else { - /* Disable the Alarm B */ + /* Disable Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* Clear the Alarm flag */ + /* Clear Alarm B flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* Reload the counter */ @@ -1379,16 +1386,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U); + /* Configure Alarm B register */ hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Subseconds register */ + /* Configure Alarm B Subseconds register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ + /* Enable Alarm B */ __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ + /* Enable Alarm B interrupt */ __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); } - /* RTC Alarm Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Alarm interrupt */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); @@ -1440,7 +1448,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) @@ -1468,7 +1476,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) @@ -1565,7 +1573,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Clear the EXTI's line Flag for RTC Alarm */ + /* Clear the EXTI flag associated to the RTC Alarm interrupt */ __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); /* Get the Alarm A interrupt source enable status */ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c index 49f1f68e71..df2bf370bd 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rtc_ex.c @@ -54,7 +54,7 @@ *** Tamper configuration *** ============================ [..] - (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger + (+) To enable the RTC Tamper and configure the Tamper filter count, trigger Edge or Level according to the Tamper filter value (if equal to 0 Edge else Level), sampling frequency, NoErase, MaskFlag, precharge or discharge and Pull-UP use the HAL_RTCEx_SetTamper() function. @@ -86,14 +86,14 @@ This cycle is maintained by a 20-bit counter clocked by RTCCLK. (+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles to be masked during the 32-second cycle. - (+) The RTC Smooth Digital Calibration value and the corresponding calibration - cycle period (32s, 16s, or 8s) can be calibrated using the - HAL_RTCEx_SetSmoothCalib() function. + (+) To configure the RTC Smooth Digital Calibration value and the corresponding + calibration cycle period (32s,16s and 8s) use the HAL_RTCEx_SetSmoothCalib() + function. *** Outputs configuration *** ============================= [..] The RTC has 2 different outputs: - (+) RTC_ALARM: this output is used to manage the RTC Alarm A, Alarm B + (+) RTC_ALARM: this output is used to manage the RTC alarms (Alarm A and Alarm B) and WaKeUp signals. To output the selected RTC signal, use the HAL_RTC_Init() function. (+) RTC_CALIB: this output is 512Hz signal or 1Hz. @@ -288,7 +288,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RT /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* RTC Timestamp Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); @@ -319,7 +319,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); /* Get the RTC_CR register and clear the bits to be configured */ @@ -721,7 +721,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /* Copy desired configuration into configuration register */ hrtc->Instance->TAMPCR = tmpreg; - /* RTC Tamper Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Timestamp and Tamper interrupts */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); @@ -740,11 +740,11 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType * the configuration information for RTC. * @param Tamper Selected tamper pin. * This parameter can be any combination of the following values: - * @arg RTC_TAMPER_1: Tamper 1 + * @arg RTC_TAMPER_1: Tamper 1 (*) * @arg RTC_TAMPER_2: Tamper 2 - * @arg RTC_TAMPER_3: Tamper 3 - * @note RTC_TAMPER_1 is not applicable to all devices. - * @note RTC_TAMPER_3 is not applicable to all devices. + * @arg RTC_TAMPER_3: Tamper 3 (*) + * + * (*) value not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) @@ -795,7 +795,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ + /* Clear the EXTI flag associated to the RTC Timestamp and Tamper interrupts */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); /* Get the Timestamp interrupt source enable status */ @@ -1295,7 +1295,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* RTC wakeup timer Interrupt Configuration: EXTI configuration */ + /* Enable and configure the EXTI line associated to the RTC Wakeup Timer interrupt */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); @@ -1337,7 +1337,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Disable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must disabled */ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); /* Get tick */ @@ -1391,7 +1391,7 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + /* Clear the EXTI flag associated to the RTC Wakeup Timer interrupt */ __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); /* Get the Wakeup timer interrupt source enable status */ @@ -1512,7 +1512,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Write the specified register */ @@ -1535,7 +1535,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t) & (hrtc->Instance->BKP0R); + tmp = (uint32_t) &(hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Read the specified register */ @@ -1899,7 +1899,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + hrtc->Instance->CR |= (uint32_t)RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1932,7 +1932,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BYPSHAD; /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c index b59dce8efb..2592c42b7e 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smartcard.c @@ -134,7 +134,7 @@ [..] Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -149,10 +149,10 @@ [..] By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + reset to the legacy weak functions in the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -169,7 +169,7 @@ [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -461,7 +461,7 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /** * @brief Register a User SMARTCARD Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID * and HAL_SMARTCARD_MSPDEINIT_CB_ID @@ -2283,7 +2283,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c index ad040c5364..5f8557e0c1 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus.c @@ -926,6 +926,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer; /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -958,11 +959,35 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint hsmbus->XferSize = Size; } + sizetoxfer = hsmbus->XferSize; + if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + if (hsmbus->pBuffPtr != NULL) + { + /* Preload TX register */ + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferCount--; + hsmbus->XferSize--; + } + else + { + return HAL_ERROR; + } + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } @@ -977,7 +1002,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ @@ -987,7 +1012,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint SMBUS_ConvertOtherXferOptions(hsmbus); /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE); } @@ -996,8 +1021,15 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) { - hsmbus->XferSize--; - hsmbus->XferCount--; + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } } } @@ -2587,8 +2619,11 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); } - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); + if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) + { + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + } /* Store current volatile hsmbus->ErrorCode, misra rule */ tmperror = hsmbus->ErrorCode; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c index 48c2151650..978257867f 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_smbus_ex.c @@ -6,6 +6,8 @@ * This file provides firmware functions to manage the following * functionalities of SMBUS Extended peripheral: * + Extended features functions + * + WakeUp Mode Functions + * + FastModePlus Functions * ****************************************************************************** * @attention diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c index a7f489f02a..369023e9c1 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -198,7 +199,8 @@ @note The max SPI frequency depend on SPI data size (8bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -223,7 +225,7 @@ * @{ */ #define SPI_DEFAULT_TIMEOUT 100U -#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */ +#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 us */ /** * @} */ @@ -769,15 +771,14 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) @@ -790,29 +791,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -851,7 +850,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -861,7 +860,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -870,9 +869,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -882,7 +881,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -891,7 +890,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -900,9 +899,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -927,29 +926,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -957,7 +958,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint32_t tmpreg = 0U; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -968,8 +968,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -979,17 +983,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1049,9 +1047,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1073,9 +1071,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1092,8 +1090,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1111,8 +1109,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1137,32 +1136,31 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint32_t tmp_mode; @@ -1174,7 +1172,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -1187,9 +1184,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1199,18 +1193,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD initial_TxXferCount = Size; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1222,7 +1218,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1250,16 +1246,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1285,9 +1290,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1296,16 +1301,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ } while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1331,9 +1344,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1347,8 +1360,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ tmpreg = READ_REG(hspi->Instance->DR); @@ -1362,17 +1376,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - goto error; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Clear overrun flag in 2 Lines communication mode because received is not read */ @@ -1381,31 +1395,31 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD __HAL_SPI_CLEAR_OVRFLAG(hspi); } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -1417,25 +1431,24 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1471,10 +1484,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1482,23 +1491,24 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); - return errorcode; + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + return HAL_OK; } /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* in this case, 16-bit access is performed on Data @@ -1509,8 +1519,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1520,15 +1534,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } + /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1568,9 +1577,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1582,26 +1588,28 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); - return errorcode; + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { @@ -1614,26 +1622,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1642,7 +1649,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1669,8 +1676,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } #endif /* USE_SPI_CRC */ - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1679,23 +1684,24 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); - return errorcode; + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1703,25 +1709,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1766,9 +1770,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -1778,16 +1782,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -1795,22 +1799,24 @@ error : * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1827,12 +1833,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1880,9 +1880,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -1892,34 +1892,33 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -1928,26 +1927,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1956,7 +1954,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2001,9 +1999,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2022,9 +2020,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2033,16 +2031,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2408,9 +2407,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -2700,7 +2701,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -2712,7 +2713,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -2739,7 +2740,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -2796,7 +2797,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -2885,7 +2886,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -2965,7 +2966,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -2983,7 +2984,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3001,7 +3002,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3019,7 +3020,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3042,7 +3043,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3064,7 +3065,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); __IO uint32_t count; hspi->hdmatx->XferAbortCallback = NULL; @@ -3129,7 +3130,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3251,7 +3252,7 @@ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3344,7 +3345,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3492,7 +3493,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3518,7 +3519,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3597,7 +3598,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -3664,8 +3668,17 @@ static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t */ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { - /* Timeout in µs */ - __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + __IO uint32_t count; + + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Timeout in us */ + count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ if (hspi->Init.Mode == SPI_MODE_MASTER) { diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c index 306ceb1f70..55de011fbd 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c @@ -3647,13 +3647,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) { { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ @@ -3681,11 +3684,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) @@ -3711,11 +3714,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) @@ -3741,11 +3744,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) @@ -3771,11 +3774,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else @@ -3784,11 +3787,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) } } /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else @@ -4269,7 +4272,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -6452,17 +6456,21 @@ static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *St /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; + + TIMx->CR1 = tmpcr1; } /** @@ -6477,11 +6485,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6524,11 +6533,12 @@ static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6572,11 +6582,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6619,11 +6630,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co uint32_t tmpccer; uint32_t tmpcr2; + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; @@ -6802,9 +6814,9 @@ static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) @@ -6892,9 +6904,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; @@ -6931,9 +6943,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; @@ -6975,9 +6987,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC3S; @@ -7023,9 +7035,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccer; /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; TIMx->CCER &= ~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c index 974db59017..93bd715ff0 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c @@ -105,7 +105,7 @@ [..] Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -127,10 +127,10 @@ [..] By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + reset to the legacy weak functions in the HAL_UART_Init() and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -147,7 +147,7 @@ [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -193,8 +193,8 @@ /** @addtogroup UART_Private_Functions * @{ */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); @@ -332,15 +332,17 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In asynchronous mode, the following bits must be kept cleared: @@ -397,15 +399,17 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In half-duplex mode, the following bits must be kept cleared: @@ -483,15 +487,17 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In LIN mode, the following bits must be kept cleared: @@ -567,15 +573,17 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* In multiprocessor mode, the following bits must be kept cleared: @@ -680,7 +688,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /** * @brief Register a User UART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID @@ -928,10 +936,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = pCallback; } @@ -942,9 +947,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; } @@ -958,10 +960,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) + if (huart->RxState == HAL_UART_STATE_READY) { huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ } @@ -972,8 +971,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(huart); return status; } @@ -990,75 +987,79 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -2436,6 +2437,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3213,6 +3236,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) { @@ -3234,13 +3264,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); } - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) { @@ -3366,24 +3389,24 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_TIMEOUT; } - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) { - /* Clear Overrun Error flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts if ongoing */ - UART_EndRxTransfer(huart); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->ErrorCode = HAL_UART_ERROR_ORE; + huart->ErrorCode = HAL_UART_ERROR_ORE; - /* Process Unlocked */ - __HAL_UNLOCK(huart); + /* Process Unlocked */ + __HAL_UNLOCK(huart); - return HAL_ERROR; + return HAL_ERROR; } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { @@ -3653,12 +3676,24 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3691,12 +3726,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3761,7 +3806,6 @@ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c index ea4595369a..2727c83151 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -193,15 +193,17 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) { - return HAL_ERROR; + UART_AdvFeatureConfig(huart); } - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) { - UART_AdvFeatureConfig(huart); + return HAL_ERROR; } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ @@ -233,11 +235,10 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() @endverbatim * @{ */ @@ -286,19 +287,19 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -306,13 +307,13 @@ __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -662,7 +663,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_OK; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) @@ -687,24 +688,20 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; huart->RxEventType = HAL_UART_RXEVENT_TC; - status = UART_Start_Receive_IT(huart, pData, Size); + (void)UART_Start_Receive_IT(huart, pData, Size); - /* Check Rx process has been successfully started */ - if (status == HAL_OK) + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; } return status; @@ -800,23 +797,21 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) */ -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) { /* Return Rx Event type value, as stored in UART handle */ return (huart->RxEventType); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c index 29c79722dd..00a76438b8 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_usart.c @@ -89,7 +89,7 @@ [..] Use function HAL_USART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. + weak function. HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: @@ -105,10 +105,10 @@ [..] By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: + all callbacks are set to the corresponding weak functions: examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the HAL_USART_Init() + reset to the legacy weak functions in the HAL_USART_Init() and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). @@ -125,7 +125,7 @@ [..] When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. + and weak callbacks are used. @endverbatim @@ -140,7 +140,7 @@ */ /** @defgroup USART USART - * @brief HAL USART Synchronous module driver + * @brief HAL USART Synchronous SPI module driver * @{ */ @@ -212,8 +212,8 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + in synchronous SPI master mode. + (+) For the synchronous SPI mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit @@ -225,7 +225,7 @@ static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous SPI configuration procedure (details for the procedure are available in reference manual). @endverbatim @@ -303,7 +303,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) return HAL_ERROR; } - /* In Synchronous mode, the following bits must be kept cleared: + /* In Synchronous SPI mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register. */ @@ -393,7 +393,7 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) /** * @brief Register a User USART Callback - * To be used instead of the weak predefined callback + * To be used to override the weak predefined callback * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle @@ -626,10 +626,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ =============================================================================== ##### IO operation functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI data transfers. - [..] The USART supports master mode only: it cannot receive or send data related to an input + [..] The USART Synchronous SPI supports master mode only: it cannot receive or send data related to an input clock (SCLK is always an output). [..] @@ -2863,7 +2863,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: * set CPOL bit according to husart->Init.CLKPolarity value * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) * set STOP[13:12] bits according to husart->Init.StopBits value */ tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)husart->Init.CLKLastBit; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c index cb76ed4c0a..8a97989e76 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_crc.c @@ -59,7 +59,7 @@ * - SUCCESS: CRC registers are de-initialized * - ERROR: CRC registers are not de-initialized */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c index e6189614ee..76deab9faa 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rng.c @@ -59,7 +59,7 @@ * - SUCCESS: RNG registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c index 3058c0eddb..a8e01ed10a 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_spi.c @@ -119,7 +119,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -156,8 +156,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) @@ -336,7 +337,7 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx) { return LL_SPI_DeInit(SPIx); } diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c index 68a8095815..8dcb436291 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c @@ -700,7 +700,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM return SUCCESS; } - /** * @brief Configure the TIMx input channel 1. * @param TIMx Timer Instance @@ -825,7 +824,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - /* Select the Polarity and set the CC2E Bit */ + /* Select the Polarity and set the CC4E Bit */ MODIFY_REG(TIMx->CCER, (TIM_CCER_CC4P | TIM_CCER_CC4NP), ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); diff --git a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c index 7c715f9fd2..4e1c863f36 100644 --- a/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c +++ b/system/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usb.c @@ -172,6 +172,47 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) return HAL_OK; } +/** + * @brief USB_FlushTxFifo : Flush a Tx FIFO + * @param USBx : Selected device + * @param num : FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo : Flush Rx FIFO + * @param USBx : Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + + /* NOTE : - This function is not required by USB Device FS peripheral, it is used + only by USB OTG FS peripheral. + - This function is added to ensure compatibility across platforms. + */ + + return HAL_OK; +} + + #if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint @@ -278,6 +319,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -382,7 +427,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -484,9 +529,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -518,19 +563,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -539,15 +590,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -558,18 +607,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -613,26 +652,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } @@ -751,7 +787,7 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) * @param USBx Selected device * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_TypeDef const *USBx) { uint32_t tmpreg; @@ -791,7 +827,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_WritePMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; uint32_t BaseAddr = (uint32_t)USBx; @@ -826,7 +862,7 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui * @param wNBytes no. of bytes to be copied. * @retval None */ -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) { uint32_t n = (uint32_t)wNBytes >> 1; uint32_t BaseAddr = (uint32_t)USBx; diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 385bc6504c..1159a67d87 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -11,7 +11,7 @@ * STM32G4: 1.2.5 * STM32H5: 1.5.0 * STM32H7: 1.11.5 - * STM32L0: 1.10.6 + * STM32L0: 1.10.7 * STM32L1: 1.4.6 * STM32L4: 1.13.5 * STM32L5: 1.0.6 From e8424943d1479e1b5e2921530e590f84e704fbfc Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 25 Mar 2025 10:33:40 +0100 Subject: [PATCH 06/22] system(l0): update STM32L0xx CMSIS Drivers to v1.9.4 Included in STM32CubeL0 FW v1.12.3 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32L0xx/Include/stm32l010x4.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l010x6.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l010x8.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l010xb.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l011xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l021xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l031xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l041xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l051xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l052xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l053xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l062xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l063xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l071xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l072xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l073xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l081xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l082xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l083xx.h | 242 ++++++++++++------ .../Device/ST/STM32L0xx/Include/stm32l0xx.h | 2 +- .../ST/STM32L0xx/{License.md => LICENSE.md} | 0 .../CMSIS/Device/ST/STM32L0xx/README.md | 25 +- .../Device/ST/STM32L0xx/Release_Notes.html | 93 ++++--- .../Source/Templates/system_stm32l0xx.c | 8 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 25 files changed, 3149 insertions(+), 1579 deletions(-) rename system/Drivers/CMSIS/Device/ST/STM32L0xx/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h index 6349b7fd20..6d12941c0d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h @@ -2010,86 +2010,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h index a538cbe81f..987ec29039 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h @@ -2016,86 +2016,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h index 100a071095..5d517cc61e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h @@ -2018,86 +2018,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h index 0c4d289c3b..9bde1b9ae0 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h @@ -2026,86 +2026,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h index e9360b4160..1dfee91597 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h @@ -2091,86 +2091,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h index a056668d39..fd2715d5d7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h @@ -2219,86 +2219,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h index dc83514cef..379556f619 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h @@ -2157,86 +2157,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h index 9890981d4c..f723aeea31 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h @@ -2285,86 +2285,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h index df8cf52d46..8a8a4cb880 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h @@ -2198,86 +2198,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h index 941c8f125e..b6b281a81e 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h @@ -2487,86 +2487,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h index 155bd6a953..8e74bf7a32 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h @@ -2509,86 +2509,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h index 23ac2024e7..b57d9e0e04 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h @@ -2615,86 +2615,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h index da17873f12..a7cf903a24 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h @@ -2637,86 +2637,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h index d0df9aea06..13bf84ae45 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h @@ -2244,86 +2244,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h index 18a980888e..750d946722 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h @@ -2632,86 +2632,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h index af87c0ce07..6aa4fb2d7c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h @@ -2654,86 +2654,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h index 3449d29a4f..4e58712c22 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h @@ -2372,86 +2372,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h index 5a1b61eaf8..d2b70e8652 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h @@ -2760,86 +2760,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h index 1bbc635359..cdb103ad74 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h @@ -2782,86 +2782,168 @@ typedef struct #define GPIO_OTYPER_OT_15 (0x00008000U) /**************** Bit definition for GPIO_OSPEEDR register ******************/ -#define GPIO_OSPEEDER_OSPEED0_Pos (0U) -#define GPIO_OSPEEDER_OSPEED0_Msk (0x3UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ -#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk -#define GPIO_OSPEEDER_OSPEED0_0 (0x1UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ -#define GPIO_OSPEEDER_OSPEED0_1 (0x2UL << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ -#define GPIO_OSPEEDER_OSPEED1_Pos (2U) -#define GPIO_OSPEEDER_OSPEED1_Msk (0x3UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ -#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk -#define GPIO_OSPEEDER_OSPEED1_0 (0x1UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ -#define GPIO_OSPEEDER_OSPEED1_1 (0x2UL << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ -#define GPIO_OSPEEDER_OSPEED2_Pos (4U) -#define GPIO_OSPEEDER_OSPEED2_Msk (0x3UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ -#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk -#define GPIO_OSPEEDER_OSPEED2_0 (0x1UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ -#define GPIO_OSPEEDER_OSPEED2_1 (0x2UL << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ -#define GPIO_OSPEEDER_OSPEED3_Pos (6U) -#define GPIO_OSPEEDER_OSPEED3_Msk (0x3UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ -#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk -#define GPIO_OSPEEDER_OSPEED3_0 (0x1UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ -#define GPIO_OSPEEDER_OSPEED3_1 (0x2UL << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ -#define GPIO_OSPEEDER_OSPEED4_Pos (8U) -#define GPIO_OSPEEDER_OSPEED4_Msk (0x3UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ -#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk -#define GPIO_OSPEEDER_OSPEED4_0 (0x1UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ -#define GPIO_OSPEEDER_OSPEED4_1 (0x2UL << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ -#define GPIO_OSPEEDER_OSPEED5_Pos (10U) -#define GPIO_OSPEEDER_OSPEED5_Msk (0x3UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ -#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk -#define GPIO_OSPEEDER_OSPEED5_0 (0x1UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ -#define GPIO_OSPEEDER_OSPEED5_1 (0x2UL << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ -#define GPIO_OSPEEDER_OSPEED6_Pos (12U) -#define GPIO_OSPEEDER_OSPEED6_Msk (0x3UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ -#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk -#define GPIO_OSPEEDER_OSPEED6_0 (0x1UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ -#define GPIO_OSPEEDER_OSPEED6_1 (0x2UL << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ -#define GPIO_OSPEEDER_OSPEED7_Pos (14U) -#define GPIO_OSPEEDER_OSPEED7_Msk (0x3UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ -#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk -#define GPIO_OSPEEDER_OSPEED7_0 (0x1UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ -#define GPIO_OSPEEDER_OSPEED7_1 (0x2UL << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ -#define GPIO_OSPEEDER_OSPEED8_Pos (16U) -#define GPIO_OSPEEDER_OSPEED8_Msk (0x3UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ -#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk -#define GPIO_OSPEEDER_OSPEED8_0 (0x1UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ -#define GPIO_OSPEEDER_OSPEED8_1 (0x2UL << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ -#define GPIO_OSPEEDER_OSPEED9_Pos (18U) -#define GPIO_OSPEEDER_OSPEED9_Msk (0x3UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ -#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk -#define GPIO_OSPEEDER_OSPEED9_0 (0x1UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ -#define GPIO_OSPEEDER_OSPEED9_1 (0x2UL << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ -#define GPIO_OSPEEDER_OSPEED10_Pos (20U) -#define GPIO_OSPEEDER_OSPEED10_Msk (0x3UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ -#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk -#define GPIO_OSPEEDER_OSPEED10_0 (0x1UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ -#define GPIO_OSPEEDER_OSPEED10_1 (0x2UL << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ -#define GPIO_OSPEEDER_OSPEED11_Pos (22U) -#define GPIO_OSPEEDER_OSPEED11_Msk (0x3UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ -#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk -#define GPIO_OSPEEDER_OSPEED11_0 (0x1UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ -#define GPIO_OSPEEDER_OSPEED11_1 (0x2UL << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ -#define GPIO_OSPEEDER_OSPEED12_Pos (24U) -#define GPIO_OSPEEDER_OSPEED12_Msk (0x3UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ -#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk -#define GPIO_OSPEEDER_OSPEED12_0 (0x1UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ -#define GPIO_OSPEEDER_OSPEED12_1 (0x2UL << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ -#define GPIO_OSPEEDER_OSPEED13_Pos (26U) -#define GPIO_OSPEEDER_OSPEED13_Msk (0x3UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ -#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk -#define GPIO_OSPEEDER_OSPEED13_0 (0x1UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ -#define GPIO_OSPEEDER_OSPEED13_1 (0x2UL << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ -#define GPIO_OSPEEDER_OSPEED14_Pos (28U) -#define GPIO_OSPEEDER_OSPEED14_Msk (0x3UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ -#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk -#define GPIO_OSPEEDER_OSPEED14_0 (0x1UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ -#define GPIO_OSPEEDER_OSPEED14_1 (0x2UL << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ -#define GPIO_OSPEEDER_OSPEED15_Pos (30U) -#define GPIO_OSPEEDER_OSPEED15_Msk (0x3UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ -#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk -#define GPIO_OSPEEDER_OSPEED15_0 (0x1UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ -#define GPIO_OSPEEDER_OSPEED15_1 (0x2UL << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/* Legacy defines */ +#define GPIO_OSPEEDER_OSPEED0_Pos GPIO_OSPEEDR_OSPEED0_Pos +#define GPIO_OSPEEDER_OSPEED0_Msk GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDR_OSPEED0 +#define GPIO_OSPEEDER_OSPEED0_0 GPIO_OSPEEDR_OSPEED0_0 +#define GPIO_OSPEEDER_OSPEED0_1 GPIO_OSPEEDR_OSPEED0_1 +#define GPIO_OSPEEDER_OSPEED1_Pos GPIO_OSPEEDR_OSPEED1_Pos +#define GPIO_OSPEEDER_OSPEED1_Msk GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDR_OSPEED1 +#define GPIO_OSPEEDER_OSPEED1_0 GPIO_OSPEEDR_OSPEED1_0 +#define GPIO_OSPEEDER_OSPEED1_1 GPIO_OSPEEDR_OSPEED1_1 +#define GPIO_OSPEEDER_OSPEED2_Pos GPIO_OSPEEDR_OSPEED2_Pos +#define GPIO_OSPEEDER_OSPEED2_Msk GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDR_OSPEED2 +#define GPIO_OSPEEDER_OSPEED2_0 GPIO_OSPEEDR_OSPEED2_0 +#define GPIO_OSPEEDER_OSPEED2_1 GPIO_OSPEEDR_OSPEED2_1 +#define GPIO_OSPEEDER_OSPEED3_Pos GPIO_OSPEEDR_OSPEED3_Pos +#define GPIO_OSPEEDER_OSPEED3_Msk GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDR_OSPEED3 +#define GPIO_OSPEEDER_OSPEED3_0 GPIO_OSPEEDR_OSPEED3_0 +#define GPIO_OSPEEDER_OSPEED3_1 GPIO_OSPEEDR_OSPEED3_1 +#define GPIO_OSPEEDER_OSPEED4_Pos GPIO_OSPEEDR_OSPEED4_Pos +#define GPIO_OSPEEDER_OSPEED4_Msk GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDR_OSPEED4 +#define GPIO_OSPEEDER_OSPEED4_0 GPIO_OSPEEDR_OSPEED4_0 +#define GPIO_OSPEEDER_OSPEED4_1 GPIO_OSPEEDR_OSPEED4_1 +#define GPIO_OSPEEDER_OSPEED5_Pos GPIO_OSPEEDR_OSPEED5_Pos +#define GPIO_OSPEEDER_OSPEED5_Msk GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDR_OSPEED5 +#define GPIO_OSPEEDER_OSPEED5_0 GPIO_OSPEEDR_OSPEED5_0 +#define GPIO_OSPEEDER_OSPEED5_1 GPIO_OSPEEDR_OSPEED5_1 +#define GPIO_OSPEEDER_OSPEED6_Pos GPIO_OSPEEDR_OSPEED6_Pos +#define GPIO_OSPEEDER_OSPEED6_Msk GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDR_OSPEED6 +#define GPIO_OSPEEDER_OSPEED6_0 GPIO_OSPEEDR_OSPEED6_0 +#define GPIO_OSPEEDER_OSPEED6_1 GPIO_OSPEEDR_OSPEED6_1 +#define GPIO_OSPEEDER_OSPEED7_Pos GPIO_OSPEEDR_OSPEED7_Pos +#define GPIO_OSPEEDER_OSPEED7_Msk GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDR_OSPEED7 +#define GPIO_OSPEEDER_OSPEED7_0 GPIO_OSPEEDR_OSPEED7_0 +#define GPIO_OSPEEDER_OSPEED7_1 GPIO_OSPEEDR_OSPEED7_1 +#define GPIO_OSPEEDER_OSPEED8_Pos GPIO_OSPEEDR_OSPEED8_Pos +#define GPIO_OSPEEDER_OSPEED8_Msk GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDR_OSPEED8 +#define GPIO_OSPEEDER_OSPEED8_0 GPIO_OSPEEDR_OSPEED8_0 +#define GPIO_OSPEEDER_OSPEED8_1 GPIO_OSPEEDR_OSPEED8_1 +#define GPIO_OSPEEDER_OSPEED9_Pos GPIO_OSPEEDR_OSPEED9_Pos +#define GPIO_OSPEEDER_OSPEED9_Msk GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDR_OSPEED9 +#define GPIO_OSPEEDER_OSPEED9_0 GPIO_OSPEEDR_OSPEED9_0 +#define GPIO_OSPEEDER_OSPEED9_1 GPIO_OSPEEDR_OSPEED9_1 +#define GPIO_OSPEEDER_OSPEED10_Pos GPIO_OSPEEDR_OSPEED10_Pos +#define GPIO_OSPEEDER_OSPEED10_Msk GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDR_OSPEED10 +#define GPIO_OSPEEDER_OSPEED10_0 GPIO_OSPEEDR_OSPEED10_0 +#define GPIO_OSPEEDER_OSPEED10_1 GPIO_OSPEEDR_OSPEED10_1 +#define GPIO_OSPEEDER_OSPEED11_Pos GPIO_OSPEEDR_OSPEED11_Pos +#define GPIO_OSPEEDER_OSPEED11_Msk GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDR_OSPEED11 +#define GPIO_OSPEEDER_OSPEED11_0 GPIO_OSPEEDR_OSPEED11_0 +#define GPIO_OSPEEDER_OSPEED11_1 GPIO_OSPEEDR_OSPEED11_1 +#define GPIO_OSPEEDER_OSPEED12_Pos GPIO_OSPEEDR_OSPEED12_Pos +#define GPIO_OSPEEDER_OSPEED12_Msk GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDR_OSPEED12 +#define GPIO_OSPEEDER_OSPEED12_0 GPIO_OSPEEDR_OSPEED12_0 +#define GPIO_OSPEEDER_OSPEED12_1 GPIO_OSPEEDR_OSPEED12_1 +#define GPIO_OSPEEDER_OSPEED13_Pos GPIO_OSPEEDR_OSPEED13_Pos +#define GPIO_OSPEEDER_OSPEED13_Msk GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDR_OSPEED13 +#define GPIO_OSPEEDER_OSPEED13_0 GPIO_OSPEEDR_OSPEED13_0 +#define GPIO_OSPEEDER_OSPEED13_1 GPIO_OSPEEDR_OSPEED13_1 +#define GPIO_OSPEEDER_OSPEED14_Pos GPIO_OSPEEDR_OSPEED14_Pos +#define GPIO_OSPEEDER_OSPEED14_Msk GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDR_OSPEED14 +#define GPIO_OSPEEDER_OSPEED14_0 GPIO_OSPEEDR_OSPEED14_0 +#define GPIO_OSPEEDER_OSPEED14_1 GPIO_OSPEEDR_OSPEED14_1 +#define GPIO_OSPEEDER_OSPEED15_Pos GPIO_OSPEEDR_OSPEED15_Pos +#define GPIO_OSPEEDER_OSPEED15_Msk GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDR_OSPEED15 +#define GPIO_OSPEEDER_OSPEED15_0 GPIO_OSPEEDR_OSPEED15_0 +#define GPIO_OSPEEDER_OSPEED15_1 GPIO_OSPEEDR_OSPEED15_1 /******************* Bit definition for GPIO_PUPDR register ******************/ #define GPIO_PUPDR_PUPD0_Pos (0U) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h index 4a550efa6f..1416377d81 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h @@ -103,7 +103,7 @@ */ #define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32L0xx_CMSIS_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */ -#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ #define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/License.md b/system/Drivers/CMSIS/Device/ST/STM32L0xx/LICENSE.md similarity index 100% rename from system/Drivers/CMSIS/Device/ST/STM32L0xx/License.md rename to system/Drivers/CMSIS/Device/ST/STM32L0xx/LICENSE.md diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md b/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md index e022d05950..05d7cd7245 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/README.md @@ -1,19 +1,21 @@ -# STM32CubeG4 CMSIS Device MCU Component +# STM32CubeL0 CMSIS Device MCU Component + +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_l0.svg?color=brightgreen) ## Overview **STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as RTOS, USB, FatFS, Graphics, STM32_TouchSensing_Library ... - * A full set of software projects (basic examples, applications or demonstrations) for each board provided by this STM32 series +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, discovery, or nucleo board provided for this STM32 series. -Two models of publication are proposed for the STM32Cube embedded software : - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from November 2019, each STM32Cube software module being part of the STM32Cube MCU Package, will be delivered as an individual repo, allowing the user to select and get only the required software functions. + * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... + * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +Two models of publication are proposed for the STM32Cube embedded software: + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -30,6 +32,5 @@ It is **crucial** that you use a consistent set of versions for the CMSIS Core - The full **STM32CubeL0** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL0). ## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/cmsis_device_l0/issues/new). -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html index ecfd8d86a5..74ff71c8f6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Release_Notes.html @@ -46,12 +46,23 @@

                                                                Purpose

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                                                                • Align GPIO_OSPEEDR Register Bits Naming with Reference Manual.
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                                                                • All source files: update disclaimer to add reference to the new license agreement.
                                                                • Fix inconsistent IRQn_Type enumeration for supervisor call exception with alias for compatibility.
                                                                • Update the GCC startup file to be aligned to IAR/Keil IDE.
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                                                                  • Add new atomic register access macros in stm32l0xx.h file.
                                                                  • Add LSI maximum startup time datasheet value: LSI_STARTUP_TIME.
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                                                                            • Updated IS_COMP_COMMON_INSTANCE() macro.
                                                                            • Corrected ADC_CFGR2_TOVS bit and mask definitions.
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                                                                              • Added Pos and Msk macros missing within the CMSIS stm32l083xx.h file.
                                                                              • Added LCD_CR_BUFEN bit definition in LCD CR register for stm32l053xx, stm32l063xx, stm32l073xx, stm32l083xx devices.
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                                                                                    • MISRA C 2004 rule 5.1 and rule 10.6 compliance.
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                                                                                      • Remove the Debug Monitor handler from the startup files (not supported on L0).
                                                                                      • Renamings and usage of some aliases in order to be compliant with the RefManuals.
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                                                                                        • Several renamings in order to be compliant with the specifications.
                                                                                        • Adding of new bit definitions (COMP_CSR_COMP2LPTIM1IN1, SYSCFG_CFGR1_UFB, I2C_OAR2_x, LCD_CR_MUX_SEG, RTC_BKP_NUMBER)
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                                                                                          • Add IAR set of files STM32L073xx - STM32L072xx - STM32L071xx - STM32L083xx - STM32L082xx - STM32L081xx
                                                                                          • Added MDK-ARM startup files for L071xx, L072xx, L073xx, L081xx, L082xx, L083xx
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                                                                                            • Header files
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                                                                                                diff --git a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c index d50e65c844..d87a7480e7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c @@ -90,14 +90,14 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 9c4aa19e70..f2e4cc5252 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -11,7 +11,7 @@ * STM32G4: 1.2.5 * STM32H5: 1.4.0 * STM32H7: 1.10.6 - * STM32L0: 1.9.3 + * STM32L0: 1.9.4 * STM32L1: 2.3.4 * STM32L4: 1.7.4 * STM32L5: 1.0.6 From 782fbafea706eb5275740152541fcec93a6b9c7e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 25 Mar 2025 14:45:58 +0100 Subject: [PATCH 07/22] ci(stm32variant): improve skip feature avoid to parse the xml file if family have to be skipped Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 35af1c64e6..bfc9facc62 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -178,6 +178,19 @@ def parse_mcu_file(): if mcu_family.endswith("+"): mcu_family = mcu_family[:-1] + + # Generate only for specified pattern series or supported one + # Check if mcu_family is supported by the core + if ( + mcu_family not in stm32_list + or args.serie + and serie_pattern.search(mcu_family) is None + ): + if mcu_family not in ignored_stm32_list and mcu_family not in stm32_list: + ignored_stm32_list.append(mcu_family) + xml_mcu.unlink() + return False + mcu_refname = mcu_node.attributes["RefName"].value core_node = mcu_node.getElementsByTagName("Core") for f in core_node: @@ -213,6 +226,7 @@ def parse_mcu_file(): else: if gpiofile == "" and s.attributes["Name"].value == "GPIO": gpiofile = s.attributes["Version"].value + return True def get_gpio_af_num(pintofind, iptofind): @@ -2742,18 +2756,7 @@ def manage_repo(): for mcu_file in mcu_list: # Open input file xml_mcu = parse(str(mcu_file)) - parse_mcu_file() - - # Generate only for specified pattern series or supported one - # Check if mcu_family is supported by the core - if ( - mcu_family not in stm32_list - or args.serie - and serie_pattern.search(mcu_family) is None - ): - if mcu_family not in ignored_stm32_list and mcu_family not in stm32_list: - ignored_stm32_list.append(mcu_family) - xml_mcu.unlink() + if parse_mcu_file() is False: continue # Add mcu family to the list of directory to aggregate From df761bf36f90a3997ee171876345e8842e326e6f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 14 Mar 2025 10:37:47 +0100 Subject: [PATCH 08/22] fix(openocd): update to xpack-openocd v0.12.0-6 https://github.com/xpack-dev-tools/openocd-xpack/releases/tag/v0.12.0-6 Fixes #2683. Signed-off-by: Frederic Pillon --- platform.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.txt b/platform.txt index 651928558f..faeddf45fa 100644 --- a/platform.txt +++ b/platform.txt @@ -17,7 +17,7 @@ busybox= busybox.windows={runtime.tools.STM32Tools.path}/win/busybox.exe toolchain_dir={runtime.tools.xpack-arm-none-eabi-gcc-14.2.1-1.1.path} -openocd_dir={runtime.tools.xpack-openocd-0.12.0-5.path} +openocd_dir={runtime.tools.xpack-openocd-0.12.0-6.path} tools_bin_path.windows={runtime.tools.STM32Tools.path}/win tools_bin_path.macosx={runtime.tools.STM32Tools.path}/macosx From 2ef2edb393c7f58a7c9d04ab6a8a161e256e6fc9 Mon Sep 17 00:00:00 2001 From: Tom Hayden Date: Thu, 20 Mar 2025 15:23:28 -0500 Subject: [PATCH 09/22] variant(l5): add generic L552Q(C-E)IxQ and L562QEIxQ Signed-off-by: Tom Hayden Co-Authored-by: Frederic Pillon --- README.md | 2 + boards.txt | 27 +++ .../L552Q(C-E)IxQ_L562QEIxQ/generic_clock.c | 58 +++++- .../L552Q(C-E)IxQ_L562QEIxQ/ldscript.ld | 186 ++++++++++++++++++ 4 files changed, 272 insertions(+), 1 deletion(-) create mode 100644 variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/ldscript.ld diff --git a/README.md b/README.md index 1353cefcb6..3144385b98 100644 --- a/README.md +++ b/README.md @@ -743,7 +743,9 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32L552ZC-Q
                                                                                                STM32L552ZE-Q | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32L552QCIxQ
                                                                                                STM32L552QEIxQ | Generic Board | **2.11.0** | | | :green_heart: | STM32L562ZE-Q | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32L562QEIxQ | Generic Board | **2.11.0** | | ### Generic STM32U0 boards diff --git a/boards.txt b/boards.txt index 9d8fb3b19e..abaa3a4438 100644 --- a/boards.txt +++ b/boards.txt @@ -12226,6 +12226,24 @@ GenL5.openocd.target=stm32l5x GenL5.vid.0=0x0483 GenL5.pid.0=0x5740 +# Generic L552QCIxQ +GenL5.menu.pnum.GENERIC_L552QCIXQ=Generic L552QCIxQ +GenL5.menu.pnum.GENERIC_L552QCIXQ.upload.maximum_size=262144 +GenL5.menu.pnum.GENERIC_L552QCIXQ.upload.maximum_data_size=262144 +GenL5.menu.pnum.GENERIC_L552QCIXQ.build.board=GENERIC_L552QCIXQ +GenL5.menu.pnum.GENERIC_L552QCIXQ.build.product_line=STM32L552xx +GenL5.menu.pnum.GENERIC_L552QCIXQ.build.variant=STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ +GenL5.menu.pnum.GENERIC_L552QCIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L5xx/STM32L552.svd + +# Generic L552QEIxQ +GenL5.menu.pnum.GENERIC_L552QEIXQ=Generic L552QEIxQ +GenL5.menu.pnum.GENERIC_L552QEIXQ.upload.maximum_size=524288 +GenL5.menu.pnum.GENERIC_L552QEIXQ.upload.maximum_data_size=262144 +GenL5.menu.pnum.GENERIC_L552QEIXQ.build.board=GENERIC_L552QEIXQ +GenL5.menu.pnum.GENERIC_L552QEIXQ.build.product_line=STM32L552xx +GenL5.menu.pnum.GENERIC_L552QEIXQ.build.variant=STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ +GenL5.menu.pnum.GENERIC_L552QEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L5xx/STM32L552.svd + # Generic L552ZCTxQ GenL5.menu.pnum.GENERIC_L552ZCTXQ=Generic L552ZCTxQ GenL5.menu.pnum.GENERIC_L552ZCTXQ.upload.maximum_size=262144 @@ -12244,6 +12262,15 @@ GenL5.menu.pnum.GENERIC_L552ZETXQ.build.product_line=STM32L552xx GenL5.menu.pnum.GENERIC_L552ZETXQ.build.variant=STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ GenL5.menu.pnum.GENERIC_L552ZETXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L5xx/STM32L552.svd +# Generic L562QC-EIxQ +GenL5.menu.pnum.GENERIC_L562QEIXQ=Generic L562QC-EIxQ +GenL5.menu.pnum.GENERIC_L562QEIXQ.upload.maximum_size=524288 +GenL5.menu.pnum.GENERIC_L562QEIXQ.upload.maximum_data_size=196608 +GenL5.menu.pnum.GENERIC_L562QEIXQ.build.board=GENERIC_L562QEIXQ +GenL5.menu.pnum.GENERIC_L562QEIXQ.build.product_line=STM32L562xx +GenL5.menu.pnum.GENERIC_L562QEIXQ.build.variant=STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ +GenL5.menu.pnum.GENERIC_L562QEIXQ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L5xx/STM32L562.svd + # Generic L562ZETxQ GenL5.menu.pnum.GENERIC_L562ZETXQ=Generic L562ZETxQ GenL5.menu.pnum.GENERIC_L562ZETXQ.upload.maximum_size=524288 diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/generic_clock.c b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/generic_clock.c index ea09640eb3..fcbb9b3dff 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/generic_clock.c +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/generic_clock.c @@ -22,7 +22,63 @@ WEAK void SystemClock_Config(void) { /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI + | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 55; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + + /** Enable MSI Auto calibration + */ + HAL_RCCEx_EnableMSIPLLMode(); } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/ldscript.ld b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/ldscript.ld new file mode 100644 index 0000000000..1cc217a4cb --- /dev/null +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/ldscript.ld @@ -0,0 +1,186 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32L562xE Device from STM32L5 series +** 512Kbytes FLASH +** 256Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2025 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From 9bff2b6f57bbe10d487dd721f4e00e883482792a Mon Sep 17 00:00:00 2001 From: Tom Hayden Date: Wed, 26 Mar 2025 11:00:01 +0100 Subject: [PATCH 10/22] variant(l5): add support for STM32L562E-DK board Signed-off-by: Tom Hayden Co-Authored-by: Frederic Pillon --- README.md | 1 + boards.txt | 16 + .../PeripheralPins_STM32L562E_DK.c | 431 ++++++++++++++++++ .../variant_STM32L562E_DK.cpp | 220 +++++++++ .../variant_STM32L562E_DK.h | 281 ++++++++++++ 5 files changed, 949 insertions(+) create mode 100644 variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins_STM32L562E_DK.c create mode 100644 variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.cpp create mode 100644 variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.h diff --git a/README.md b/README.md index 3144385b98..f8b7b0bd73 100644 --- a/README.md +++ b/README.md @@ -192,6 +192,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32H573IIKxQ | [STM32H573I-DK](https://www.st.com/en/evaluation-tools/stm32h573i-dk.html) | *2.6.0* | | | :green_heart: | STM32H747XIHx | [STM32H747I-DISCO](https://www.st.com/en/evaluation-tools/stm32h747i-disco.html) | *2.7.0* | | | :green_heart: | STM32L4S5VI | [B-L4S5I-IOT01A](https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html) | *2.0.0* | | +| :yellow_heart: | STM32L562QEIxQ | [STM32L562E-DK](https://www.st.com/en/evaluation-tools/stm32l562e-dk.html) | **2.11.0** | | | :green_heart: | STM32U585AIIxQ | [B-U585I-IOT02A](https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html) | *2.1.0* | | | :green_heart: | STM32WB5MMG | [STM32WB5MM-DK](https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html) | *2.1.0* | | diff --git a/boards.txt b/boards.txt index abaa3a4438..aaebef7be9 100644 --- a/boards.txt +++ b/boards.txt @@ -1423,6 +1423,22 @@ Disco.menu.pnum.STM32H747I_DISCO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Disco.menu.pnum.STM32H747I_DISCO.openocd.target=stm32h7x Disco.menu.pnum.STM32H747I_DISCO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H747_CM7.svd +# STM32L562E-DK +Disco.menu.pnum.STM32L562E_DK=STM32L562E-DK +Disco.menu.pnum.STM32L562E_DK.node=DIS_L562QE +Disco.menu.pnum.STM32L562E_DK.upload.maximum_size=524288 +Disco.menu.pnum.STM32L562E_DK.upload.maximum_data_size=196608 +Disco.menu.pnum.STM32L562E_DK.build.mcu=cortex-m33 +Disco.menu.pnum.STM32L562E_DK.build.fpu=-mfpu=fpv4-sp-d16 +Disco.menu.pnum.STM32L562E_DK.build.float-abi=-mfloat-abi=hard +Disco.menu.pnum.STM32L562E_DK.build.board=STM32L562E_DK +Disco.menu.pnum.STM32L562E_DK.build.series=STM32L5xx +Disco.menu.pnum.STM32L562E_DK.build.product_line=STM32L562xx +Disco.menu.pnum.STM32L562E_DK.build.variant=STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ +Disco.menu.pnum.STM32L562E_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +Disco.menu.pnum.STM32L562E_DK.openocd.target=stm32l5x +Disco.menu.pnum.STM32L562E_DK.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L5xx/STM32L562.svd + # STM32WB5MM-DK board Disco.menu.pnum.STM32WB5MM_DK=STM32WB5MM-DK Disco.menu.pnum.STM32WB5MM_DK.node="DIS_WB5MMG" diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins_STM32L562E_DK.c b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins_STM32L562E_DK.c new file mode 100644 index 0000000000..e083b99c20 --- /dev/null +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/PeripheralPins_STM32L562E_DK.c @@ -0,0 +1,431 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32L552Q(C-E)IxQ.xml, STM32L562QEIxQ.xml + * CubeMX DB release 6.0.140 + */ +#if defined(ARDUINO_STM32L562E_DK) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PD_13, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT1, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1_ALT2, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_13_ALT1, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PE_0, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PG_9, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, TIM15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PG_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_2, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, + {PB_7, UART4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF_NONE)}, + {PB_13, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PB_5_ALT1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PG_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_4_ALT1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PG_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PG_2, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PG_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** FDCAN *** + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_RD[] = { + {PB_8, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_FDCAN_MODULE_ENABLED +WEAK const PinMap PinMap_CAN_TD[] = { + {PB_9, FDCAN1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** OCTOSPI *** + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA0[] = { + {PB_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA1[] = { + {PB_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA2[] = { + {PA_7, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA3[] = { + {PA_6, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA4[] = { + {PC_1, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA5[] = { + {PC_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA6[] = { + {PC_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_IO6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_DATA7[] = { + {PC_0, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPI1)}, // OCTOSPI1_IO7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SCLK[] = { + {PA_3, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_CLK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_OSPI_MODULE_ENABLED +WEAK const PinMap PinMap_OCTOSPI_SSEL[] = { + {PA_2, OCTOSPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPI1)}, // OCTOSPI1_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB[] = { + {PA_11, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DM + {PA_12, USB, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_USB)}, // USB_DP + {NC, NP, 0} +}; +#endif + +//*** SD *** + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDMMC1)}, // SDMMC1_CK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CKIN[] = { + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CDIR[] = { + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D0DIR[] = { + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_D123DIR[] = { + {NC, NP, 0} +}; +#endif + +#endif /* ARDUINO_STM32L562E_DK */ diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.cpp b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.cpp new file mode 100644 index 0000000000..806c9b190c --- /dev/null +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.cpp @@ -0,0 +1,220 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_STM32L562E_DK) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PB_10, // D0 + PB_11, + PD_11, + PD_12, + PF_4, + PD_13, + PB_8, + PC_6, + PG_0, + PB_9, + PE_0, // D10 + PB_5, + PB_4, + PG_9, + PB_7, + PB_6, + PA_0, + PA_1, + PA_4, + PA_5, + PC_4, // D20 + PC_5, + PB_14, + PB_15, + PA_2, + PA_3, + PA_6, + PA_7, + PB_0, + PB_1, + PB_2, // D30 + PC_0, + PC_1, + PC_2, + PC_3, + PF_2, + PC_8, + PC_9, + PC_10, + PC_11, + PC_12, // D40 + PD_2, + PD_7, + PD_5, + PD_4, + PF_0, + PD_14, + PD_15, + PD_0, + PD_1, + PE_7, // D50 + PE_8, + PE_9, + PE_10, + PE_11, + PE_12, + PE_13, + PE_14, + PE_15, + PD_8, + PD_9, // D60 + PD_10, + PE_1, + PF_1, + PA_8, + PF_14, + PF_15, + PH_0, + PA_11, + PA_12, + PC_13, // D70 + PD_3, + PG_12, + PG_8, + PG_6, + PG_5, + PG_4, + PG_3, + PG_2, + PG_1, + PE_2, // D80 + PE_3, + PE_4, + PE_5, + PE_6, + PG_7, + PB_12, + PC_7, + PH_1, + PF_3, + PF_11, // D90 + PF_12, + PB_13, + PF_5, + PD_6, + PG_10, + PB_3, + PA_15, + PA_9, + PA_10, + PA_13, // D100 + PA_14, + PC_14, + PC_15 +}; + + +const uint32_t analogInputPin[] = { + 16, // A0 + 17, // A1 + 18, // A2 + 19, // A3 + 20, // A4 + 21 // A5 +}; + +// ---------------------------------------------------------------------------- +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + // Configure the main internal regulator output voltage + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) { + Error_Handler(); + } + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE + | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 12; + RCC_OscInitStruct.PLL.PLLN = 55; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { + Error_Handler(); + } + + // Configure the other peripheral clocks + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SAI1 + | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; + PeriphClkInit.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1; + PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK; + PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSAI1SOURCE_HSI; + PeriphClkInit.PLLSAI1.PLLSAI1M = 4; + PeriphClkInit.PLLSAI1.PLLSAI1N = 48; + PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV17; + PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_ADC1CLK; + PeriphClkInit.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_MSI; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_MSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + + /** Enable MSI Auto calibration */ + HAL_RCCEx_EnableMSIPLLMode(); +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_STM32L562E_DK */ diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.h b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.h new file mode 100644 index 0000000000..f268407c09 --- /dev/null +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/variant_STM32L562E_DK.h @@ -0,0 +1,281 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ + +// CN12: Arduino connector +#define PB10 0 // ARD.D0_RX, T.VCP_RX +#define PB11 1 // ARD.D1_TX, T.VCP_TX +#define PD11 2 // ARD.D2_IO +#define PD12 3 // ARD.D3_TIM +#define PF4 4 // ARD.D4_INT +#define PD13 5 // ARD.D5_TIM +#define PB8 6 // ARD.D6_TIM +#define PC6 7 // ARD.D7_IO + +// CN11: Arduino connector +#define PG0 8 // ARD.D8_IO +#define PB9 9 // ARD.D9_TIM +#define PE0 10 // ARD.D10: SPI_CSn and TIM16_CH1 +#define PB5 11 // ARD.D11_TIM_SPI_MOSI, STMod+3_SPI_MOSIp +#define PB4 12 // ARD.D12_SPI_MISO, STMod+3_SPI_MISOp +#define PG9 13 // ARD.D13_SPI_SCK +#define PB7 14 // ARD.D14_I2C1_SDA +#define PB6 15 // ARD.D15_I2C1_SCL + +// CN19: Arduino connector +#define PA0 PIN_A0 // ARD.A0: ADC1_IN5, shared with STMod+ +#define PA1 PIN_A1 // ARD.A1: ADC1_IN6 +#define PA4 PIN_A2 // ARD_ADC.A2, USB_C.VBUS_VSENSE +#define PA5 PIN_A3 // ARD_ADC.A3 +#define PC4 PIN_A4 // ARD_ADC.A5 +#define PC5 PIN_A5 // ARD_ADC.A4 + +// CN17: USB Micro-B +#define PB14 22 // USB_C.FLT +#define PB15 23 // USB_C.CC2 + +// octoSPI pins (no reused pin numbers) +#define PA2 24 // OCTOSPI.NCS +#define PA3 25 // OCTOSPI.CLK +#define PA6 26 // OCTOSPI.IO3 +#define PA7 27 // OCTOSPI.IO2 +#define PB0 28 // OCTOSPI.IO1 +#define PB1 29 // OCTOSPI.IO0 +#define PB2 30 // OCTOSPI.DQS +#define PC0 31 // OCTOSPI.IO7 +#define PC1 32 // OCTOSPI.IO4 +#define PC2 33 // OCTOSPI.IO5 +#define PC3 34 // OCTOSPI.IO6 + +// microSD card pins +#define PF2 35 // SDIO.DETECT +#define PC8 36 // SDIO.D0 +#define PC9 37 // SDIO.D1 +#define PC10 38 // SDIO.D2 +#define PC11 39 // SDIO.D3 +#define PC12 40 // SDIO.CLK +#define PD2 41 // SDIO.CMD + +// LCD pins +#define PD7 42 // LCD.FMC_NE1_CS +#define PD5 43 // LCD.FMC_NWE +#define PD4 44 // LCD.FMC_NOE +#define PF0 45 // LCD.FMC_A0 +#define PD14 46 // LCD.FMC_D0 +#define PD15 47 // LCD.FMC_D1 +#define PD0 48 // LCD.FMC_D2 +#define PD1 49 // LCD.FMC_D3 +#define PE7 50 // LCD.FMC_D4 +#define PE8 51 // LCD.FMC_D5 +#define PE9 52 // LCD.FMC_D6 +#define PE10 53 // LCD.FMC_D7 +#define PE11 54 // LCD.FMC_D8 +#define PE12 55 // LCD.FMC_D9 +#define PE13 56 // LCD.FMC_D10 +#define PE14 57 // LCD.FMC_D11 +#define PE15 58 // LCD.FMC_D12 +#define PD8 59 // LCD.FMC_D13 +#define PD9 60 // LCD.FMC_D14 +#define PD10 61 // LCD.FMC_D15 +#define PE1 62 // LCD_BL_CTRL +#define PF1 63 // LCD.CTP_INT +#define PA8 64 +#define PF14 65 // LCD.RST +#define PF15 66 // LCD.CTP_RST +#define PH0 67 // LCD_PWR_ON + +// usb +#define PA11 68 // USB_C.FS_N +#define PA12 69 // USB_C.FS_P + +// User button +#define PC13 70 // USER BUTTON (WKUP2), PM_WAKE-UP + +// User LED +#define PD3 71 // LED_RED +#define PG12 72 // LED_GREEN + +// bluetooth low energy and spi +#define PG8 73 // BLE_RSTN +#define PG6 74 // BLE_INT +#define PG5 75 // SPI1.BLE_CS +#define PG4 76 // SPI1.MOSI +#define PG3 77 // SPI1.MISO +#define PG2 78 // SPI1.SCK + +// Audio codec interface +#define PG1 79 // audio RESET (active low) +#define PE2 80 // SAI.MCLK_A +#define PE3 81 // SAI.SD_B +#define PE4 82 // SAI.FS_A +#define PE5 83 // SAI.SCK_A +#define PE6 84 // SAI.SD_A + +// Digital microphone interface +#define PG7 85 // DFSDM_CKOUT +#define PB12 86 // DFSDM_DATIN1 +#define PC7 87 // DFSDM_DATIN3 +#define PH1 88 // Module LED + +// 3D ACC/GYRO +#define PF3 89 // GYRO_ACC_INT. + +// Pmod +#define PF11 90 // STMod+ SEL_12 +#define PF12 91 // STMod+ SEL_34 +#define PB13 92 +#define PF5 93 + +// STMod+ +#define PD6 94 +#define PG10 95 + +// STLINK-V3E +#define PB3 96 // T.SWO +#define PA15 97 // T.JTDI +#define PA9 98 // T.VCP_TX +#define PA10 99 // T.VCP_RX, ARD.D0_RX +#define PA13 100 // T.SWDIO +#define PA14 101 // T.SWCLK + +#define PC14 102 // OSC32_IN +#define PC15 103 // OSC32_OUT + +// PF13 NC +// PH3 Boot0 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB6_ALT1 (PB6 | ALT1) +#define PB7_ALT1 (PB7 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB10_ALT1 (PB10 | ALT1) +#define PB11_ALT1 (PB11 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 104 +#define NUM_ANALOG_INPUTS 6 + +// On-board LEDs pin number +#define LED1 PG9 +#define LED_BLUE LED1 +#define LED2 PG12 +#define LED_GREEN LED2 +#define LED3 PD3 +#define LED_RED LED3 + +#ifndef LED_BUILTIN + #define LED_BUILTIN LED_BLUE +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA10 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA9 +#endif + +// Pin UCPD to configure TCPP in default Type-C legacy state (UCPD_DBn for TCPP01) +#define PIN_UCPD_TCPP PB5 + +// SDMMC signals not available +#define SDMMC_CKIN_NA +#define SDMMC_CDIR_NA +#define SDMMC_D0DIR_NA +#define SDMMC_D123DIR_NA +// SD detect signal +#ifndef SD_DETECT_PIN + #define SD_DETECT_PIN PF2 +#endif + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_OSPI_MODULE_DISABLED) + #define HAL_OSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SD_MODULE_DISABLED) + #define HAL_SD_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 646bec61cc8afba9396714dd9d19d8a187560e34 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Sat, 29 Mar 2025 11:17:18 +0100 Subject: [PATCH 11/22] fix(uart): typo Signed-off-by: Frederic Pillon --- cores/arduino/HardwareSerial.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index 1c89de7f61..0bd61e6ddf 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -273,7 +273,7 @@ HardwareSerial::HardwareSerial(void *peripheral, HalfDuplexMode_t halfDuplex) } else #endif #if defined(PIN_SERIALLP3_TX) && defined(LPUART3_BASE) - if (peripheral == LPUART2) { + if (peripheral == LPUART3) { #if defined(PIN_SERIALLP3_RX) setRx(PIN_SERIALLP3_RX); #endif From 3a607767059e451c1093322d8d1b7e3b5dde0a8b Mon Sep 17 00:00:00 2001 From: Andrew Yong Date: Thu, 27 Mar 2025 22:48:50 +0800 Subject: [PATCH 12/22] feat(uart): support UART Tx, Rx and data invert function This enables UART Tx, Rx and data invert function on STM32 families that support it. In order to enable Tx, Rx and/or data invert, call respectively: ```c++ Serial1.setTxInvert(); Serial1.setRxInvert(); Serial1.setDataInvert(); ``` Fixes: #1160 #2669 See also: #1418 Signed-off-by: Andrew Yong --- cores/arduino/HardwareSerial.cpp | 17 ++++++++++++++- cores/arduino/HardwareSerial.h | 9 ++++++++ keywords.txt | 3 +++ libraries/SrcWrapper/inc/uart.h | 3 ++- libraries/SrcWrapper/src/stm32/uart.c | 30 ++++++++++++++++++++++----- 5 files changed, 55 insertions(+), 7 deletions(-) diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index 0bd61e6ddf..4dd8fd02a4 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -446,7 +446,7 @@ void HardwareSerial::begin(unsigned long baud, byte config) break; } - uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits); + uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert); enableHalfDuplexRx(); uart_attach_rx_callback(&_serial, _rx_complete_irq); } @@ -668,4 +668,19 @@ void HardwareSerial::enableHalfDuplexRx(void) } } +void HardwareSerial::setRxInvert(void) +{ + _rx_invert = true; +} + +void HardwareSerial::setTxInvert(void) +{ + _tx_invert = true; +} + +void HardwareSerial::setDataInvert(void) +{ + _data_invert = true; +} + #endif // HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY diff --git a/cores/arduino/HardwareSerial.h b/cores/arduino/HardwareSerial.h index f8a2884de0..3ed29a873d 100644 --- a/cores/arduino/HardwareSerial.h +++ b/cores/arduino/HardwareSerial.h @@ -95,6 +95,9 @@ class HardwareSerial : public Stream { protected: // Has any byte been written to the UART since begin() bool _written; + bool _rx_invert; + bool _tx_invert; + bool _data_invert; // Don't put any members after these buffers, since only the first // 32 bytes of this struct can be accessed quickly using the ldd @@ -165,6 +168,12 @@ class HardwareSerial : public Stream { bool isHalfDuplex(void) const; void enableHalfDuplexRx(void); + // Enable HW Rx/Tx/data inversion + // This needs to be done before the call to begin() + void setRxInvert(void); + void setTxInvert(void); + void setDataInvert(void); + friend class STM32LowPower; // Interrupt handlers diff --git a/keywords.txt b/keywords.txt index a4a284e59a..5ddcab36dd 100644 --- a/keywords.txt +++ b/keywords.txt @@ -274,6 +274,9 @@ HALF_DUPLEX_ENABLED LITERAL1 setHalfDuplex KEYWORD2 isHalfDuplex KEYWORD2 enableHalfDuplexRx KEYWORD2 +setRxInvert KEYWORD2 +setTxInvert KEYWORD2 +setDataInvert KEYWORD2 Serial4 KEYWORD1 Serial5 KEYWORD1 Serial6 KEYWORD1 diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h index a6c41390e7..7f99d498e7 100644 --- a/libraries/SrcWrapper/inc/uart.h +++ b/libraries/SrcWrapper/inc/uart.h @@ -38,6 +38,7 @@ #define __UART_H /* Includes ------------------------------------------------------------------*/ +#include #include "stm32_def.h" #include "PinNames.h" @@ -254,7 +255,7 @@ struct serial_s { /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ -void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits); +void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert); void uart_deinit(serial_t *obj); #if defined(HAL_PWR_MODULE_ENABLED) && (defined(UART_IT_WUF) || defined(LPUART1_BASE)) void uart_config_lowpower(serial_t *obj); diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 04ccb2c820..4aaa3f0e2e 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -115,7 +115,7 @@ serial_t *get_serial_obj(UART_HandleTypeDef *huart) * @param obj : pointer to serial_t structure * @retval None */ -void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits) +void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert) { if (obj == NULL) { return; @@ -407,11 +407,31 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par huart->Init.Mode = UART_MODE_TX_RX; huart->Init.HwFlowCtl = flow_control; huart->Init.OverSampling = UART_OVERSAMPLING_16; +#if defined(UART_ADVFEATURE_NO_INIT) + // Default value + huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; #if defined(UART_ADVFEATURE_SWAP_INIT) - huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_SWAP_INIT; + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_SWAP_INIT; huart->AdvancedInit.Swap = pin_swap; -#elif defined(UART_ADVFEATURE_NO_INIT) - huart->AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; +#endif +#if defined(UART_ADVFEATURE_RXINVERT_INIT) + if (rx_invert) { + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_RXINVERT_INIT; + huart->AdvancedInit.RxPinLevelInvert = UART_ADVFEATURE_RXINV_ENABLE; + } +#endif +#if defined(UART_ADVFEATURE_TXINVERT_INIT) + if (tx_invert) { + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_TXINVERT_INIT; + huart->AdvancedInit.TxPinLevelInvert = UART_ADVFEATURE_TXINV_ENABLE; + } +#endif +#if defined(UART_ADVFEATURE_DATAINVERT_INIT) + if (data_invert) { + huart->AdvancedInit.AdvFeatureInit |= UART_ADVFEATURE_DATAINVERT_INIT; + huart->AdvancedInit.DataInvert = UART_ADVFEATURE_DATAINV_ENABLE; + } +#endif #endif #ifdef UART_ONE_BIT_SAMPLE_DISABLE huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; @@ -812,7 +832,7 @@ void uart_debug_init(void) serial_debug.pin_tx = pinmap_pin(DEBUG_UART, PinMap_UART_TX); #endif /* serial_debug.pin_rx set by default to NC to configure in half duplex mode */ - uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1); + uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false); } } From 06547a23b14c8de9d2ad658977323772b0490eba Mon Sep 17 00:00:00 2001 From: dojyorin Date: Thu, 20 Mar 2025 01:28:01 +0900 Subject: [PATCH 13/22] chore: unify clock configuration of H5. Signed-off-by: dojyorin --- .../STM32H5xx/H503CB(T-U)/generic_clock.c | 30 ++++------ variants/STM32H5xx/H503KBU/generic_clock.c | 40 +++++++------ variants/STM32H5xx/H503RBT/generic_clock.c | 40 +++++++------ .../H503RBT/variant_NUCLEO_H503RB.cpp | 42 +++++++------ .../STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h | 7 ++- .../STM32H5xx/H562R(G-I)T/generic_clock.c | 53 ++++++++--------- .../H562R(G-I)T/variant_WEACT_H562RG.cpp | 49 ++++++++------- .../H562R(G-I)T/variant_WEACT_H562RG.h | 4 +- .../H563IIKxQ_H573IIKxQ/generic_clock.c | 39 ++++++------ .../variant_STM32H573I_DK.cpp | 59 ++++++++++--------- .../H563R(G-I)T_H573RIT/generic_clock.c | 47 ++++++++------- .../H563Z(G-I)T_H573ZIT/generic_clock.c | 39 ++++++------ .../variant_NUCLEO_H563ZI.cpp | 57 +++++++++--------- .../variant_NUCLEO_H563ZI.h | 6 +- 14 files changed, 254 insertions(+), 258 deletions(-) diff --git a/variants/STM32H5xx/H503CB(T-U)/generic_clock.c b/variants/STM32H5xx/H503CB(T-U)/generic_clock.c index 914aa62e0f..e551c58b58 100644 --- a/variants/STM32H5xx/H503CB(T-U)/generic_clock.c +++ b/variants/STM32H5xx/H503CB(T-U)/generic_clock.c @@ -33,20 +33,20 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -63,7 +63,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -78,17 +77,17 @@ WEAK void SystemClock_Config(void) | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; @@ -96,11 +95,6 @@ WEAK void SystemClock_Config(void) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } - - - /** Configure the programming delay - */ - __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H503KBU/generic_clock.c b/variants/STM32H5xx/H503KBU/generic_clock.c index 9963cdf75a..97c81ecb17 100644 --- a/variants/STM32H5xx/H503KBU/generic_clock.c +++ b/variants/STM32H5xx/H503KBU/generic_clock.c @@ -33,30 +33,29 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -64,33 +63,38 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_USB; + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 + | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } - } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H503RBT/generic_clock.c b/variants/STM32H5xx/H503RBT/generic_clock.c index 2ac59ece4c..05793477a7 100644 --- a/variants/STM32H5xx/H503RBT/generic_clock.c +++ b/variants/STM32H5xx/H503RBT/generic_clock.c @@ -24,35 +24,38 @@ WEAK void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /* Configure the main internal regulator output voltage */ + /** Configure the main internal regulator output voltage + */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} - /* Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /* Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -68,22 +71,23 @@ WEAK void SystemClock_Config(void) */ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); - /* Initializes the peripherals clock */ + /** Initializes the peripherals clock + */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp index 1bdf66f48a..e3dfb8cbb2 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.cpp @@ -109,7 +109,8 @@ WEAK void SystemClock_Config(void) RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; - /* Configure the main internal regulator output voltage */ + /** Configure the main internal regulator output voltage + */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} @@ -120,29 +121,32 @@ WEAK void SystemClock_Config(void) HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); - /* Initializes the RCC Oscillators according to the specified parameters in the RCC_OscInitTypeDef structure */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /* Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -150,7 +154,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -159,22 +162,23 @@ WEAK void SystemClock_Config(void) */ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); - /* Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADCDAC - | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; diff --git a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h index f9b1282e19..ac10a32bce 100644 --- a/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h +++ b/variants/STM32H5xx/H503RBT/variant_NUCLEO_H503RB.h @@ -157,13 +157,14 @@ #define PIN_SERIAL_TX PA4 #endif -#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ - // Extra HAL modules #if !defined(HAL_DAC_MODULE_DISABLED) #define HAL_DAC_MODULE_ENABLED #endif +// Value of the External oscillator in Hz +#define HSE_VALUE 24000000UL + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ @@ -190,4 +191,4 @@ #ifndef SERIAL_PORT_HARDWARE #define SERIAL_PORT_HARDWARE Serial #endif -#endif \ No newline at end of file +#endif diff --git a/variants/STM32H5xx/H562R(G-I)T/generic_clock.c b/variants/STM32H5xx/H562R(G-I)T/generic_clock.c index 346843eb6d..1a0abf62c2 100644 --- a/variants/STM32H5xx/H562R(G-I)T/generic_clock.c +++ b/variants/STM32H5xx/H562R(G-I)T/generic_clock.c @@ -33,30 +33,29 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -64,7 +63,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -74,47 +72,42 @@ WEAK void SystemClock_Config(void) __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; - PeriphClkInitStruct.PLL2.PLL2R = 10; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; - PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; PeriphClkInitStruct.PLL3.PLL3M = 2; PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } - - /** Configure the programming delay - */ - __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp b/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp index de8d46e0f5..181291d8c0 100644 --- a/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp +++ b/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.cpp @@ -112,30 +112,29 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } - /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -143,7 +142,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -153,40 +151,39 @@ WEAK void SystemClock_Config(void) __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); /** Initializes the peripherals clock - */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; - PeriphClkInitStruct.PLL2.PLL2R = 10; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; - PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; PeriphClkInitStruct.PLL3.PLL3M = 2; PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL1Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.h b/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.h index 795a583011..7de50c267b 100644 --- a/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.h +++ b/variants/STM32H5xx/H562R(G-I)T/variant_WEACT_H562RG.h @@ -222,8 +222,6 @@ P1 P2 #define HAL_SD_MODULE_ENABLED #endif -#define HSE_VALUE 8000000UL - // SD card slot Definitions // SDMMC signals not available #define SDMMC_CDIR_NA @@ -257,6 +255,8 @@ P1 P2 #define SDX_CK PC12 #endif +#define HSE_VALUE 8000000UL + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c index 341cde4070..804709efd0 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/generic_clock.c @@ -33,20 +33,20 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -55,7 +55,7 @@ WEAK void SystemClock_Config(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -63,7 +63,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -74,19 +73,18 @@ WEAK void SystemClock_Config(void) /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 - | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_SDMMC1 + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 - | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 - | RCC_PERIPHCLK_USB; + | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; @@ -96,21 +94,20 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.OspiClockSelection = RCC_OSPICLKSOURCE_HCLK; PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp index 0d4f520fb1..bff522d755 100644 --- a/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp +++ b/variants/STM32H5xx/H563IIKxQ_H573IIKxQ/variant_STM32H573I_DK.cpp @@ -205,18 +205,22 @@ WEAK void SystemClock_Config(void) while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + /** Configure LSE Drive Capability + * Warning : Only applied when the LSE is disabled. + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI - | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 5; @@ -233,7 +237,7 @@ WEAK void SystemClock_Config(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -241,7 +245,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -252,44 +255,44 @@ WEAK void SystemClock_Config(void) /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 - | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6 - | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_USB; - PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 32; - PeriphClkInitStruct.PLL2.PLL2P = 1; - PeriphClkInitStruct.PLL2.PLL2Q = 4; - PeriphClkInitStruct.PLL2.PLL2R = 2; + | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6; + PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; + PeriphClkInitStruct.PLL2.PLL2M = 5; + PeriphClkInitStruct.PLL2.PLL2N = 100; + PeriphClkInitStruct.PLL2.PLL2P = 2; + PeriphClkInitStruct.PLL2.PLL2Q = 15; + PeriphClkInitStruct.PLL2.PLL2R = 4; PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; - PeriphClkInitStruct.PLL3.PLL3M = 2; - PeriphClkInitStruct.PLL3.PLL3N = 125; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + PeriphClkInitStruct.PLL3.PLL3M = 5; + PeriphClkInitStruct.PLL3.PLL3N = 50; PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_2; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; - PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL2P; - PeriphClkInitStruct.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL2P; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVP | RCC_PLL3_DIVQ; + PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL3P; + PeriphClkInitStruct.Sai2ClockSelection = RCC_SAI2CLKSOURCE_PLL3P; PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c b/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c index 8a4327650f..3ce37be061 100644 --- a/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c +++ b/variants/STM32H5xx/H563R(G-I)T_H573RIT/generic_clock.c @@ -34,20 +34,20 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -56,7 +56,7 @@ WEAK void SystemClock_Config(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -64,7 +64,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -75,38 +74,38 @@ WEAK void SystemClock_Config(void) /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1 + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 - | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6 - | RCC_PERIPHCLK_USB; + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; - PeriphClkInitStruct.PLL2.PLL2R = 8; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2R = 4; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; - PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; - PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_CSI; PeriphClkInitStruct.PLL3.PLL3M = 2; PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c index f983f04d9c..eb6d45bfed 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/generic_clock.c @@ -34,20 +34,20 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSI - | RCC_OSCILLATORTYPE_CSI; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.CSIState = RCC_CSI_ON; RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 125; + RCC_OscInitStruct.PLL.PLLM = 2; + RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -56,7 +56,7 @@ WEAK void SystemClock_Config(void) /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -64,7 +64,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -76,17 +75,17 @@ WEAK void SystemClock_Config(void) /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC - | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 - | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 - | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 - | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_USB; + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 + | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI; - PeriphClkInitStruct.PLL2.PLL2M = 1; - PeriphClkInitStruct.PLL2.PLL2N = 125; + PeriphClkInitStruct.PLL2.PLL2M = 2; + PeriphClkInitStruct.PLL2.PLL2N = 250; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; @@ -96,20 +95,20 @@ WEAK void SystemClock_Config(void) PeriphClkInitStruct.PLL3.PLL3P = 2; PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_3; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; - PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL2R; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp index 6446bceb5b..97bea6a4c8 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.cpp @@ -188,27 +188,30 @@ WEAK void SystemClock_Config(void) /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_CSI | RCC_OSCILLATORTYPE_HSI48 + | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.CSIState = RCC_CSI_ON; + RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 250; RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB buses clocks */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; @@ -216,7 +219,6 @@ WEAK void SystemClock_Config(void) RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { Error_Handler(); } @@ -227,42 +229,41 @@ WEAK void SystemClock_Config(void) /** Initializes the peripherals clock */ - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADCDAC - | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI1 - | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 - | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_SPI5 - | RCC_PERIPHCLK_SPI6; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_ADCDAC + | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_USB + | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 + | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4 + | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_SPI6; PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE; - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 125; - PeriphClkInitStruct.PLL2.PLL2P = 10; + PeriphClkInitStruct.PLL2.PLL2M = 4; + PeriphClkInitStruct.PLL2.PLL2N = 250; + PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 15; PeriphClkInitStruct.PLL2.PLL2R = 4; - PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2; + PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE; PeriphClkInitStruct.PLL2.PLL2FRACN = 0; - PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVP | RCC_PLL2_DIVQ - | RCC_PLL2_DIVR; + PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ | RCC_PLL2_DIVR; PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; - PeriphClkInitStruct.PLL3.PLL3M = 2; - PeriphClkInitStruct.PLL3.PLL3N = 96; + PeriphClkInitStruct.PLL3.PLL3M = 4; + PeriphClkInitStruct.PLL3.PLL3N = 125; PeriphClkInitStruct.PLL3.PLL3P = 2; - PeriphClkInitStruct.PLL3.PLL3Q = 8; + PeriphClkInitStruct.PLL3.PLL3Q = 5; PeriphClkInitStruct.PLL3.PLL3R = 2; - PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0; - PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; - PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q; PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R; - PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL2P; - PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL2P; - PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL2P; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PLL2Q; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q; + PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q; PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi5ClockSelection = RCC_SPI5CLKSOURCE_PLL3Q; PeriphClkInitStruct.Spi6ClockSelection = RCC_SPI6CLKSOURCE_PLL3Q; - PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } diff --git a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h index 0019181e6b..6741386632 100644 --- a/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h +++ b/variants/STM32H5xx/H563Z(G-I)T_H573ZIT/variant_NUCLEO_H563ZI.h @@ -254,12 +254,12 @@ #define HAL_SD_MODULE_ENABLED #endif -// Value of the HSE Bypass in Hz -#define HSE_VALUE 8000000U - // Pin UCPD to configure TCPP in default Type-C legacy state (UCPD_DBn for TCPP01) #define PIN_UCPD_TCPP PA9 +// Value of the HSE Bypass in Hz +#define HSE_VALUE 8000000U + /*---------------------------------------------------------------------------- * Arduino objects - C++ only *----------------------------------------------------------------------------*/ From 55e4695ce625d24758b96756b6e7dbda8d09b35e Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Mon, 31 Mar 2025 16:43:27 +0200 Subject: [PATCH 14/22] ci: harden python scripts Signed-off-by: Frederic Pillon --- CI/update/fqbn.py | 5 +- CI/update/stm32cube.py | 70 +++++++++++------------ CI/update/stm32svd.py | 8 +-- CI/update/stm32variant.py | 115 ++++++++++++++++++-------------------- CI/update/stm32wrapper.py | 56 +++++++++---------- 5 files changed, 122 insertions(+), 132 deletions(-) diff --git a/CI/update/fqbn.py b/CI/update/fqbn.py index 4c9dde4e5e..25d0033907 100644 --- a/CI/update/fqbn.py +++ b/CI/update/fqbn.py @@ -66,7 +66,7 @@ def get_fqbn_list(): for fqbn in fqbn_list_tmp: try: output = subprocess.check_output( - [arduino_cli, "board", "details", "--format", "json", fqbn], + [arduino_cli, "board", "details", "--format", "json", "-b", fqbn], stderr=subprocess.DEVNULL, ).decode("utf-8") board_detail = json.loads(output) @@ -106,8 +106,7 @@ def main(): arg_board_pattern = re.compile(args.board, re.IGNORECASE) for fqbn in fqbn_list: - if args.board: - if arg_board_pattern.search(fqbn) is None: + if args.board and arg_board_pattern.search(fqbn) is None: continue print(fqbn) diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index 09e0db29fb..5732fa769e 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -96,9 +96,8 @@ def checkConfig(): config_file_path = script_path / "update_config.json" if config_file_path.is_file(): try: - config_file = open(config_file_path, "r") - path_config = json.load(config_file) - config_file.close() + with open(config_file_path, "r") as config_file: + path_config = json.load(config_file) # Common path if "REPO_LOCAL_PATH" not in path_config: path_config["REPO_LOCAL_PATH"] = str(repo_local_path) @@ -201,9 +200,8 @@ def createSystemFiles(serie): stm32_hal_conf_file = system_serie / stm32yyxx_hal_conf_file.replace( "yy", serie.lower() ) - out_file = open(stm32_hal_conf_file, "w", newline="\n") - out_file.write(stm32yyxx_hal_conf_file_template.render(serie=serie)) - out_file.close() + with open(stm32_hal_conf_file, "w", newline="\n") as out_file: + out_file.write(stm32yyxx_hal_conf_file_template.render(serie=serie)) # Copy system_stm32*.c file from CMSIS device template system_stm32_path = cmsis_dest_path / f"STM32{serie}xx" / "Source" / "Templates" filelist = sorted(system_stm32_path.glob("system_stm32*.c")) @@ -365,36 +363,36 @@ def parseVersion(path, patterns): sub1_found = False sub2_found = False rc_found = False - - for i, line in enumerate(open(path, encoding="utf8", errors="ignore")): - for match in re.finditer(patterns[0], line): - VERSION_MAIN = int(match.group(1), 16) - main_found = True - for match in re.finditer(patterns[1], line): - VERSION_SUB1 = int(match.group(1), 16) - sub1_found = True - for match in re.finditer(patterns[2], line): - VERSION_SUB2 = int(match.group(1), 16) - sub2_found = True - for match in re.finditer(patterns[3], line): - VERSION_RC = int(match.group(1), 16) - rc_found = True - if main_found and sub1_found and sub2_found and rc_found: - break - else: - print(f"Could not find the full version in {path}") - if main_found: - print(f"main version found: {VERSION_MAIN}") - VERSION_MAIN = "FF" - if sub1_found: - print(f"sub1 version found: {VERSION_SUB1}") - VERSION_SUB1 = "FF" - if sub2_found: - print(f"sub2 version found: {VERSION_SUB2}") - VERSION_SUB2 = "FF" - if rc_found: - print(f"rc version found: {VERSION_RC}") - VERSION_RC = "FF" + with open(path, encoding="utf8", errors="ignore") as fp: + for _i, line in enumerate(fp): + for match in re.finditer(patterns[0], line): + VERSION_MAIN = int(match.group(1), 16) + main_found = True + for match in re.finditer(patterns[1], line): + VERSION_SUB1 = int(match.group(1), 16) + sub1_found = True + for match in re.finditer(patterns[2], line): + VERSION_SUB2 = int(match.group(1), 16) + sub2_found = True + for match in re.finditer(patterns[3], line): + VERSION_RC = int(match.group(1), 16) + rc_found = True + if main_found and sub1_found and sub2_found and rc_found: + break + else: + print(f"Could not find the full version in {path}") + if main_found: + print(f"main version found: {VERSION_MAIN}") + VERSION_MAIN = "FF" + if sub1_found: + print(f"sub1 version found: {VERSION_SUB1}") + VERSION_SUB1 = "FF" + if sub2_found: + print(f"sub2 version found: {VERSION_SUB2}") + VERSION_SUB2 = "FF" + if rc_found: + print(f"rc version found: {VERSION_RC}") + VERSION_RC = "FF" ret = f"{VERSION_MAIN}.{VERSION_SUB1}.{VERSION_SUB2}" diff --git a/CI/update/stm32svd.py b/CI/update/stm32svd.py index 199c8baab1..aa2babb28b 100644 --- a/CI/update/stm32svd.py +++ b/CI/update/stm32svd.py @@ -28,9 +28,8 @@ def checkConfig(): config_file_path = script_path / "update_config.json" if config_file_path.is_file(): try: - config_file = open(config_file_path, "r") - path_config = json.load(config_file) - config_file.close() + with open(config_file_path, "r") as config_file: + path_config = json.load(config_file) if "STM32CUBECLT_PATH" not in path_config: path_config["STM32CUBECLT_PATH"] = str( @@ -159,8 +158,9 @@ def main(): for serie in stm32_list: serie_dir = stm32_svd_dir / f"STM32{serie}xx" if not any(serie_dir.glob("*")): - print (f"Folder {serie_dir} is empty.") + print(f"Folder {serie_dir} is empty.") serie_dir.rmdir() + if __name__ == "__main__": main() diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index bfc9facc62..95181242a7 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -382,9 +382,8 @@ def get_gpio_af_numF1_default(pintofind, iptofind): # return "AFIO_" + iptofind .split("_")[0] + "_DISABLE" ip = iptofind.split("_")[0] afio_default = "AFIO_NONE" - if pintofind in default_afio_f1: - if ip in default_afio_f1[pintofind]: - afio_default = default_afio_f1[pintofind][ip] + if pintofind in default_afio_f1 and ip in default_afio_f1[pintofind]: + afio_default = default_afio_f1[pintofind][ip] return afio_default @@ -559,10 +558,9 @@ def store_xspi(pin, name, signal): # Store SYS pins def store_sys(pin, name, signal): - if "_WKUP" in signal: - if not any(pin.replace("_C", "") in i for i in syswkup_list): - signal = signal.replace("PWR", "SYS") - syswkup_list.append([pin, name, signal]) + if "_WKUP" in signal and not any(pin.replace("_C", "") in i for i in syswkup_list): + signal = signal.replace("PWR", "SYS") + syswkup_list.append([pin, name, signal]) # Store USB pins @@ -1341,7 +1339,7 @@ def print_pinamevar(): alt_syswkup_list = [] for idx, syswkup_list in enumerate(syswkup_pins_list, start=1): if len(syswkup_list) > 1: - for idx2, lst in enumerate(syswkup_list[1:], start=1): + for idx2, _lst in enumerate(syswkup_list[1:], start=1): alt_syswkup_list.append(f"{idx}_{idx2}") return alt_syswkup_list @@ -1375,13 +1373,13 @@ def spi_pins_variant(): for ss in spissel_list: ss_inst = ss[2].split("_", 1)[0] if mosi_inst == ss_inst: - if "PNUM_NOT_DEFINED" == ss_pin: + if ss_pin == "PNUM_NOT_DEFINED": ss_pin = ss[0].replace("_", "", 1) - elif "PNUM_NOT_DEFINED" == ss1_pin: + elif ss1_pin == "PNUM_NOT_DEFINED": ss1_pin = ss[0].replace("_", "", 1) - elif "PNUM_NOT_DEFINED" == ss2_pin: + elif ss2_pin == "PNUM_NOT_DEFINED": ss2_pin = ss[0].replace("_", "", 1) - elif "PNUM_NOT_DEFINED" == ss3_pin: + elif ss3_pin == "PNUM_NOT_DEFINED": ss3_pin = ss[0].replace("_", "", 1) break break @@ -1449,7 +1447,7 @@ def serial_pins_variant(): print("No serial instance number found!") serialnum = "-1" else: - serialtx_pin = serialtx_pin = "PNUM_NOT_DEFINED" + serialtx_pin = "PNUM_NOT_DEFINED" serialnum = "-1" print("No serial found!") return dict(instance=serialnum, rx=serialrx_pin, tx=serialtx_pin) @@ -1653,10 +1651,13 @@ def search_product_line(valueline: str, extra: str) -> str: else: break if pline >= vline: - if extra and len(product_line_list) > idx_pline + 1: - if product_line_list[idx_pline + 1] == (product_line + extra): - # Look for the next product line if contains the extra - product_line = product_line_list[idx_pline + 1] + if ( + extra + and len(product_line_list) > idx_pline + 1 + and product_line_list[idx_pline + 1] == (product_line + extra) + ): + # Look for the next product line if contains the extra + product_line = product_line_list[idx_pline + 1] break else: # In case of CMSIS device does not exist @@ -1700,9 +1701,7 @@ def parse_stm32targets(): def search_svdfile(mcu_name): - svd_file = "" - if mcu_name in svd_dict: - svd_file = svd_dict[mcu_name] + svd_file = svd_dict.get(mcu_name, "") return svd_file @@ -2275,7 +2274,7 @@ def merge_dir(out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp) # Save board entry skip = False with open(dir_name / boards_entry_filename) as fp: - for index, line in enumerate(fp): + for _index, line in enumerate(fp): # Skip until next empty line (included) if skip: if line == "\n": @@ -2391,24 +2390,23 @@ def aggregate_dir(): periph_xml_tmp = [] variant_exp_tmp = [] for index2, fname in enumerate(mcu_dir1_files_list): - with open(fname, "r") as f1: - with open(mcu_dir2_files_list[index2], "r") as f2: - diff = set(f1).symmetric_difference(f2) - diff.discard("\n") - if not diff or len(diff) == 2: - if index2 == 0: - for line in diff: - periph_xml_tmp += periperalpins_regex.findall( - line - ) - elif index2 == 2: - for line in diff: - variant_exp_tmp += variant_regex.findall(line) - continue - else: - # Not the same directory compare with the next one - index += 1 - break + with open(fname, "r") as f1, open( + mcu_dir2_files_list[index2], "r" + ) as f2: + diff = set(f1).symmetric_difference(f2) + diff.discard("\n") + if not diff or len(diff) == 2: + if index2 == 0: + for line in diff: + periph_xml_tmp += periperalpins_regex.findall(line) + elif index2 == 2: + for line in diff: + variant_exp_tmp += variant_regex.findall(line) + continue + else: + # Not the same directory compare with the next one + index += 1 + break # All files compared and matched else: # Concatenate lists without duplicate @@ -2505,10 +2503,11 @@ def checkConfig(): default_cubemxdir() if config_filename.is_file(): try: - config_file = open(config_filename, "r") - path_config = json.load(config_file) - config_file.close() - + # config_file = open(config_filename, "r") + # path_config = json.load(config_file) + # config_file.close() + with open(config_filename, "r") as config_file: + path_config = json.load(config_file) if "REPO_LOCAL_PATH" not in path_config: path_config["REPO_LOCAL_PATH"] = str(repo_local_path) defaultConfig(config_filename, path_config) @@ -2779,21 +2778,21 @@ def manage_repo(): generic_clock_filepath = out_temp_path / generic_clock_filename out_temp_path.mkdir(parents=True, exist_ok=True) - # open output file - periph_c_file = open(periph_c_filepath, "w", newline="\n") - pinvar_h_file = open(pinvar_h_filepath, "w", newline="\n") - variant_cpp_file = open(variant_cpp_filepath, "w", newline="\n") - variant_h_file = open(variant_h_filepath, "w", newline="\n") - boards_entry_file = open(boards_entry_filepath, "w", newline="\n") - generic_clock_file = open(generic_clock_filepath, "w", newline="\n") parse_pins() manage_af_and_alternate() - generic_list = print_boards_entry() - print_general_clock(generic_list) - print_peripheral() - alt_syswkup_list = print_pinamevar() - print_variant(generic_list, alt_syswkup_list) + with open(boards_entry_filepath, "w", newline="\n") as boards_entry_file: + generic_list = print_boards_entry() + with open(generic_clock_filepath, "w", newline="\n") as generic_clock_file: + print_general_clock(generic_list) + with open(periph_c_filepath, "w", newline="\n") as periph_c_file: + print_peripheral() + with open(pinvar_h_filepath, "w", newline="\n") as pinvar_h_file: + alt_syswkup_list = print_pinamevar() + with open(variant_cpp_filepath, "w", newline="\n") as variant_cpp_file, open( + variant_h_filepath, "w", newline="\n" + ) as variant_h_file: + print_variant(generic_list, alt_syswkup_list) del alt_syswkup_list[:] del generic_list[:] sum_io = len(io_list) + len(alt_list) + len(dualpad_list) + len(remap_list) @@ -2810,12 +2809,6 @@ def manage_repo(): clean_all_lists() - periph_c_file.close() - pinvar_h_file.close() - variant_h_file.close() - variant_cpp_file.close() - boards_entry_file.close() - generic_clock_file.close() xml_mcu.unlink() xml_gpio.unlink() diff --git a/CI/update/stm32wrapper.py b/CI/update/stm32wrapper.py index ac1d24d917..2132944c71 100644 --- a/CI/update/stm32wrapper.py +++ b/CI/update/stm32wrapper.py @@ -129,9 +129,8 @@ def printCMSISStartup(log): vline = valueline[1].upper().replace("X", "x") cm = valueline[2].upper() cmsis_list.append({"vline": vline, "fn": fn, "cm": cm}) - out_file = open(CMSIS_Startupfile, "w", newline="\n") - out_file.write(stm32_def_build_template.render(cmsis_list=cmsis_list)) - out_file.close() + with open(CMSIS_Startupfile, "w", newline="\n") as out_file: + out_file.write(stm32_def_build_template.render(cmsis_list=cmsis_list)) else: if log: print("No startup files found!") @@ -145,9 +144,8 @@ def printSystemSTM32(log): system_list = [] for fp in filelist: system_list.append({"serie": fp.parent.name, "fn": fp.name}) - out_file = open(system_stm32_outfile, "w", newline="\n") - out_file.write(system_stm32_template.render(system_list=system_list)) - out_file.close() + with open(system_stm32_outfile, "w", newline="\n") as out_file: + out_file.write(system_stm32_template.render(system_list=system_list)) else: if log: print("No system stm32 files found!") @@ -186,7 +184,7 @@ def wrap(arg_core, arg_cmsis, log): # Search stm32yyxx_[hal|ll]*.c file filelist = src.glob(f"**/stm32{lower}xx_*.c") for fp in filelist: - legacy = True if fp.parent.name == "Legacy" else False + legacy = fp.parent.name == "Legacy" # File name fn = fp.name found = peripheral_c_regex.match(fn) @@ -242,30 +240,32 @@ def wrap(arg_core, arg_cmsis, log): filepath = HALoutSrc_path / c_file.replace("zz", "hal").replace("_ppp", "") else: filepath = HALoutSrc_path / c_file.replace("zz", "hal").replace("ppp", key) - out_file = open(filepath, "w", newline="\n") - out_file.write(c_file_template.render(periph=key, type="hal", serieslist=value)) - out_file.close() + with open(filepath, "w", newline="\n") as out_file: + out_file.write( + c_file_template.render(periph=key, type="hal", serieslist=value) + ) # Generate stm32yyxx_ll_*.c file for key, value in ll_c_dict.items(): filepath = LLoutSrc_path / c_file.replace("zz", "ll").replace("ppp", key) - out_file = open(filepath, "w", newline="\n") - out_file.write(c_file_template.render(periph=key, type="ll", serieslist=value)) - out_file.close() + with open(filepath, "w", newline="\n") as out_file: + out_file.write( + c_file_template.render(periph=key, type="ll", serieslist=value) + ) # Generate stm32yyxx_ll_*.h file for key, value in ll_h_dict.items(): filepath = LLoutInc_path / ll_h_file.replace("ppp", key) - out_file = open(filepath, "w", newline="\n") - out_file.write(ll_h_file_template.render(periph=key, serieslist=value)) - out_file.close() + with open(filepath, "w", newline="\n") as out_file: + out_file.write(ll_h_file_template.render(periph=key, serieslist=value)) if log: print("done") # Filter all LL header file all_ll_h_list = sorted(set(all_ll_h_list)) # Generate the all LL header file - all_ll_file = open(LLoutInc_path / all_ll_h_file, "w", newline="\n") - all_ll_file.write(all_ll_header_file_template.render(ll_header_list=all_ll_h_list)) - all_ll_file.close() + with open(LLoutInc_path / all_ll_h_file, "w", newline="\n") as all_ll_file: + all_ll_file.write( + all_ll_header_file_template.render(ll_header_list=all_ll_h_list) + ) # CMSIS startup files printCMSISStartup(log) @@ -280,15 +280,15 @@ def wrap(arg_core, arg_cmsis, log): # Delete all subfolders deleteFolder(CMSIS_DSP_outSrc_path / "*") for path_object in CMSIS_DSPSrc_path.glob("**/*"): - if path_object.is_file(): - if path_object.name.endswith(".c"): - dn = path_object.parent.name - fn = path_object.name - if dn in fn: - fdn = CMSIS_DSP_outSrc_path / dn - out_file = open(fdn / (f"{fn}"), "w", newline="\n") - out_file.write(dsp_file_template.render(dsp_dir=dn, dsp_name=fn)) - out_file.close() + if path_object.is_file() and path_object.name.endswith(".c"): + dn = path_object.parent.name + fn = path_object.name + if dn in fn: + fdn = CMSIS_DSP_outSrc_path / dn + with open(fdn / (f"{fn}"), "w", newline="\n") as out_file: + out_file.write( + dsp_file_template.render(dsp_dir=dn, dsp_name=fn) + ) return 0 From b4aa21ddd116325801d737ea1fa934e325bcb17a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 18 Apr 2025 09:19:12 +0200 Subject: [PATCH 15/22] fix(doc): update url Signed-off-by: Frederic Pillon --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f8b7b0bd73..8f150229d9 100644 --- a/README.md +++ b/README.md @@ -818,7 +818,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F446VE | [RUMBA32](https://github.com/Aus3D/RUMBA32) | *1.5.0* | | | :green_heart: | STM32F401VE | [STEVAL-3DP001V1](https://www.st.com/en/evaluation-tools/steval-3dp001v1.html) | *1.6.0* | | | :green_heart: | STM32F446RE | VAkE v1.0 | *1.6.0* | | -| :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/FYSETC_S6/) | *1.9.0* | | +| :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/docs/FYSETCS6) | *1.9.0* | | | :green_heart: | STM32G0B1CB | [BTT EBB42 CAN V1.1](https://github.com/bigtreetech/EBB/tree/master) | *2.4.0* | | ### [Blues](https://blues.com/) boards From 5d402d921de02ef67264ba3feea55aadef53935d Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 18 Apr 2025 09:24:27 +0200 Subject: [PATCH 16/22] ci: schedule url check each day at 11 AM Signed-off-by: Frederic Pillon --- .github/workflows/MarkdwonLinksCheck.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/MarkdwonLinksCheck.yml b/.github/workflows/MarkdwonLinksCheck.yml index 5525a3050d..5f2220b8ad 100644 --- a/.github/workflows/MarkdwonLinksCheck.yml +++ b/.github/workflows/MarkdwonLinksCheck.yml @@ -11,6 +11,9 @@ on: - '**.md' # Allows you to run this workflow manually from the Actions tab workflow_dispatch: + schedule: + # Run every day at 12 AM UTC to check url. + - cron: "0 11 * * *" jobs: linkinator: runs-on: ubuntu-latest From fddfdeb9c7b2e664dad0733265adfdd3850f787c Mon Sep 17 00:00:00 2001 From: Antun Skuric <36178713+askuric@users.noreply.github.com> Date: Tue, 22 Apr 2025 15:35:55 +0200 Subject: [PATCH 17/22] variant(l4): add generic L412RB(I-T)xP and Nucleo L412RB-P Signed-off-by: Antun Skuric <36178713+askuric@users.noreply.github.com> Co-authored-by: Frederic Pillon --- README.md | 2 + boards.txt | 33 +++ .../STM32L4xx/L412RB(I-T)xP/CMakeLists.txt | 1 + variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld | 208 ++++++++++++++++++ .../L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp | 162 ++++++++++++++ .../L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h | 155 +++++++++++++ 6 files changed, 561 insertions(+) create mode 100644 variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld create mode 100644 variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp create mode 100644 variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h diff --git a/README.md b/README.md index 8f150229d9..3252271192 100644 --- a/README.md +++ b/README.md @@ -148,6 +148,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | | | :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | | | :green_heart: | STM32L152RE | [Nucleo L152RE](http://www.st.com/en/evaluation-tools/nucleo-l152re.html) | *1.0.0* | | +| :yellow_heart: | STM32L412RB-P | [Nucleo L412RC-P](https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html) | **2.11.0** | | | :green_heart: | STM32L433RC-P | [Nucleo L433RC-P](https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html) | *1.9.0* | | | :green_heart: | STM32L452RE | [Nucleo L452RE](http://www.st.com/en/evaluation-tools/nucleo-l452re.html) | *1.5.0* | | | :green_heart: | STM32L452RE-P | [Nucleo L452RE-P](http://www.st.com/en/evaluation-tools/nucleo-l452re-p.html) | *1.8.0* | | @@ -704,6 +705,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32L412K8
                                                                                                STM32L412KB
                                                                                                STM32L422KB | Generic Board | *2.0.0* | | +| :yellow_heart: | STM32L412RBIxP
                                                                                                STM32L412RBTxP | Generic Board | **2.11.0** | | | :green_heart: | STM32L431CB
                                                                                                STM32L431CC | Generic Board | *2.8.1* | | | :green_heart: | STM32L431RB
                                                                                                STM32L431RC | Generic Board | *2.3.0* | | | :green_heart: | STM32L432KB
                                                                                                STM32L432KC
                                                                                                STM32L442KC | Generic Board | *2.0.0* | | diff --git a/boards.txt b/boards.txt index aaebef7be9..4f64d3f800 100644 --- a/boards.txt +++ b/boards.txt @@ -758,6 +758,21 @@ Nucleo_64.menu.pnum.NUCLEO_L152RE.build.variant=STM32L1xx/L151RET_L152RET_L162RE Nucleo_64.menu.pnum.NUCLEO_L152RE.openocd.target=stm32l1 Nucleo_64.menu.pnum.NUCLEO_L152RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd +# NUCLEO_L412RB_P board +Nucleo_64.menu.pnum.NUCLEO_L412RB_P=Nucleo L412RB-P +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.node=NODE_L412RB +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.upload.maximum_size=131072 +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.upload.maximum_data_size=40960 +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.mcu=cortex-m4 +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.float-abi=-mfloat-abi=hard +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.board=NUCLEO_L412RB_P +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.series=STM32L4xx +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.product_line=STM32L412xx +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.build.variant=STM32L4xx/L412RB(I-T)xP +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.openocd.target=stm32l4x +Nucleo_64.menu.pnum.NUCLEO_L412RB_P.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd + # NUCLEO_L433RC_P board Nucleo_64.menu.pnum.NUCLEO_L433RC_P=Nucleo L433RC-P Nucleo_64.menu.pnum.NUCLEO_L433RC_P.node=NODE_L433RC @@ -11471,6 +11486,24 @@ GenL4.menu.pnum.GENERIC_L412KBUX.build.product_line=STM32L412xx GenL4.menu.pnum.GENERIC_L412KBUX.build.variant=STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U) GenL4.menu.pnum.GENERIC_L412KBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd +# Generic L412RBIxP +GenL4.menu.pnum.GENERIC_L412RBIXP=Generic L412RBIxP +GenL4.menu.pnum.GENERIC_L412RBIXP.upload.maximum_size=131072 +GenL4.menu.pnum.GENERIC_L412RBIXP.upload.maximum_data_size=40960 +GenL4.menu.pnum.GENERIC_L412RBIXP.build.board=GENERIC_L412RBIXP +GenL4.menu.pnum.GENERIC_L412RBIXP.build.product_line=STM32L412xx +GenL4.menu.pnum.GENERIC_L412RBIXP.build.variant=STM32L4xx/L412RB(I-T)xP +GenL4.menu.pnum.GENERIC_L412RBIXP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd + +# Generic L412RBTxP +GenL4.menu.pnum.GENERIC_L412RBTXP=Generic L412RBTxP +GenL4.menu.pnum.GENERIC_L412RBTXP.upload.maximum_size=131072 +GenL4.menu.pnum.GENERIC_L412RBTXP.upload.maximum_data_size=40960 +GenL4.menu.pnum.GENERIC_L412RBTXP.build.board=GENERIC_L412RBTXP +GenL4.menu.pnum.GENERIC_L412RBTXP.build.product_line=STM32L412xx +GenL4.menu.pnum.GENERIC_L412RBTXP.build.variant=STM32L4xx/L412RB(I-T)xP +GenL4.menu.pnum.GENERIC_L412RBTXP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd + # Generic L422KBTx GenL4.menu.pnum.GENERIC_L422KBTX=Generic L422KBTx GenL4.menu.pnum.GENERIC_L422KBTX.upload.maximum_size=131072 diff --git a/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt b/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt index 2a4d55b6b1..3eab75f214 100644 --- a/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt +++ b/variants/STM32L4xx/L412RB(I-T)xP/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_L412RB_P.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld b/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld new file mode 100644 index 0000000000..9eb56d5d17 --- /dev/null +++ b/variants/STM32L4xx/L412RB(I-T)xP/ldscript.ld @@ -0,0 +1,208 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32L412RBTxP series +** 128Kbytes FLASH and 40Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

                                                                                                © COPYRIGHT(c) 2025 STMicroelectronics

                                                                                                +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE +RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 8K +FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(8); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(8); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(8); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(8); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(8); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(8); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(8); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(8); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(8); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(8); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(8); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + + { + . = ALIGN(8); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(8); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(8); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(8); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +} + + diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp new file mode 100644 index 0000000000..9b79190615 --- /dev/null +++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.cpp @@ -0,0 +1,162 @@ +/* + ******************************************************************************* + * Copyright (c) 2021, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_L412RB_P) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_10, + PA_9, + PA_12, + PB_3, + PB_5, + PA_15, + PB_10, + PC_7, + PB_6, + PA_8, + PA_11, + PB_15, + PB_14, + PB_13, // LED + PB_7, + PB_8, + // ST Morpho + // CN5 Left Side + PC_10, + PC_12, + PB_12, + PA_13, + PA_14, + PC_13, // User Button + PC_14, + PC_15, + PH_0, + PH_1, + PB_4, + PB_9, + // CN5 Right Side + PC_11, + // CN6 Left Side + PC_9, + // CN6 Right Side + PC_8, + PC_6, + PB_0, + PB_11, + PB_2, + PB_1, + PA_7, + PA_6, + PA_5, + PA_4, + PC_4, + PA_3, // STLink Rx + PA_2, // STLink Tx + PA_0, + PA_1, + PC_3, + PC_2, + PC_1, + PC_0, + PH_3 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 43, //A0 + 44, //A1 + 45, //A2 + 46, //A3 + 47, //A4 + 48, //A5 + 32, //A6 + 35, //A7 + 36, //A8 + 37, //A9 + 38, //A10 + 39, //A11 + 40 //A12 +}; + + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + + + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /* Configure LSE Drive Capability */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + /* + * Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + /* MSI is enabled after System reset, activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 + clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } + /* Configure the main internal regulator output voltage */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + /* Enable MSI Auto calibration */ + HAL_RCCEx_EnableMSIPLLMode(); +} + + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_NUCLEO_L412RB_P */ diff --git a/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h new file mode 100644 index 0000000000..a3bb945b4a --- /dev/null +++ b/variants/STM32L4xx/L412RB(I-T)xP/variant_NUCLEO_L412RB_P.h @@ -0,0 +1,155 @@ +/* + ******************************************************************************* + * Copyright (c) 2021, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * Pins + *----------------------------------------------------------------------------*/ + +#define PA10 0 // SB33 ON / SB32 OFF +#define PA9 1 // SB35 ON / SB34 OFF +#define PA12 2 +#define PB3 3 +#define PB5 4 +#define PA15 5 +#define PB10 6 +#define PC7 7 +#define PB6 8 +#define PA8 9 +#define PA11 10 +#define PB15 11 +#define PB14 12 +#define PB13 13 // LED +#define PB7 14 +#define PB8 15 +// ST Morpho +// CN5 Left Side +#define PC10 16 +#define PC12 17 +#define PB12 18 +#define PA13 19 +#define PA14 20 +#define PC13 21 // User Button +#define PC14 22 +#define PC15 23 +#define PH0 24 +#define PH1 25 +#define PB4 26 +#define PB9 27 +// CN5 Right Side +#define PC11 28 +// CN6 Left Side +#define PC9 29 +// CN6 Right Side +#define PC8 30 +#define PC6 31 +#define PB0 PIN_A6 +#define PB11 33 +#define PB2 34 +#define PB1 PIN_A7 +#define PA7 PIN_A8 +#define PA6 PIN_A9 +#define PA5 PIN_A10 +#define PA4 PIN_A11 +#define PC4 PIN_A12 +#define PA3 41 // STLink Rx +#define PA2 42 // STLink Tx +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PC3 PIN_A2 +#define PC2 PIN_A3 +#define PC1 PIN_A4 +#define PC0 PIN_A5 +#define PH3 49 + +// Alternate pins number +#define PA1_ALT1 (PA1 | ALT1) +#define PA2_ALT1 (PA2 | ALT1) +#define PA3_ALT1 (PA3 | ALT1) +#define PA4_ALT1 (PA4 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA15_ALT1 (PA15 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB13_ALT1 (PB13 | ALT1) +#define PB14_ALT1 (PB14 | ALT1) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 50 +#define NUM_ANALOG_INPUTS 13 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PB13 +#endif +#ifndef LED_GREEN + #define LED_GREEN LED_BUILTIN +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + +// Timer Definitions (optional) +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM16 +#endif + +// UART Definitions +// Define here Serial instance number to map on Serial generic name +#define SERIAL_UART_INSTANCE 101 + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Enable QSPI +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #define SERIAL_PORT_MONITOR Serial + #define SERIAL_PORT_HARDWARE Serial +#endif From 6a987257c90b5ed21e23715ed083a6e5db3b9519 Mon Sep 17 00:00:00 2001 From: patricklaf Date: Tue, 15 Apr 2025 16:09:56 +0200 Subject: [PATCH 18/22] chore(uart): harden init Signed-off-by: patricklaf --- cores/arduino/HardwareSerial.cpp | 10 +++-- cores/arduino/HardwareSerial.h | 3 +- libraries/SrcWrapper/inc/uart.h | 2 +- libraries/SrcWrapper/src/stm32/uart.c | 54 +++++++++++++++------------ 4 files changed, 41 insertions(+), 28 deletions(-) diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index 4dd8fd02a4..cde5cab7e0 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -446,13 +446,17 @@ void HardwareSerial::begin(unsigned long baud, byte config) break; } - uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert); - enableHalfDuplexRx(); - uart_attach_rx_callback(&_serial, _rx_complete_irq); + _ready = uart_init(&_serial, (uint32_t)baud, databits, parity, stopbits, _rx_invert, _tx_invert, _data_invert); + if (_ready) { + enableHalfDuplexRx(); + uart_attach_rx_callback(&_serial, _rx_complete_irq); + } } void HardwareSerial::end() { + _ready = false; + // wait for transmission of outgoing data flush(TX_TIMEOUT); diff --git a/cores/arduino/HardwareSerial.h b/cores/arduino/HardwareSerial.h index 3ed29a873d..be670e9540 100644 --- a/cores/arduino/HardwareSerial.h +++ b/cores/arduino/HardwareSerial.h @@ -146,7 +146,7 @@ class HardwareSerial : public Stream { using Print::write; // pull in write(str) from Print operator bool() { - return true; + return _ready; } void setRx(uint32_t _rx); @@ -189,6 +189,7 @@ class HardwareSerial : public Stream { #endif // HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY private: + bool _ready; bool _rx_enabled; uint8_t _config; unsigned long _baud; diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h index 7f99d498e7..5d681407f8 100644 --- a/libraries/SrcWrapper/inc/uart.h +++ b/libraries/SrcWrapper/inc/uart.h @@ -255,7 +255,7 @@ struct serial_s { /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ -void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert); +bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert); void uart_deinit(serial_t *obj); #if defined(HAL_PWR_MODULE_ENABLED) && (defined(UART_IT_WUF) || defined(LPUART1_BASE)) void uart_config_lowpower(serial_t *obj); diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 4aaa3f0e2e..14e431dc09 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -113,12 +113,12 @@ serial_t *get_serial_obj(UART_HandleTypeDef *huart) /** * @brief Function called to initialize the uart interface * @param obj : pointer to serial_t structure - * @retval None + * @retval boolean status */ -void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert) +bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t parity, uint32_t stopbits, bool rx_invert, bool tx_invert, bool data_invert) { if (obj == NULL) { - return; + return false; } UART_HandleTypeDef *huart = &(obj->handle); @@ -143,28 +143,28 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] Tx pin has no peripheral!\n"); } - return; + return false; } /* Pin Rx must not be NP if not half-duplex */ if ((obj->pin_rx != NC) && (uart_rx == NP) && (uart_rx_swap == NP)) { if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] Rx pin has no peripheral!\n"); } - return; + return false; } /* Pin RTS must not be NP if flow control is enabled */ if ((obj->pin_rts != NC) && (uart_rts == NP)) { if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] RTS pin has no peripheral!\n"); } - return; + return false; } /* Pin CTS must not be NP if flow control is enabled */ if ((obj->pin_cts != NC) && (uart_cts == NP)) { if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] CTS pin has no peripheral!\n"); } - return; + return false; } /* @@ -184,7 +184,7 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj != &serial_debug) { core_debug("ERROR: [U(S)ART] Rx/Tx/RTS/CTS pins peripherals mismatch!\n"); } - return; + return false; } /* Enable USART clock */ @@ -364,6 +364,12 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par obj->irq = UART12_IRQn; } #endif + else { + if (obj != &serial_debug) { + core_debug("ERROR: [U(S)ART] Peripheral not supported!\n"); + } + return false; + } /* Configure UART GPIO pins */ #if defined(UART_ADVFEATURE_SWAP_INIT) uint32_t pin_swap = UART_ADVFEATURE_SWAP_DISABLE; @@ -468,10 +474,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par /* Trying default LPUART clock source */ if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return; + return true; } } else if (HAL_UART_Init(huart) == HAL_OK) { - return; + return true; } /* Trying to change LPUART clock source */ /* If baudrate is lower than or equal to 9600 try to change to LSE */ @@ -494,10 +500,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return; + return true; } } else if (HAL_UART_Init(huart) == HAL_OK) { - return; + return true; } } } @@ -517,10 +523,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return; + return true; } } else if (HAL_UART_Init(huart) == HAL_OK) { - return; + return true; } } if (obj->uart == LPUART1) { @@ -544,10 +550,10 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par #endif if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { - return; + return true; } } else if (HAL_UART_Init(huart) == HAL_OK) { - return; + return true; } #if defined(RCC_LPUART1CLKSOURCE_SYSCLK) if (obj->uart == LPUART1) { @@ -569,11 +575,12 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if ((uart_rx == NP) && (uart_rx_swap == NP)) { if (HAL_HalfDuplex_Init(huart) != HAL_OK) { - return; + return false; } } else if (HAL_UART_Init(huart) != HAL_OK) { - return; + return false; } + return true; } /** @@ -821,10 +828,11 @@ void uart_config_lowpower(serial_t *obj) * @note Call only if debug U(S)ART peripheral is not already initialized * by a Serial instance * Default config: 8N1 - * @retval None + * @retval boolean status */ -void uart_debug_init(void) +bool uart_debug_init(void) { + bool status = false; if (DEBUG_UART != NP) { #if defined(DEBUG_PINNAME_TX) serial_debug.pin_tx = DEBUG_PINNAME_TX; @@ -832,8 +840,9 @@ void uart_debug_init(void) serial_debug.pin_tx = pinmap_pin(DEBUG_UART, PinMap_UART_TX); #endif /* serial_debug.pin_rx set by default to NC to configure in half duplex mode */ - uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false); + status = uart_init(&serial_debug, DEBUG_UART_BAUDRATE, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, false, false, false); } + return status; } /** @@ -863,8 +872,7 @@ size_t uart_debug_write(uint8_t *data, uint32_t size) if (serial_debug.index >= UART_NUM) { /* DEBUG_UART not initialized */ - uart_debug_init(); - if (serial_debug.index >= UART_NUM) { + if (!uart_debug_init()) { return 0; } } From 61b4df866945c745981eeb434492d45fcb1e6d1f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 25 Apr 2025 11:21:18 +0200 Subject: [PATCH 19/22] fix(uart): unused warnings Fixes #2718. Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/uart.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 14e431dc09..d854061655 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -438,6 +438,10 @@ bool uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par huart->AdvancedInit.DataInvert = UART_ADVFEATURE_DATAINV_ENABLE; } #endif +#else /* UART_ADVFEATURE_NO_INIT */ + UNUSED(rx_invert); + UNUSED(tx_invert); + UNUSED(data_invert); #endif #ifdef UART_ONE_BIT_SAMPLE_DISABLE huart->Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; From bb565fd657d896242e69c08e7743e7814da45773 Mon Sep 17 00:00:00 2001 From: gospar Date: Fri, 25 Apr 2025 10:17:57 +0200 Subject: [PATCH 20/22] variant(f4): add Nucleo F410RB Signed-off-by: gospar --- README.md | 1 + boards.txt | 15 ++ .../STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt | 1 + .../F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp | 150 ++++++++++++++++++ .../F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h | 140 ++++++++++++++++ 5 files changed, 307 insertions(+) create mode 100644 variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp create mode 100644 variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h diff --git a/README.md b/README.md index 3252271192..70b2e3275a 100644 --- a/README.md +++ b/README.md @@ -136,6 +136,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F302R8 | [Nucleo F302R8](http://www.st.com/en/evaluation-tools/nucleo-f302r8.html) | *1.1.0* | | | :green_heart: | STM32F303RE | [Nucleo F303RE](http://www.st.com/en/evaluation-tools/nucleo-f303re.html) | *0.1.0* | | | :green_heart: | STM32F401RE | [Nucleo F401RE](http://www.st.com/en/evaluation-tools/nucleo-f401re.html) | *0.2.1* | | +| :yellow_heart: | STM32F410RB | [Nucleo F410RB](http://www.st.com/en/evaluation-tools/nucleo-f410rb.html) | **2.11.0** | | | :green_heart: | STM32F411RE | [Nucleo F411RE](http://www.st.com/en/evaluation-tools/nucleo-f411re.html) | *0.2.1* | | | :green_heart: | STM32F446RE | [Nucleo F446RE](http://www.st.com/en/evaluation-tools/nucleo-f446re.html) | *1.1.1* | | | :green_heart: | STM32G070RB | [Nucleo G070RB](https://www.st.com/en/evaluation-tools/nucleo-g070rb.html) | *2.3.0* | | diff --git a/boards.txt b/boards.txt index 4f64d3f800..737597a70c 100644 --- a/boards.txt +++ b/boards.txt @@ -586,6 +586,21 @@ Nucleo_64.menu.pnum.NUCLEO_F401RE.build.variant=STM32F4xx/F401R(B-C-D-E)T Nucleo_64.menu.pnum.NUCLEO_F401RE.openocd.target=stm32f4x Nucleo_64.menu.pnum.NUCLEO_F401RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F401.svd +# NUCLEO_F410RB board +Nucleo_64.menu.pnum.NUCLEO_F410RB=Nucleo F410RB +Nucleo_64.menu.pnum.NUCLEO_F410RB.node="NOD_F410RB,NUCLEO" +Nucleo_64.menu.pnum.NUCLEO_F410RB.upload.maximum_size=131072 +Nucleo_64.menu.pnum.NUCLEO_F410RB.upload.maximum_data_size=32768 +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.mcu=cortex-m4 +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.float-abi=-mfloat-abi=hard +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.board=NUCLEO_F410RB +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.series=STM32F4xx +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.product_line=STM32F410Rx +Nucleo_64.menu.pnum.NUCLEO_F410RB.build.variant=STM32F4xx/F410R(8-B)(I-T) +Nucleo_64.menu.pnum.NUCLEO_F410RB.openocd.target=stm32f4x +Nucleo_64.menu.pnum.NUCLEO_F410RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F410.svd + # NUCLEO_F411RE board Nucleo_64.menu.pnum.NUCLEO_F411RE=Nucleo F411RE Nucleo_64.menu.pnum.NUCLEO_F411RE.node="NODE_F411RE,NUCLEO" diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt b/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt index 2a4d55b6b1..14f4ef4bc2 100644 --- a/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/CMakeLists.txt @@ -22,6 +22,7 @@ add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c variant_generic.cpp + variant_NUCLEO_F410RB.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp new file mode 100644 index 0000000000..18c8d1d098 --- /dev/null +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.cpp @@ -0,0 +1,150 @@ +/* + ******************************************************************************* + * Copyright (c) 2025, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_F410RB) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_3, + PA_2, + PA_10, + PB_3, + PB_5, + PB_4, + PB_10, + PA_8, + PA_9, + PC_7, + PB_6, + PA_7, + PA_6, + PA_5, + PB_9, + PB_8, + // ST Morpho + // CN7 Left Side + PC_10, + PC_12, + NC, //D18 - BOOT0 + PA_13, + PA_14, + PA_15, + PB_7, + PC_13, + PC_14, + PC_15, + PH_0, + PH_1, + PC_2, + PC_3, + // CN7 Right Side + PC_11, + PB_11, + // CN10 Left Side + PC_9, + // CN10 Right side + PC_8, + PC_6, + PC_5, + PA_12, + PA_11, + PB_12, + NC, //D39 + PB_2, + PB_1, + PB_15, + PB_14, + PB_13, + PC_4, + PA_0, + PA_1, + PA_4, + PB_0, + PC_1, + PC_0 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 46, //A0 + 47, //A1 + 48, //A2 + 49, //A3 + 50, //A4 + 51, //A5 + 11, //A6 + 12, //A7 + 13, //A8 + 28, //A9 + 29, //A10 + 35, //A11 + 41, //A12 + 45, //A13 + 0, //A14 + 1 //A15 +}; + +#ifdef __cplusplus +extern "C" { +#endif +/** + * @brief System Clock Configuration + * SYSCLK = 100MHz for ARDUINO_NUCLEO_F410RB + * @param None + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 4; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLR = 2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } +} + + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h new file mode 100644 index 0000000000..8e05086ea0 --- /dev/null +++ b/variants/STM32F4xx/F410R(8-B)(I-T)/variant_NUCLEO_F410RB.h @@ -0,0 +1,140 @@ +/* + ******************************************************************************* + * Copyright (c) 2025, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA3 PIN_A14 +#define PA2 PIN_A15 +#define PA10 2 +#define PB3 3 +#define PB5 4 +#define PB4 5 +#define PB10 6 +#define PA8 7 +#define PA9 8 +#define PC7 9 +#define PB6 10 +#define PA7 PIN_A6 +#define PA6 PIN_A7 +#define PA5 PIN_A8 // LD2 +#define PB9 14 +#define PB8 15 +// ST Morpho +// CN7 Left Side +#define PC10 16 +#define PC12 17 +// 18 is NC - BOOT0 +#define PA13 19 // SWD +#define PA14 20 // SWD +#define PA15 21 +#define PB7 22 +#define PC13 23 // USER_BTN +#define PC14 24 +#define PC15 25 +#define PH0 26 +#define PH1 27 +#define PC2 PIN_A9 +#define PC3 PIN_A10 +// CN7 Right Side +#define PC11 30 +#define PB11 31 +// CN10 Left Side +#define PC9 32 +// CN10 Right side +#define PC8 33 +#define PC6 34 +#define PC5 PIN_A11 +#define PA12 36 +#define PA11 37 +#define PB12 38 +// 39 is NC +#define PB2 40 +#define PB1 PIN_A12 +#define PB15 42 +#define PB14 43 +#define PB13 44 +#define PC4 PIN_A13 +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA4 PIN_A2 +#define PB0 PIN_A3 +#define PC1 PIN_A4 +#define PC0 PIN_A5 + +// Alternate pins number +#define PA2_ALT1 = (PA2 | ALT1) +#define PA3_ALT1 = (PA3 | ALT1) +#define PB9_ALT1 = (PB9 | ALT1) + +#define NUM_DIGITAL_PINS 52 +#define NUM_ANALOG_INPUTS 16 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PA5 +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PC13 +#endif + + +// Timer Definitions +// Use TIM9/TIM11 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM11 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 2 //Connected to ST-Link +#endif + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA3 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #define SERIAL_PORT_MONITOR Serial + #define SERIAL_PORT_HARDWARE Serial +#endif From b62c9198fd1ac1a919d93608b2adeb478baa91d6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 25 Apr 2025 14:29:45 +0200 Subject: [PATCH 21/22] chore: update cmake support with new targets Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 656 ++++++++++++++++++ .../L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt | 2 + 2 files changed, 658 insertions(+) diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 24a946c9dd..ea28c93087 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -93548,6 +93548,170 @@ target_compile_options(GENERIC_L412KBUX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_L412RBIXP +# ----------------------------------------------------------------------------- + +set(GENERIC_L412RBIXP_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP") +set(GENERIC_L412RBIXP_MAXSIZE 131072) +set(GENERIC_L412RBIXP_MAXDATASIZE 40960) +set(GENERIC_L412RBIXP_MCU cortex-m4) +set(GENERIC_L412RBIXP_FPCONF "-") +add_library(GENERIC_L412RBIXP INTERFACE) +target_compile_options(GENERIC_L412RBIXP INTERFACE + "SHELL:-DSTM32L412xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L412RBIXP_MCU} +) +target_compile_definitions(GENERIC_L412RBIXP INTERFACE + "STM32L4xx" + "ARDUINO_GENERIC_L412RBIXP" + "BOARD_NAME=\"GENERIC_L412RBIXP\"" + "BOARD_ID=GENERIC_L412RBIXP" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_L412RBIXP INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ + ${GENERIC_L412RBIXP_VARIANT_PATH} +) + +target_link_options(GENERIC_L412RBIXP INTERFACE + "LINKER:--default-script=${GENERIC_L412RBIXP_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L412RBIXP_MCU} +) + +add_library(GENERIC_L412RBIXP_serial_disabled INTERFACE) +target_compile_options(GENERIC_L412RBIXP_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_L412RBIXP_serial_generic INTERFACE) +target_compile_options(GENERIC_L412RBIXP_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_L412RBIXP_serial_none INTERFACE) +target_compile_options(GENERIC_L412RBIXP_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_L412RBIXP_usb_CDC INTERFACE) +target_compile_options(GENERIC_L412RBIXP_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_L412RBIXP_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_L412RBIXP_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_L412RBIXP_usb_HID INTERFACE) +target_compile_options(GENERIC_L412RBIXP_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_L412RBIXP_usb_none INTERFACE) +target_compile_options(GENERIC_L412RBIXP_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_L412RBIXP_xusb_FS INTERFACE) +target_compile_options(GENERIC_L412RBIXP_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_L412RBIXP_xusb_HS INTERFACE) +target_compile_options(GENERIC_L412RBIXP_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_L412RBIXP_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_L412RBIXP_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_L412RBTXP +# ----------------------------------------------------------------------------- + +set(GENERIC_L412RBTXP_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP") +set(GENERIC_L412RBTXP_MAXSIZE 131072) +set(GENERIC_L412RBTXP_MAXDATASIZE 40960) +set(GENERIC_L412RBTXP_MCU cortex-m4) +set(GENERIC_L412RBTXP_FPCONF "-") +add_library(GENERIC_L412RBTXP INTERFACE) +target_compile_options(GENERIC_L412RBTXP INTERFACE + "SHELL:-DSTM32L412xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L412RBTXP_MCU} +) +target_compile_definitions(GENERIC_L412RBTXP INTERFACE + "STM32L4xx" + "ARDUINO_GENERIC_L412RBTXP" + "BOARD_NAME=\"GENERIC_L412RBTXP\"" + "BOARD_ID=GENERIC_L412RBTXP" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_L412RBTXP INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ + ${GENERIC_L412RBTXP_VARIANT_PATH} +) + +target_link_options(GENERIC_L412RBTXP INTERFACE + "LINKER:--default-script=${GENERIC_L412RBTXP_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L412RBTXP_MCU} +) + +add_library(GENERIC_L412RBTXP_serial_disabled INTERFACE) +target_compile_options(GENERIC_L412RBTXP_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_L412RBTXP_serial_generic INTERFACE) +target_compile_options(GENERIC_L412RBTXP_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_L412RBTXP_serial_none INTERFACE) +target_compile_options(GENERIC_L412RBTXP_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_L412RBTXP_usb_CDC INTERFACE) +target_compile_options(GENERIC_L412RBTXP_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_L412RBTXP_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_L412RBTXP_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_L412RBTXP_usb_HID INTERFACE) +target_compile_options(GENERIC_L412RBTXP_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_L412RBTXP_usb_none INTERFACE) +target_compile_options(GENERIC_L412RBTXP_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_L412RBTXP_xusb_FS INTERFACE) +target_compile_options(GENERIC_L412RBTXP_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_L412RBTXP_xusb_HS INTERFACE) +target_compile_options(GENERIC_L412RBTXP_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_L412RBTXP_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_L412RBTXP_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_L422KBTX # ----------------------------------------------------------------------------- @@ -100108,6 +100272,170 @@ target_compile_options(GENERIC_L4S9ZIYX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_L552QCIXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_L552QCIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ") +set(GENERIC_L552QCIXQ_MAXSIZE 262144) +set(GENERIC_L552QCIXQ_MAXDATASIZE 262144) +set(GENERIC_L552QCIXQ_MCU cortex-m33) +set(GENERIC_L552QCIXQ_FPCONF "-") +add_library(GENERIC_L552QCIXQ INTERFACE) +target_compile_options(GENERIC_L552QCIXQ INTERFACE + "SHELL:-DSTM32L552xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L552QCIXQ_MCU} +) +target_compile_definitions(GENERIC_L552QCIXQ INTERFACE + "STM32L5xx" + "ARDUINO_GENERIC_L552QCIXQ" + "BOARD_NAME=\"GENERIC_L552QCIXQ\"" + "BOARD_ID=GENERIC_L552QCIXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_L552QCIXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ + ${GENERIC_L552QCIXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_L552QCIXQ INTERFACE + "LINKER:--default-script=${GENERIC_L552QCIXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=262144" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L552QCIXQ_MCU} +) + +add_library(GENERIC_L552QCIXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_L552QCIXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_L552QCIXQ_serial_none INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_L552QCIXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_L552QCIXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_L552QCIXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_L552QCIXQ_usb_none INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_L552QCIXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_L552QCIXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_L552QCIXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_L552QCIXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_L552QEIXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_L552QEIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ") +set(GENERIC_L552QEIXQ_MAXSIZE 524288) +set(GENERIC_L552QEIXQ_MAXDATASIZE 262144) +set(GENERIC_L552QEIXQ_MCU cortex-m33) +set(GENERIC_L552QEIXQ_FPCONF "-") +add_library(GENERIC_L552QEIXQ INTERFACE) +target_compile_options(GENERIC_L552QEIXQ INTERFACE + "SHELL:-DSTM32L552xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L552QEIXQ_MCU} +) +target_compile_definitions(GENERIC_L552QEIXQ INTERFACE + "STM32L5xx" + "ARDUINO_GENERIC_L552QEIXQ" + "BOARD_NAME=\"GENERIC_L552QEIXQ\"" + "BOARD_ID=GENERIC_L552QEIXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_L552QEIXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ + ${GENERIC_L552QEIXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_L552QEIXQ INTERFACE + "LINKER:--default-script=${GENERIC_L552QEIXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=262144" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L552QEIXQ_MCU} +) + +add_library(GENERIC_L552QEIXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_L552QEIXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_L552QEIXQ_serial_none INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_L552QEIXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_L552QEIXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_L552QEIXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_L552QEIXQ_usb_none INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_L552QEIXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_L552QEIXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_L552QEIXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_L552QEIXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_L552ZCTXQ # ----------------------------------------------------------------------------- @@ -100272,6 +100600,88 @@ target_compile_options(GENERIC_L552ZETXQ_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_L562QEIXQ +# ----------------------------------------------------------------------------- + +set(GENERIC_L562QEIXQ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ") +set(GENERIC_L562QEIXQ_MAXSIZE 524288) +set(GENERIC_L562QEIXQ_MAXDATASIZE 196608) +set(GENERIC_L562QEIXQ_MCU cortex-m33) +set(GENERIC_L562QEIXQ_FPCONF "-") +add_library(GENERIC_L562QEIXQ INTERFACE) +target_compile_options(GENERIC_L562QEIXQ INTERFACE + "SHELL:-DSTM32L562xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L562QEIXQ_MCU} +) +target_compile_definitions(GENERIC_L562QEIXQ INTERFACE + "STM32L5xx" + "ARDUINO_GENERIC_L562QEIXQ" + "BOARD_NAME=\"GENERIC_L562QEIXQ\"" + "BOARD_ID=GENERIC_L562QEIXQ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_L562QEIXQ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ + ${GENERIC_L562QEIXQ_VARIANT_PATH} +) + +target_link_options(GENERIC_L562QEIXQ INTERFACE + "LINKER:--default-script=${GENERIC_L562QEIXQ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_L562QEIXQ_MCU} +) + +add_library(GENERIC_L562QEIXQ_serial_disabled INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_L562QEIXQ_serial_generic INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_L562QEIXQ_serial_none INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_L562QEIXQ_usb_CDC INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_L562QEIXQ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_L562QEIXQ_usb_HID INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_L562QEIXQ_usb_none INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_L562QEIXQ_xusb_FS INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_L562QEIXQ_xusb_HS INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_L562QEIXQ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_L562QEIXQ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_L562ZETXQ # ----------------------------------------------------------------------------- @@ -106718,6 +107128,88 @@ target_compile_options(NUCLEO_F401RE_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_F410RB +# ----------------------------------------------------------------------------- + +set(NUCLEO_F410RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32F4xx/F410R(8-B)(I-T)") +set(NUCLEO_F410RB_MAXSIZE 131072) +set(NUCLEO_F410RB_MAXDATASIZE 32768) +set(NUCLEO_F410RB_MCU cortex-m4) +set(NUCLEO_F410RB_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_F410RB INTERFACE) +target_compile_options(NUCLEO_F410RB INTERFACE + "SHELL:-DSTM32F410Rx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_F410RB_MCU} +) +target_compile_definitions(NUCLEO_F410RB INTERFACE + "STM32F4xx" + "ARDUINO_NUCLEO_F410RB" + "BOARD_NAME=\"NUCLEO_F410RB\"" + "BOARD_ID=NUCLEO_F410RB" + "VARIANT_H=\"variant_NUCLEO_F410RB.h\"" +) +target_include_directories(NUCLEO_F410RB INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32F4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32F4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc/ + ${NUCLEO_F410RB_VARIANT_PATH} +) + +target_link_options(NUCLEO_F410RB INTERFACE + "LINKER:--default-script=${NUCLEO_F410RB_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_F410RB_MCU} +) + +add_library(NUCLEO_F410RB_serial_disabled INTERFACE) +target_compile_options(NUCLEO_F410RB_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_F410RB_serial_generic INTERFACE) +target_compile_options(NUCLEO_F410RB_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_F410RB_serial_none INTERFACE) +target_compile_options(NUCLEO_F410RB_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_F410RB_usb_CDC INTERFACE) +target_compile_options(NUCLEO_F410RB_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_F410RB_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_F410RB_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_F410RB_usb_HID INTERFACE) +target_compile_options(NUCLEO_F410RB_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_F410RB_usb_none INTERFACE) +target_compile_options(NUCLEO_F410RB_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_F410RB_xusb_FS INTERFACE) +target_compile_options(NUCLEO_F410RB_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_F410RB_xusb_HS INTERFACE) +target_compile_options(NUCLEO_F410RB_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_F410RB_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_F410RB_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_F411RE # ----------------------------------------------------------------------------- @@ -109260,6 +109752,88 @@ target_compile_options(NUCLEO_L412KB_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_L412RB_P +# ----------------------------------------------------------------------------- + +set(NUCLEO_L412RB_P_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L4xx/L412RB(I-T)xP") +set(NUCLEO_L412RB_P_MAXSIZE 131072) +set(NUCLEO_L412RB_P_MAXDATASIZE 40960) +set(NUCLEO_L412RB_P_MCU cortex-m4) +set(NUCLEO_L412RB_P_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_L412RB_P INTERFACE) +target_compile_options(NUCLEO_L412RB_P INTERFACE + "SHELL:-DSTM32L412xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_L412RB_P_MCU} +) +target_compile_definitions(NUCLEO_L412RB_P INTERFACE + "STM32L4xx" + "ARDUINO_NUCLEO_L412RB_P" + "BOARD_NAME=\"NUCLEO_L412RB_P\"" + "BOARD_ID=NUCLEO_L412RB_P" + "VARIANT_H=\"variant_NUCLEO_L412RB_P.h\"" +) +target_include_directories(NUCLEO_L412RB_P INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/ + ${NUCLEO_L412RB_P_VARIANT_PATH} +) + +target_link_options(NUCLEO_L412RB_P INTERFACE + "LINKER:--default-script=${NUCLEO_L412RB_P_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_L412RB_P_MCU} +) + +add_library(NUCLEO_L412RB_P_serial_disabled INTERFACE) +target_compile_options(NUCLEO_L412RB_P_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_L412RB_P_serial_generic INTERFACE) +target_compile_options(NUCLEO_L412RB_P_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_L412RB_P_serial_none INTERFACE) +target_compile_options(NUCLEO_L412RB_P_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_L412RB_P_usb_CDC INTERFACE) +target_compile_options(NUCLEO_L412RB_P_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_L412RB_P_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_L412RB_P_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_L412RB_P_usb_HID INTERFACE) +target_compile_options(NUCLEO_L412RB_P_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_L412RB_P_usb_none INTERFACE) +target_compile_options(NUCLEO_L412RB_P_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_L412RB_P_xusb_FS INTERFACE) +target_compile_options(NUCLEO_L412RB_P_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_L412RB_P_xusb_HS INTERFACE) +target_compile_options(NUCLEO_L412RB_P_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_L412RB_P_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_L412RB_P_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_L432KC # ----------------------------------------------------------------------------- @@ -112664,6 +113238,88 @@ target_compile_options(STM32H747I_DISCO_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# STM32L562E_DK +# ----------------------------------------------------------------------------- + +set(STM32L562E_DK_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ") +set(STM32L562E_DK_MAXSIZE 524288) +set(STM32L562E_DK_MAXDATASIZE 196608) +set(STM32L562E_DK_MCU cortex-m33) +set(STM32L562E_DK_FPCONF "fpv4-sp-d16-hard") +add_library(STM32L562E_DK INTERFACE) +target_compile_options(STM32L562E_DK INTERFACE + "SHELL:-DSTM32L562xx " + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${STM32L562E_DK_MCU} +) +target_compile_definitions(STM32L562E_DK INTERFACE + "STM32L5xx" + "ARDUINO_STM32L562E_DK" + "BOARD_NAME=\"STM32L562E_DK\"" + "BOARD_ID=STM32L562E_DK" + "VARIANT_H=\"variant_STM32L562E_DK.h\"" +) +target_include_directories(STM32L562E_DK INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32L5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32L5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/gcc/ + ${STM32L562E_DK_VARIANT_PATH} +) + +target_link_options(STM32L562E_DK INTERFACE + "LINKER:--default-script=${STM32L562E_DK_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${STM32L562E_DK_MCU} +) + +add_library(STM32L562E_DK_serial_disabled INTERFACE) +target_compile_options(STM32L562E_DK_serial_disabled INTERFACE + "SHELL:" +) +add_library(STM32L562E_DK_serial_generic INTERFACE) +target_compile_options(STM32L562E_DK_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(STM32L562E_DK_serial_none INTERFACE) +target_compile_options(STM32L562E_DK_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(STM32L562E_DK_usb_CDC INTERFACE) +target_compile_options(STM32L562E_DK_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(STM32L562E_DK_usb_CDCgen INTERFACE) +target_compile_options(STM32L562E_DK_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(STM32L562E_DK_usb_HID INTERFACE) +target_compile_options(STM32L562E_DK_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(STM32L562E_DK_usb_none INTERFACE) +target_compile_options(STM32L562E_DK_usb_none INTERFACE + "SHELL:" +) +add_library(STM32L562E_DK_xusb_FS INTERFACE) +target_compile_options(STM32L562E_DK_xusb_FS INTERFACE + "SHELL:" +) +add_library(STM32L562E_DK_xusb_HS INTERFACE) +target_compile_options(STM32L562E_DK_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(STM32L562E_DK_xusb_HSFS INTERFACE) +target_compile_options(STM32L562E_DK_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # STM32MP157A_DK1 # ----------------------------------------------------------------------------- diff --git a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt index 2a4d55b6b1..656acd547b 100644 --- a/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt +++ b/variants/STM32L5xx/L552Q(C-E)IxQ_L562QEIxQ/CMakeLists.txt @@ -21,7 +21,9 @@ target_link_libraries(variant INTERFACE variant_usage) add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c + PeripheralPins_STM32L562E_DK.c variant_generic.cpp + variant_STM32L562E_DK.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) From 9154e6e0d3b9cbe8692692380517616fda6c5320 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 25 Apr 2025 14:34:51 +0200 Subject: [PATCH 22/22] ci(build): update config Signed-off-by: Frederic Pillon --- CI/build/conf/cores_config.json | 3 +++ CI/build/conf/cores_config_ci.json | 3 +++ 2 files changed, 6 insertions(+) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index c47e35a460..7cdc1022ca 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -760,6 +760,7 @@ "GENERIC_L412K8UX", "GENERIC_L412KBTX", "GENERIC_L412KBUX", + "GENERIC_L412RBIXP", "GENERIC_L422KBTX", "GENERIC_L431CBTX", "GENERIC_L431CBUX", @@ -823,6 +824,8 @@ "GENERIC_L4S5VITX", "GENERIC_L4S5ZITX", "GENERIC_L4S5ZIYX", + "GENERIC_L552QCIXQ", + "GENERIC_L552QEIXQ", "GENERIC_L552ZCTXQ", "GENERIC_L552ZETXQ", "GENERIC_MP153AACX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index 8dff66d592..267c32f85c 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -760,6 +760,7 @@ "GENERIC_L412K8UX", "GENERIC_L412KBTX", "GENERIC_L412KBUX", + "GENERIC_L412RBIXP", "GENERIC_L422KBTX", "GENERIC_L431CBTX", "GENERIC_L431CBUX", @@ -823,6 +824,8 @@ "GENERIC_L4S5VITX", "GENERIC_L4S5ZITX", "GENERIC_L4S5ZIYX", + "GENERIC_L552QCIXQ", + "GENERIC_L552QEIXQ", "GENERIC_L552ZCTXQ", "GENERIC_L552ZETXQ", "GENERIC_MP153AACX",