diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index 85f34f3321..56e5df6cd2 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -3,7 +3,7 @@ Please, Make sure that your PR is not a duplicate. Search among the [Pull request](https://github.com/stm32duino/Arduino_Core_STM32/pulls) before creating one. -IMPORTANT: Please review the [CONTRIBUTING.md](../CONTRIBUTING.md) file for detailed contributing guidelines. +IMPORTANT: Please review the [CONTRIBUTING.md](https://github.com/stm32duino/Arduino_Core_STM32/blob/main/CONTRIBUTING.md) file for detailed contributing guidelines. Thanks for submitting a pull request. Please provide enough information so that others can review your pull request: diff --git a/.github/workflows/Cmake.yml b/.github/workflows/Cmake.yml index 4a5307a483..f39ac307f3 100644 --- a/.github/workflows/Cmake.yml +++ b/.github/workflows/Cmake.yml @@ -45,6 +45,7 @@ jobs: - NUCLEO_L152RE - NUCLEO_L476RG - NUCLEO_L552ZE_Q + - NUCLEO_U083RC - NUCLEO_U575ZI_Q - P_NUCLEO_WB55RG - NUCLEO_WBA55CG diff --git a/.github/workflows/MarkdwonLinksCheck.yml b/.github/workflows/MarkdwonLinksCheck.yml index c68646ef78..5525a3050d 100644 --- a/.github/workflows/MarkdwonLinksCheck.yml +++ b/.github/workflows/MarkdwonLinksCheck.yml @@ -20,4 +20,4 @@ jobs: with: paths: '*.md ./CI/**/*.md, ./variants/**/*.md, ./libraries/**/*.md' verbosity: 'INFO' - linksToSkip: 'www.st.com, de.elv.com/lorawan' + linksToSkip: 'www.st.com, blues.com' diff --git a/CI/build/arduino-cli.py b/CI/build/arduino-cli.py index 9af0f81838..08dbc8c0f9 100644 --- a/CI/build/arduino-cli.py +++ b/CI/build/arduino-cli.py @@ -74,12 +74,11 @@ sketch_options = {} # key: sketch pattern, value: options na_sketch_pattern = {} # key: board name, value: sketch pattern list -all_warnings = False - # Counter nb_build_passed = 0 nb_build_failed = 0 nb_build_skipped = 0 +nb_warnings = 0 # Timing full_buildTime = time.time() @@ -95,7 +94,7 @@ overflow_pattern = re.compile( r"(will not fit in |section .+ is not within )?region( .+ overflowed by [\d]+ bytes)?" ) - +warning_pattern = re.compile(r"warning: .+LOAD segment with RWX permissions") # format build_format_header = "| {:^8} | {:42} | {:^10} | {:^7} |" build_format_result = "| {:^8} | {:42} | {:^19} | {:^6.2f}s |" @@ -302,14 +301,14 @@ def check_config(): cli_config = cli_config["config"] # Since arduino-cli 1.x config init does not create full config if "directories" in cli_config.keys(): - if "data" in cli_config["directories"].key(): + if "data" in cli_config["directories"].keys(): if cli_config["directories"]["data"] is not None: sketches_path_list.append( Path(cli_config["directories"]["data"]) ) else: print("No data directory") - if "user" in cli_config["directories"].key(): + if "user" in cli_config["directories"].keys(): if cli_config["directories"]["user"] is not None: sketches_path_list.append( Path(cli_config["directories"]["user"]) @@ -441,10 +440,10 @@ def manage_inos(): ino_file = Path(args.ino) if ino_file.exists(): # Store only the path - if ino_file.is_file(args.ino): + if ino_file.is_file(): sketch_list.append(ino_file.parent) else: - sketch_list.append(args.ino) + sketch_list.append(ino_file) else: for path in sketches_path_list: fp = path / ino_file @@ -590,11 +589,18 @@ def find_board(): def check_status(status, build_conf, boardKo, nb_build_conf): global nb_build_passed global nb_build_failed + global nb_warnings sketch_name = build_conf[idx_cmd][-1].name if status[1] == 0: result = fsucc nb_build_passed += 1 + # Check warnings + logFile = build_conf[idx_log] / f"{sketch_name}.log" + for i, line in enumerate(open(logFile)): + if warning_pattern.search(line): + nb_warnings += 1 + print(f"Warning: {line}") elif status[1] == 1: # Check if failed due to a region overflowed logFile = build_conf[idx_log] / f"{sketch_name}.log" @@ -608,7 +614,11 @@ def check_status(status, build_conf, boardKo, nb_build_conf): elif ld_pattern.search(line): # If one ld line is not for region overflowed --> failed if overflow_pattern.search(line) is None: - error_found = True + if warning_pattern.search(line): + nb_warnings += 1 + print(f"Warning: {line}") + else: + error_found = True else: overflow_found = True if error_found: @@ -675,8 +685,12 @@ def log_sketch_build_result(sketch, boardKo, boardSkipped): def log_final_result(): # Also equal to len(board_fqbn) * len(sketch_list) nb_build_total = nb_build_passed + nb_build_failed - stat_passed = round(nb_build_passed * 100.0 / nb_build_total, 2) - stat_failed = round(nb_build_failed * 100.0 / nb_build_total, 2) + if nb_build_total != 0: + stat_passed = round(nb_build_passed * 100.0 / nb_build_total, 2) + stat_failed = round(nb_build_failed * 100.0 / nb_build_total, 2) + else: + stat_passed = 0 + stat_failed = 0 duration = str(timedelta(seconds=time.time() - full_buildTime)) # Log file @@ -688,6 +702,8 @@ def log_final_result(): sfail = f"{nb_build_failed} failed ({stat_failed}%)" sskip = f"{nb_build_skipped} skipped)" f.write(f"{ssucc}, {sfail} of {nb_build_total} builds ({sskip})\n") + if nb_warnings: + f.write(f"Total warning to remove: {nb_warnings}\n") f.write(f"Ends {time.strftime('%A %d %B %Y %H:%M:%S')}\n") f.write(f"Duration: {duration}\n") f.write(f"Logs are available here:\n{output_dir}\n") @@ -698,6 +714,8 @@ def log_final_result(): sfail = f"{nb_build_failed} {ffail} ({stat_failed}%)" sskip = f"{nb_build_skipped} {fskip}" print(f"Builds Summary: {ssucc}, {sfail} of {nb_build_total} builds ({sskip})") + if nb_warnings: + print(f"Total warning to remove: {nb_warnings}") print(f"Duration: {duration}") print("Logs are available here:") print(output_dir) diff --git a/CI/build/conf/cores_config.json b/CI/build/conf/cores_config.json index 9a0f081e29..baf56c80e4 100644 --- a/CI/build/conf/cores_config.json +++ b/CI/build/conf/cores_config.json @@ -49,6 +49,7 @@ "GENERIC_C031C4UX", "GENERIC_C031C6TX", "GENERIC_C031F4PX", + "GENERIC_C071R8TX", "GENERIC_F031C4TX", "GENERIC_F031E6YX", "GENERIC_F031F4PX", @@ -459,6 +460,7 @@ "GENERIC_G431R8TX", "GENERIC_G431RBIX", "GENERIC_G431RBTX", + "GENERIC_G431RBTXZ", "GENERIC_G431V6TX", "GENERIC_G431V8TX", "GENERIC_G431VBTX", @@ -485,9 +487,11 @@ "GENERIC_G473QBTX", "GENERIC_G473QCTX", "GENERIC_G473QETX", + "GENERIC_G473QETXZ", "GENERIC_G473RBTX", "GENERIC_G473RCTX", "GENERIC_G473RETX", + "GENERIC_G473RETXZ", "GENERIC_G473VBHX", "GENERIC_G473VBTX", "GENERIC_G473VCHX", @@ -535,12 +539,15 @@ "GENERIC_G491RCTX", "GENERIC_G491REIX", "GENERIC_G491RETX", + "GENERIC_G491RETXZ", "GENERIC_G491REYX", "GENERIC_G491VCTX", "GENERIC_G491VETX", "GENERIC_G4A1MESX", "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", + "GENERIC_H503CBTX", + "GENERIC_H562RGTX", "GENERIC_H563IIKXQ", "GENERIC_H563RGTX", "GENERIC_H563RITX", @@ -808,6 +815,13 @@ "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U073R8IX", + "GENERIC_U073R8TX", + "GENERIC_U073RBIX", + "GENERIC_U073RBTX", + "GENERIC_U073RCIX", + "GENERIC_U073RCTX", + "GENERIC_U083RCIX", "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", "GENERIC_U575CGTX", diff --git a/CI/build/conf/cores_config_ci.json b/CI/build/conf/cores_config_ci.json index a0299ed2a6..c8f42cb299 100644 --- a/CI/build/conf/cores_config_ci.json +++ b/CI/build/conf/cores_config_ci.json @@ -49,6 +49,7 @@ "GENERIC_C031C4UX", "GENERIC_C031C6TX", "GENERIC_C031F4PX", + "GENERIC_C071R8TX", "GENERIC_F031C4TX", "GENERIC_F031E6YX", "GENERIC_F031F4PX", @@ -459,6 +460,7 @@ "GENERIC_G431R8TX", "GENERIC_G431RBIX", "GENERIC_G431RBTX", + "GENERIC_G431RBTXZ", "GENERIC_G431V6TX", "GENERIC_G431V8TX", "GENERIC_G431VBTX", @@ -485,9 +487,11 @@ "GENERIC_G473QBTX", "GENERIC_G473QCTX", "GENERIC_G473QETX", + "GENERIC_G473QETXZ", "GENERIC_G473RBTX", "GENERIC_G473RCTX", "GENERIC_G473RETX", + "GENERIC_G473RETXZ", "GENERIC_G473VBHX", "GENERIC_G473VBTX", "GENERIC_G473VCHX", @@ -535,12 +539,15 @@ "GENERIC_G491RCTX", "GENERIC_G491REIX", "GENERIC_G491RETX", + "GENERIC_G491RETXZ", "GENERIC_G491REYX", "GENERIC_G491VCTX", "GENERIC_G491VETX", "GENERIC_G4A1MESX", "GENERIC_G4A1REIX", "GENERIC_G4A1RETX", + "GENERIC_H503CBTX", + "GENERIC_H562RGTX", "GENERIC_H563IIKXQ", "GENERIC_H563RGTX", "GENERIC_H563RITX", @@ -808,6 +815,13 @@ "GENERIC_MP157AACX", "GENERIC_MP157CACX", "GENERIC_MP157DACX", + "GENERIC_U073R8IX", + "GENERIC_U073R8TX", + "GENERIC_U073RBIX", + "GENERIC_U073RBTX", + "GENERIC_U073RCIX", + "GENERIC_U073RCTX", + "GENERIC_U083RCIX", "GENERIC_U575AGIXQ", "GENERIC_U575AIIXQ", "GENERIC_U575CGTX", diff --git a/CI/update/stm32cube.py b/CI/update/stm32cube.py index 5a98d6a038..a1ad9666db 100644 --- a/CI/update/stm32cube.py +++ b/CI/update/stm32cube.py @@ -115,6 +115,7 @@ def checkConfig(): / repo_core_name / "libraries" / "SrcWrapper" + / "inc" / stm32_def ) except IOError: diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 4a19cea1cc..5d53d01164 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -2519,7 +2519,6 @@ def manage_repo(): "STM32H7S", "STM32MP13", "STM32MP2", - "STM32U0", "STM32WB0", ] periph_c_filename = "PeripheralPins.c" diff --git a/License.md b/License.md index 16854d69c8..2f1fc5aaef 100644 --- a/License.md +++ b/License.md @@ -1,35 +1,36 @@ This files includes licensing information for parts of this repository. -Note: most license information is available on top of each source file - or on bottom of Release_Notes.html if available. +> [!NOTE] +> Most license information is available on top of each source file or on bottom of Release_Notes.html if available. [LGPLv2.1](#lgplv21) is used for: -* cores/arduino/*.* mainly contains modified files from Arduino. +* `cores/arduino/*.*` mainly contains modified files from Arduino. [BSD 3-Clause License](#bsd-3-clause-license) is used for: -* system/Drivers/STM32*xx_HAL_Driver folders include the STMicroelectronics HAL Drivers -* system/Middlewares/OpenAMP -* libraries/VirtIO - except virtio implementation (see [MIT License](#mit-license)) -* libraries/SrcWrapper/inc/PinName*.h +* `system/Drivers/STM32*xx_HAL_Driver` folders include the STMicroelectronics HAL Drivers +* `system/Middlewares/OpenAMP` +* `libraries/VirtIO` - except virtio implementation (see [MIT License](#mit-license)) +* `libraries/SrcWrapper/inc/PinName*.h` [Ultimate Liberty License](#Ultimate-Liberty-License) is used for: -* system/Middlewares/STM32_USB_*_Library folders -* libraries/USBDevice (see header) +* `system/Middlewares/STM32_USB_*_Library` folders +* `libraries/USBDevice` (see header) [Apache License](#apache-license) is used for: -* system/Drivers/CMSIS folder includes the STMicroelectronics CMSIS device -* system/include/include/pinmap.h -* libraries/SrcWrapper/src/stm32/pinmap.c -* tools/platformio/platformio-build.py +* `system/Drivers/CMSIS` folder includes the STMicroelectronics CMSIS device +* `system/include/include/pinmap.h` +* `libraries/SrcWrapper/src/stm32/pinmap.c` +* `tools/platformio/platformio-build.py` [MIT License](#mit-license) -* libraries/VirtIO/*/virtio* +* `libraries/VirtIO/*/virtio*` + +> [!NOTE] +> `system/STM32*xx/system_stm32*xx.c` uses same license than `system/Drivers/CMSIS` +> `system/STM32*xx/stm32*xx_hal_conf_default.h` uses same license than `system/Drivers` subfolders -Note: -* system/STM32*xx/system_stm32*xx.c uses same license than system/Drivers/ subfolders -* system/STM32*xx/stm32*xx_hal_conf_default.h uses same license than system/Drivers/CMSIS ------------------------------------------------------------------------------- ## LGPLv2.1 GNU LESSER GENERAL PUBLIC LICENSE diff --git a/README.md b/README.md index 02807e6529..dbf9d0ed10 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ [![GitHub release](https://img.shields.io/github/release/stm32duino/Arduino_Core_STM32.svg)](https://github.com/stm32duino/Arduino_Core_STM32/releases/latest) ![GitHub All Releases](https://img.shields.io/github/downloads/stm32duino/Arduino_Core_STM32/total.svg?label=downloads%20since%201.4.0) -[![GitHub commits since latest release](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/latest/main)](https://github.com/stm32duino/Arduino_Core_STM32/compare/2.8.1...main) +[![GitHub commits since latest release](https://img.shields.io/github/commits-since/stm32duino/Arduino_Core_STM32/latest/main)](https://github.com/stm32duino/Arduino_Core_STM32/compare/2.9.0...main) * [Introduction](https://github.com/stm32duino/Arduino_Core_STM32#Introduction)
@@ -28,7 +28,9 @@ This porting is based on: * The Low-Layer (LL) APIs, a light-weight, optimized, expert oriented set of APIs designed for both performance and runtime efficiency * CMSIS device definition for STM32 * [CMSIS](https://developer.arm.com/embedded/cmsis): Cortex Microcontroller Software Interface Standard (CMSIS) is a vendor-independent hardware abstraction layer for the Cortex®-M processor series and defines generic tool interfaces. It has been packaged as a module for Arduino IDE: https://github.com/stm32duino/ArduinoModule-CMSIS -* [GNU Arm Embedded Toolchain](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm): Arm Embedded GCC compiler, libraries and other GNU tools necessary for bare-metal software development on devices based on the Arm Cortex-M. Packages are provided thanks [The xPack GNU Arm Embedded GCC](https://xpack.github.io/arm-none-eabi-gcc/): https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack +* [GNU Arm Embedded Toolchain](https://developer.arm.com/open-source/gnu-toolchain/gnu-rm): Arm Embedded GCC compiler, libraries and other GNU tools necessary for bare-metal software development on devices based on the Arm Cortex-M. Packages are provided thanks [The xPack 3rd Party Development Tools](https://github.com/xpack-dev-tools/): + * https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack + * https://github.com/xpack-dev-tools/openocd-xpack ## Getting Started @@ -70,6 +72,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d - [Generic STM32L1 boards](#generic-stm32l1-boards) - [Generic STM32L4 boards](#generic-stm32l4-boards) - [Generic STM32L5 boards](#generic-stm32l5-boards) + - [Generic STM32U0 boards](#generic-stm32u0-boards) - [Generic STM32U5 boards](#generic-stm32u5-boards) - [Generic STM32WB boards](#generic-stm32wb-boards) - [Generic STM32WBA boards](#generic-stm32wba-boards) @@ -85,6 +88,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d - [Midatronics boards](#midatronics-boards) - [SparkFun boards](#sparkfun-boards) - [ELV Boards](#elv-boards) + - [STeaMi board](#steami-board) > [!Note] > - :green_heart: board support is available since the specified release version. @@ -121,6 +125,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32C031C6 | [Nucleo C031C6](https://www.st.com/en/evaluation-tools/nucleo-c031c6.html) | *2.5.0* | | +| :green_heart: | STM32C071RB | [Nucleo C071RB](https://www.st.com/en/evaluation-tools/nucleo-c071rb.html) | *2.9.0* | | | :green_heart: | STM32F030R8 | [Nucleo F030R8](http://www.st.com/en/evaluation-tools/nucleo-f030r8.html) | *0.2.0* | | | :green_heart: | STM32F070RB | [Nucleo F070RB](http://www.st.com/en/evaluation-tools/nucleo-f070rb.html) | *2.0.0* | | | :green_heart: | STM32F072RB | [Nucleo F072RB](http://www.st.com/en/evaluation-tools/nucleo-f072rb.html) | *1.9.0* | | @@ -145,6 +150,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32L452RE | [Nucleo L452RE](http://www.st.com/en/evaluation-tools/nucleo-l452re.html) | *1.5.0* | | | :green_heart: | STM32L452RE-P | [Nucleo L452RE-P](http://www.st.com/en/evaluation-tools/nucleo-l452re-p.html) | *1.8.0* | | | :green_heart: | STM32L476RG | [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) | *0.1.0* | | +| :green_heart: | STM32U083RC | [Nucleo U083RC](http://www.st.com/en/evaluation-tools/nucleo-u083rc.html) | *2.9.0* | | | :green_heart: | STM32WB15CCU | [Nucleo-WB15CC](https://www.st.com/en/evaluation-tools/nucleo-wb15cc.html) | *2.5.0* | | | :green_heart: | STM32WBA55CGU | Nucleo-WBA55CG | *2.8.0* | | | :green_heart: | STM32WB55RG | [P-Nucleo-WB55RG](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) | *1.6.0* | BLE support with [STM32duinoBLE](https://github.com/stm32duino/STM32duinoBLE) | @@ -209,6 +215,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32C011J4
STM32C011J6 | Generic Board | *2.8.0* | | | :green_heart: | STM32C031C4
STM32C031C6 | Generic Board | *2.5.0* | | | :green_heart: | STM32C031F4
STM32C031F6 | Generic Board | *2.6.0* | | +| :green_heart: | STM32C071R8
STM32C071RB | Generic Board | *2.9.0* | | ### Generic STM32F0 boards @@ -287,7 +294,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F103T4
STM32F103T6
STM32F103T8
STM32F103TB | Generic Board | *1.9.0* | | | :green_heart: | STM32F103V8
STM32F103VB
STM32F103VC
STM32F103VD
STM32F103VE
STM32F103VF
STM32F103VG | Generic Board | *1.9.0* | | | :green_heart: | STM32F103ZC
STM32F103ZD
STM32F103ZE
STM32F103ZF
STM32F103ZG | Generic Board | *1.9.0* | | -| :green_heart: | STM32F103TB | HY-TinySTM103T | *1.5.0* | [More info](https://www.hotmcu.com/stm32f103tb-arm-cortex-m3-development-board-p-222.html) | +| :green_heart: | STM32F103TB | HY-TinySTM103T | *1.5.0* | | | :green_heart: | STM32F103CB | Maple Mini | *1.2.0* | [More info](https://www.leaflabs.com/maple)
USB CDC support since *1.5.0*
Maple bootloaders support since *1.6.0* | | :green_heart: | STM32F103ZE | [vcc-gnd.com](https://stm32-base.org/boards/STM32F103ZET6-VCC-GND-XLarge) | *1.9.0* | | | :green_heart: | STM32F103ZE | vcc-gnd.com Mini | *1.9.0* | | @@ -541,8 +548,11 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | +| :green_heart: | STM32H503CB | Generic Board | *2.9.0* | | | :green_heart: | STM32H503KB | Generic Board | *2.8.1* | | | :green_heart: | STM32H503RB | Generic Board | *2.7.0* | | +| :green_heart: | STM32H562RGT | WeAct H562RGT | *2.9.0* | | +| :green_heart: | STM32H562RGT
STM32H562RIT | Generic Board | *2.9.0* | | | :green_heart: | STM32H563IIKxQ | Generic Board | *2.6.0* | | | :green_heart: | STM32H563RG
STM32H563RI | Generic Board | *2.8.1* | | | :green_heart: | STM32H563ZG
STM32H563ZI | Generic Board | *2.6.0* | | @@ -722,6 +732,13 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32L552ZC-Q
STM32L552ZE-Q | Generic Board | *2.0.0* | | | :green_heart: | STM32L562ZE-Q | Generic Board | *2.0.0* | | +### Generic STM32U0 boards + +| Status | Device(s) | Name | Release | Notes | +| :----: | :-------: | ---- | :-----: | :---- | +| :green_heart: | STM32U073R8
STSTM32U073RB
STM32U073RC | Generic Board | *2.9.0* | | +| :green_heart: | STM32U083RC | Generic Board | *2.9.0* | | + ### Generic STM32U5 boards | Status | Device(s) | Name | Release | Notes | @@ -774,7 +791,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F765VI | [RemRam v1](https://github.com/hasenbanck/remram) | *1.4.0* | | | :green_heart: | STM32F446VE | [RUMBA32](https://github.com/Aus3D/RUMBA32) | *1.5.0* | | | :green_heart: | STM32F401VE | [STEVAL-3DP001V1](https://www.st.com/en/evaluation-tools/steval-3dp001v1.html) | *1.6.0* | | -| :green_heart: | STM32F446RE | [VAkE v1.0](https://www.facebook.com/pages/category/Product-Service/VAkE-Board-2290066274575218/) | *1.6.0* | | +| :green_heart: | STM32F446RE | VAkE v1.0 | *1.6.0* | | | :green_heart: | STM32F446VE | [FYSETC_S6](https://wiki.fysetc.com/FYSETC_S6/) | *1.9.0* | | | :green_heart: | STM32G0B1CB | [BTT EBB42 CAN V1.1](https://github.com/bigtreetech/EBB/tree/master) | *2.4.0* | | @@ -845,12 +862,17 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F405RG | [SparkFun MicroMod Processor Board - STM32F405](https://www.sparkfun.com/products/21326) | *2.6.0* | | | :green_heart: | STM32WB5MMG | [SparkFun MicroMod Processor Board - STM32WB5MMG](https://www.sparkfun.com/products/21438) | *2.6.0* | | -### [ELV Boards](https://de.elv.com/lorawan) +### [ELV Boards](https://de.elv.com/) | Status | Device(s) | Name | Release | Notes | | :----: | :-------: | ---- | :-----: | :---- | | :green_heart: | STM32WLE5JB | ELV-BM-TRX1 | *2.8.0* | | +### [STeaMi Board](https://www.steami.cc/) + +| Status | Device(s) | Name | Release | Notes | +| :----: | :-------: | ---- | :-----: | :---- | +| :green_heart: | STM32WB55RGV | [STeaMi](https://www.steami.cc/) | *2.9.0* | | ## Next release See [milestones](https://github.com/stm32duino/Arduino_Core_STM32/milestones) to have an overview of the next release content. diff --git a/boards.txt b/boards.txt index 60cc71bb1a..ece804f324 100644 --- a/boards.txt +++ b/boards.txt @@ -52,7 +52,7 @@ Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.series=STM32F2xx Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.product_line=STM32F207xx Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.variant=STM32F2xx/F207Z(C-E-F-G)T_F217Z(E-G)T Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Nucleo_144.menu.pnum.NUCLEO_F207ZG.debug.server.openocd.scripts.2=target/stm32f2x.cfg +Nucleo_144.menu.pnum.NUCLEO_F207ZG.openocd.target=stm32f2x Nucleo_144.menu.pnum.NUCLEO_F207ZG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F2xx/STM32F217.svd # NUCLEO_F412ZG board @@ -67,7 +67,7 @@ Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.board=NUCLEO_F412ZG Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.series=STM32F4xx Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.product_line=STM32F412Zx Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.variant=STM32F4xx/F412Z(E-G)(J-T) -Nucleo_144.menu.pnum.NUCLEO_F412ZG.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_144.menu.pnum.NUCLEO_F412ZG.openocd.target=stm32f4x Nucleo_144.menu.pnum.NUCLEO_F412ZG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F412.svd # NUCLEO_F413ZH board @@ -82,7 +82,7 @@ Nucleo_144.menu.pnum.NUCLEO_F413ZH.build.board=NUCLEO_F413ZH Nucleo_144.menu.pnum.NUCLEO_F413ZH.build.series=STM32F4xx Nucleo_144.menu.pnum.NUCLEO_F413ZH.build.product_line=STM32F413xx Nucleo_144.menu.pnum.NUCLEO_F413ZH.build.variant=STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T) -Nucleo_144.menu.pnum.NUCLEO_F413ZH.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_144.menu.pnum.NUCLEO_F413ZH.openocd.target=stm32f4x Nucleo_144.menu.pnum.NUCLEO_F413ZH.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F413.svd # NUCLEO_F429ZI board @@ -99,7 +99,8 @@ Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.series=STM32F4xx Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.product_line=STM32F429xx Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.variant=STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y) Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.variant_h=variant_NUCLEO_F4x9ZI.h -Nucleo_144.menu.pnum.NUCLEO_F429ZI.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_144.menu.pnum.NUCLEO_F429ZI.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +Nucleo_144.menu.pnum.NUCLEO_F429ZI.openocd.target=stm32f4x Nucleo_144.menu.pnum.NUCLEO_F429ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F429.svd # NUCLEO_F439ZI board @@ -115,7 +116,8 @@ Nucleo_144.menu.pnum.NUCLEO_F439ZI.build.series=STM32F4xx Nucleo_144.menu.pnum.NUCLEO_F439ZI.build.product_line=STM32F439xx Nucleo_144.menu.pnum.NUCLEO_F439ZI.build.variant=STM32F4xx/F427Z(G-I)T_F429ZET_F429Z(G-I)(T-Y)_F437Z(G-I)T_F439Z(G-I)(T-Y) Nucleo_144.menu.pnum.NUCLEO_F439ZI.build.variant_h=variant_NUCLEO_F4x9ZI.h -Nucleo_144.menu.pnum.NUCLEO_F439ZI.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_144.menu.pnum.NUCLEO_F439ZI.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +Nucleo_144.menu.pnum.NUCLEO_F439ZI.openocd.target=stm32f4x Nucleo_144.menu.pnum.NUCLEO_F439ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F439.svd # NUCLEO_F446RE board @@ -130,7 +132,7 @@ Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.board=NUCLEO_F446ZE Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.series=STM32F4xx Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.product_line=STM32F446xx Nucleo_144.menu.pnum.NUCLEO_F446ZE.build.variant=STM32F4xx/F446Z(C-E)(H-J-T) -Nucleo_144.menu.pnum.NUCLEO_F446ZE.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_144.menu.pnum.NUCLEO_F446ZE.openocd.target=stm32f4x Nucleo_144.menu.pnum.NUCLEO_F446ZE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F446.svd # NUCLEO_F722ZE board @@ -145,7 +147,7 @@ Nucleo_144.menu.pnum.NUCLEO_F722ZE.build.series=STM32F7xx Nucleo_144.menu.pnum.NUCLEO_F722ZE.build.product_line=STM32F722xx Nucleo_144.menu.pnum.NUCLEO_F722ZE.build.variant=STM32F7xx/F722Z(C-E)T_F732ZET Nucleo_144.menu.pnum.NUCLEO_F722ZE.build.variant_h=variant_NUCLEO_F722ZE.h -Nucleo_144.menu.pnum.NUCLEO_F722ZE.debug.server.openocd.scripts.2=target/stm32f7x.cfg +Nucleo_144.menu.pnum.NUCLEO_F722ZE.openocd.target=stm32f7x Nucleo_144.menu.pnum.NUCLEO_F722ZE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F722.svd # NUCLEO_F746ZG board @@ -161,7 +163,7 @@ Nucleo_144.menu.pnum.NUCLEO_F746ZG.build.series=STM32F7xx Nucleo_144.menu.pnum.NUCLEO_F746ZG.build.product_line=STM32F746xx Nucleo_144.menu.pnum.NUCLEO_F746ZG.build.variant=STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y) Nucleo_144.menu.pnum.NUCLEO_F746ZG.build.variant_h=variant_NUCLEO_F7x6ZG.h -Nucleo_144.menu.pnum.NUCLEO_F746ZG.debug.server.openocd.scripts.2=target/stm32f7x.cfg +Nucleo_144.menu.pnum.NUCLEO_F746ZG.openocd.target=stm32f7x Nucleo_144.menu.pnum.NUCLEO_F746ZG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F746.svd # NUCLEO_F756ZG board @@ -177,7 +179,7 @@ Nucleo_144.menu.pnum.NUCLEO_F756ZG.build.series=STM32F7xx Nucleo_144.menu.pnum.NUCLEO_F756ZG.build.product_line=STM32F756xx Nucleo_144.menu.pnum.NUCLEO_F756ZG.build.variant=STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y) Nucleo_144.menu.pnum.NUCLEO_F756ZG.build.variant_h=variant_NUCLEO_F7x6ZG.h -Nucleo_144.menu.pnum.NUCLEO_F756ZG.debug.server.openocd.scripts.2=target/stm32f7x.cfg +Nucleo_144.menu.pnum.NUCLEO_F756ZG.openocd.target=stm32f7x Nucleo_144.menu.pnum.NUCLEO_F756ZG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F756.svd # NUCLEO_F767ZI board @@ -192,7 +194,7 @@ Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.board=NUCLEO_F767ZI Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.series=STM32F7xx Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.product_line=STM32F767xx Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.variant=STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT -Nucleo_144.menu.pnum.NUCLEO_F767ZI.debug.server.openocd.scripts.2=target/stm32f7x.cfg +Nucleo_144.menu.pnum.NUCLEO_F767ZI.openocd.target=stm32f7x Nucleo_144.menu.pnum.NUCLEO_F767ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F767.svd # NUCLEO H563ZI @@ -207,7 +209,7 @@ Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.board=NUCLEO_H563ZI Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.series=STM32H5xx Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.product_line=STM32H563xx Nucleo_144.menu.pnum.NUCLEO_H563ZI.build.variant=STM32H5xx/H563Z(G-I)T_H573ZIT -Nucleo_144.menu.pnum.NUCLEO_H563ZI.debug.server.openocd.scripts.2=target/stm32h5x.cfg +Nucleo_144.menu.pnum.NUCLEO_H563ZI.openocd.target=stm32h5x Nucleo_144.menu.pnum.NUCLEO_H563ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H563.svd # NUCLEO H723ZG board @@ -222,7 +224,7 @@ Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.board=NUCLEO_H723ZG Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.series=STM32H7xx Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.product_line=STM32H723xx Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.variant=STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT -Nucleo_144.menu.pnum.NUCLEO_H723ZG.debug.server.openocd.scripts.2=target/stm32h7x.cfg +Nucleo_144.menu.pnum.NUCLEO_H723ZG.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H723ZG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H723.svd # NUCLEO_H743ZI board @@ -237,7 +239,7 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.board=NUCLEO_H743ZI Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.series=STM32H7xx Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.product_line=STM32H743xx Nucleo_144.menu.pnum.NUCLEO_H743ZI.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT -Nucleo_144.menu.pnum.NUCLEO_H743ZI.debug.server.openocd.scripts.2=target/stm32h7x.cfg +Nucleo_144.menu.pnum.NUCLEO_H743ZI.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H743ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd Nucleo_144.menu.pnum.NUCLEO_H743ZI2=Nucleo H743ZI2 @@ -252,7 +254,7 @@ Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.series=STM32H7xx Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.product_line=STM32H743xx Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT Nucleo_144.menu.pnum.NUCLEO_H743ZI2.build.variant_h=variant_NUCLEO_H743ZI.h -Nucleo_144.menu.pnum.NUCLEO_H743ZI2.debug.server.openocd.scripts.2=target/stm32h7x.cfg +Nucleo_144.menu.pnum.NUCLEO_H743ZI2.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H743ZI2.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H743.svd # NUCLEO_H753ZI board @@ -268,7 +270,7 @@ Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.series=STM32H7xx Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.product_line=STM32H753xx Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant=STM32H7xx/H742Z(G-I)T_H743Z(G-I)T_H747A(G-I)I_H747I(G-I)T_H750ZBT_H753ZIT_H757AII_H757IIT Nucleo_144.menu.pnum.NUCLEO_H753ZI.build.variant_h=variant_NUCLEO_H753ZI.h -Nucleo_144.menu.pnum.NUCLEO_H753ZI.debug.server.openocd.scripts.2=target/stm32h7x.cfg +Nucleo_144.menu.pnum.NUCLEO_H753ZI.openocd.target=stm32h7x Nucleo_144.menu.pnum.NUCLEO_H753ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H753.svd # NUCLEO_L496ZG board @@ -283,7 +285,7 @@ Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.board=NUCLEO_L496ZG Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.series=STM32L4xx Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.product_line=STM32L496xx Nucleo_144.menu.pnum.NUCLEO_L496ZG.build.variant=STM32L4xx/L496Z(E-G)T_L4A6ZGT -Nucleo_144.menu.pnum.NUCLEO_L496ZG.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_144.menu.pnum.NUCLEO_L496ZG.openocd.target=stm32l4x Nucleo_144.menu.pnum.NUCLEO_L496ZG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L496.svd # NUCLEO_L496ZG-P board @@ -298,7 +300,7 @@ Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.board=NUCLEO_L496ZG_P Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.series=STM32L4xx Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.product_line=STM32L496xx Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.build.variant=STM32L4xx/L496ZGTxP_L4A6ZGTxP -Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.openocd.target=stm32l4x Nucleo_144.menu.pnum.NUCLEO_L496ZG-P.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L496.svd # NUCLEO_L4R5ZI board @@ -313,7 +315,7 @@ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.board=NUCLEO_L4R5ZI Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.series=STM32L4xx Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.product_line=STM32L4R5xx Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.build.variant=STM32L4xx/L4R5Z(G-I)T_L4R7ZIT_L4S5ZIT_L4S7ZIT -Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.openocd.target=stm32l4x Nucleo_144.menu.pnum.NUCLEO_L4R5ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4R5.svd # NUCLEO_L4R5ZI-P board @@ -328,7 +330,7 @@ Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.build.board=NUCLEO_L4R5ZI_P Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.build.series=STM32L4xx Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.build.product_line=STM32L4R5xx Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.build.variant=STM32L4xx/L4R5ZITxP -Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.openocd.target=stm32l4x Nucleo_144.menu.pnum.NUCLEO_L4R5ZI_P.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4R5.svd # NUCLEO_L552ZE-Q board @@ -343,7 +345,7 @@ Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.board=NUCLEO_L552ZE_Q Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.series=STM32L5xx Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.product_line=STM32L552xx Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.build.variant=STM32L5xx/L552Z(C-E)TxQ_L562ZETxQ -Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.debug.server.openocd.scripts.2=target/stm32l5x.cfg +Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.openocd.target=stm32l5x Nucleo_144.menu.pnum.NUCLEO_L552ZE_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L5xx/STM32L552.svd # NUCLEO_U575ZI_Q board @@ -359,7 +361,7 @@ Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.series=STM32U5xx Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.product_line=STM32U575xx Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.variant=STM32U5xx/U575Z(G-I)TxQ_U585ZITxQ Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.debug.server.openocd.scripts.2=target/stm32u5x.cfg +Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.openocd.target=stm32u5x Nucleo_144.menu.pnum.NUCLEO_U575ZI_Q.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U575.svd # Upload menu @@ -372,6 +374,11 @@ Nucleo_144.menu.upload_method.swdMethod.upload.protocol=swd Nucleo_144.menu.upload_method.swdMethod.upload.options= Nucleo_144.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Nucleo_144.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Nucleo_144.menu.upload_method.jlinkMethod.upload.protocol=jlink +Nucleo_144.menu.upload_method.jlinkMethod.upload.options= +Nucleo_144.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Nucleo_144.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Nucleo_144.menu.upload_method.serialMethod.upload.protocol=serial Nucleo_144.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -382,6 +389,14 @@ Nucleo_144.menu.upload_method.dfuMethod.upload.protocol=dfu Nucleo_144.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Nucleo_144.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Nucleo_144.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Nucleo_144.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Nucleo_144.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Nucleo_144.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Nucleo_144.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Nucleo_144.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Nucleo 64 boards @@ -423,9 +438,23 @@ Nucleo_64.menu.pnum.NUCLEO_C031C6.build.series=STM32C0xx Nucleo_64.menu.pnum.NUCLEO_C031C6.build.product_line=STM32C031xx Nucleo_64.menu.pnum.NUCLEO_C031C6.build.variant=STM32C0xx/C031C(4-6)(T-U) Nucleo_64.menu.pnum.NUCLEO_C031C6.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_C031C6.debug.server.openocd.scripts.2=target/stm32c0x.cfg +Nucleo_64.menu.pnum.NUCLEO_C031C6.openocd.target=stm32c0x Nucleo_64.menu.pnum.NUCLEO_C031C6.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd +# NUCLEO_C071RB board +Nucleo_64.menu.pnum.NUCLEO_C071RB=Nucleo C071RB +Nucleo_64.menu.pnum.NUCLEO_C071RB.node="NOD_C071RB" +Nucleo_64.menu.pnum.NUCLEO_C071RB.upload.maximum_size=131072 +Nucleo_64.menu.pnum.NUCLEO_C071RB.upload.maximum_data_size=24576 +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.mcu=cortex-m0plus +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.board=NUCLEO_C071RB +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.series=STM32C0xx +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.product_line=STM32C071xx +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.variant=STM32C0xx/C071R(8-B)T +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +Nucleo_64.menu.pnum.NUCLEO_C071RB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 +Nucleo_64.menu.pnum.NUCLEO_C071RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd + # NUCLEO_F030R8 board Nucleo_64.menu.pnum.NUCLEO_F030R8=Nucleo F030R8 Nucleo_64.menu.pnum.NUCLEO_F030R8.node="NODE_F030R8,NUCLEO" @@ -436,7 +465,7 @@ Nucleo_64.menu.pnum.NUCLEO_F030R8.build.board=NUCLEO_F030R8 Nucleo_64.menu.pnum.NUCLEO_F030R8.build.series=STM32F0xx Nucleo_64.menu.pnum.NUCLEO_F030R8.build.product_line=STM32F030x8 Nucleo_64.menu.pnum.NUCLEO_F030R8.build.variant=STM32F0xx/F030R8T -Nucleo_64.menu.pnum.NUCLEO_F030R8.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Nucleo_64.menu.pnum.NUCLEO_F030R8.openocd.target=stm32f0x Nucleo_64.menu.pnum.NUCLEO_F030R8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x0.svd # NUCLEO_F070RB board @@ -449,7 +478,7 @@ Nucleo_64.menu.pnum.NUCLEO_F070RB.build.board=NUCLEO_F070RB Nucleo_64.menu.pnum.NUCLEO_F070RB.build.series=STM32F0xx Nucleo_64.menu.pnum.NUCLEO_F070RB.build.product_line=STM32F070xB Nucleo_64.menu.pnum.NUCLEO_F070RB.build.variant=STM32F0xx/F070RBT -Nucleo_64.menu.pnum.NUCLEO_F070RB.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Nucleo_64.menu.pnum.NUCLEO_F070RB.openocd.target=stm32f0x Nucleo_64.menu.pnum.NUCLEO_F070RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x0.svd # NUCLEO_F072RB board @@ -462,7 +491,7 @@ Nucleo_64.menu.pnum.NUCLEO_F072RB.build.board=NUCLEO_F072RB Nucleo_64.menu.pnum.NUCLEO_F072RB.build.series=STM32F0xx Nucleo_64.menu.pnum.NUCLEO_F072RB.build.product_line=STM32F072xB Nucleo_64.menu.pnum.NUCLEO_F072RB.build.variant=STM32F0xx/F072R8T_F072RB(H-I-T) -Nucleo_64.menu.pnum.NUCLEO_F072RB.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Nucleo_64.menu.pnum.NUCLEO_F072RB.openocd.target=stm32f0x Nucleo_64.menu.pnum.NUCLEO_F072RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd # NUCLEO_F091RC board @@ -475,7 +504,7 @@ Nucleo_64.menu.pnum.NUCLEO_F091RC.build.board=NUCLEO_F091RC Nucleo_64.menu.pnum.NUCLEO_F091RC.build.series=STM32F0xx Nucleo_64.menu.pnum.NUCLEO_F091RC.build.product_line=STM32F091xC Nucleo_64.menu.pnum.NUCLEO_F091RC.build.variant=STM32F0xx/F091RBT_F091RC(H-T-Y) -Nucleo_64.menu.pnum.NUCLEO_F091RC.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Nucleo_64.menu.pnum.NUCLEO_F091RC.openocd.target=stm32f0x Nucleo_64.menu.pnum.NUCLEO_F091RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x1.svd # NUCLEO_F103RB board @@ -488,7 +517,7 @@ Nucleo_64.menu.pnum.NUCLEO_F103RB.build.board=NUCLEO_F103RB Nucleo_64.menu.pnum.NUCLEO_F103RB.build.series=STM32F1xx Nucleo_64.menu.pnum.NUCLEO_F103RB.build.product_line=STM32F103xB Nucleo_64.menu.pnum.NUCLEO_F103RB.build.variant=STM32F1xx/F103R(8-B)T -Nucleo_64.menu.pnum.NUCLEO_F103RB.debug.server.openocd.scripts.2=target/stm32f1x.cfg +Nucleo_64.menu.pnum.NUCLEO_F103RB.openocd.target=stm32f1x Nucleo_64.menu.pnum.NUCLEO_F103RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd # NUCLEO_F302R8 board @@ -503,7 +532,7 @@ Nucleo_64.menu.pnum.NUCLEO_F302R8.build.board=NUCLEO_F302R8 Nucleo_64.menu.pnum.NUCLEO_F302R8.build.series=STM32F3xx Nucleo_64.menu.pnum.NUCLEO_F302R8.build.product_line=STM32F302x8 Nucleo_64.menu.pnum.NUCLEO_F302R8.build.variant=STM32F3xx/F302R(6-8)T -Nucleo_64.menu.pnum.NUCLEO_F302R8.debug.server.openocd.scripts.2=target/stm32f3x.cfg +Nucleo_64.menu.pnum.NUCLEO_F302R8.openocd.target=stm32f3x Nucleo_64.menu.pnum.NUCLEO_F302R8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F302.svd # NUCLEO_F303RE board @@ -518,7 +547,7 @@ Nucleo_64.menu.pnum.NUCLEO_F303RE.build.board=NUCLEO_F303RE Nucleo_64.menu.pnum.NUCLEO_F303RE.build.series=STM32F3xx Nucleo_64.menu.pnum.NUCLEO_F303RE.build.product_line=STM32F303xE Nucleo_64.menu.pnum.NUCLEO_F303RE.build.variant=STM32F3xx/F303R(D-E)T -Nucleo_64.menu.pnum.NUCLEO_F303RE.debug.server.openocd.scripts.2=target/stm32f3x.cfg +Nucleo_64.menu.pnum.NUCLEO_F303RE.openocd.target=stm32f3x Nucleo_64.menu.pnum.NUCLEO_F303RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F303.svd # NUCLEO_F401RE board @@ -533,7 +562,7 @@ Nucleo_64.menu.pnum.NUCLEO_F401RE.build.board=NUCLEO_F401RE Nucleo_64.menu.pnum.NUCLEO_F401RE.build.series=STM32F4xx Nucleo_64.menu.pnum.NUCLEO_F401RE.build.product_line=STM32F401xE Nucleo_64.menu.pnum.NUCLEO_F401RE.build.variant=STM32F4xx/F401R(B-C-D-E)T -Nucleo_64.menu.pnum.NUCLEO_F401RE.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_64.menu.pnum.NUCLEO_F401RE.openocd.target=stm32f4x Nucleo_64.menu.pnum.NUCLEO_F401RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F401.svd # NUCLEO_F411RE board @@ -548,7 +577,7 @@ Nucleo_64.menu.pnum.NUCLEO_F411RE.build.board=NUCLEO_F411RE Nucleo_64.menu.pnum.NUCLEO_F411RE.build.series=STM32F4xx Nucleo_64.menu.pnum.NUCLEO_F411RE.build.product_line=STM32F411xE Nucleo_64.menu.pnum.NUCLEO_F411RE.build.variant=STM32F4xx/F411R(C-E)T -Nucleo_64.menu.pnum.NUCLEO_F411RE.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_64.menu.pnum.NUCLEO_F411RE.openocd.target=stm32f4x Nucleo_64.menu.pnum.NUCLEO_F411RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd # NUCLEO_F446RE board @@ -563,7 +592,7 @@ Nucleo_64.menu.pnum.NUCLEO_F446RE.build.board=NUCLEO_F446RE Nucleo_64.menu.pnum.NUCLEO_F446RE.build.series=STM32F4xx Nucleo_64.menu.pnum.NUCLEO_F446RE.build.product_line=STM32F446xx Nucleo_64.menu.pnum.NUCLEO_F446RE.build.variant=STM32F4xx/F446R(C-E)T -Nucleo_64.menu.pnum.NUCLEO_F446RE.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Nucleo_64.menu.pnum.NUCLEO_F446RE.openocd.target=stm32f4x Nucleo_64.menu.pnum.NUCLEO_F446RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F446.svd # NUCLEO_G070RB board @@ -577,7 +606,7 @@ Nucleo_64.menu.pnum.NUCLEO_G070RB.build.series=STM32G0xx Nucleo_64.menu.pnum.NUCLEO_G070RB.build.product_line=STM32G070xx Nucleo_64.menu.pnum.NUCLEO_G070RB.build.variant=STM32G0xx/G070RBT Nucleo_64.menu.pnum.NUCLEO_G070RB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_G070RB.debug.server.openocd.scripts.2=target/stm32g0x.cfg +Nucleo_64.menu.pnum.NUCLEO_G070RB.openocd.target=stm32g0x Nucleo_64.menu.pnum.NUCLEO_G070RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G0xx/STM32G070.svd # NUCLEO_G071RB board @@ -591,7 +620,7 @@ Nucleo_64.menu.pnum.NUCLEO_G071RB.build.series=STM32G0xx Nucleo_64.menu.pnum.NUCLEO_G071RB.build.product_line=STM32G071xx Nucleo_64.menu.pnum.NUCLEO_G071RB.build.variant=STM32G0xx/G071R(6-8)T_G071RB(I-T)_G081RB(I-T) Nucleo_64.menu.pnum.NUCLEO_G071RB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_G071RB.debug.server.openocd.scripts.2=target/stm32g0x.cfg +Nucleo_64.menu.pnum.NUCLEO_G071RB.openocd.target=stm32g0x Nucleo_64.menu.pnum.NUCLEO_G071RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G0xx/STM32G071.svd # NUCLEO_G0B1RE board @@ -605,7 +634,7 @@ Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.series=STM32G0xx Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.product_line=STM32G0B1xx Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.variant=STM32G0xx/G0B1R(B-C-E)T_G0C1R(C-E)T Nucleo_64.menu.pnum.NUCLEO_G0B1RE.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_G0B1RE.debug.server.openocd.scripts.2=target/stm32g0x.cfg +Nucleo_64.menu.pnum.NUCLEO_G0B1RE.openocd.target=stm32g0x Nucleo_64.menu.pnum.NUCLEO_G0B1RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G0xx/STM32G0B1.svd # NUCLEO_G431RB board @@ -619,8 +648,8 @@ Nucleo_64.menu.pnum.NUCLEO_G431RB.build.float-abi=-mfloat-abi=hard Nucleo_64.menu.pnum.NUCLEO_G431RB.build.board=NUCLEO_G431RB Nucleo_64.menu.pnum.NUCLEO_G431RB.build.series=STM32G4xx Nucleo_64.menu.pnum.NUCLEO_G431RB.build.product_line=STM32G431xx -Nucleo_64.menu.pnum.NUCLEO_G431RB.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) -Nucleo_64.menu.pnum.NUCLEO_G431RB.debug.server.openocd.scripts.2=target/stm32g4x.cfg +Nucleo_64.menu.pnum.NUCLEO_G431RB.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) +Nucleo_64.menu.pnum.NUCLEO_G431RB.openocd.target=stm32g4x Nucleo_64.menu.pnum.NUCLEO_G431RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # NUCLEO_G474RE board @@ -634,8 +663,8 @@ Nucleo_64.menu.pnum.NUCLEO_G474RE.build.float-abi=-mfloat-abi=hard Nucleo_64.menu.pnum.NUCLEO_G474RE.build.board=NUCLEO_G474RE Nucleo_64.menu.pnum.NUCLEO_G474RE.build.series=STM32G4xx Nucleo_64.menu.pnum.NUCLEO_G474RE.build.product_line=STM32G474xx -Nucleo_64.menu.pnum.NUCLEO_G474RE.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET -Nucleo_64.menu.pnum.NUCLEO_G474RE.debug.server.openocd.scripts.2=target/stm32g4x.cfg +Nucleo_64.menu.pnum.NUCLEO_G474RE.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET +Nucleo_64.menu.pnum.NUCLEO_G474RE.openocd.target=stm32g4x Nucleo_64.menu.pnum.NUCLEO_G474RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd # NUCLEO H503RB @@ -650,7 +679,7 @@ Nucleo_64.menu.pnum.NUCLEO_H503RB.build.board=NUCLEO_H503RB Nucleo_64.menu.pnum.NUCLEO_H503RB.build.series=STM32H5xx Nucleo_64.menu.pnum.NUCLEO_H503RB.build.product_line=STM32H503xx Nucleo_64.menu.pnum.NUCLEO_H503RB.build.variant=STM32H5xx/H503RBT -Nucleo_64.menu.pnum.NUCLEO_H503RB.debug.server.openocd.scripts.2=target/stm32h5x.cfg +Nucleo_64.menu.pnum.NUCLEO_H503RB.openocd.target=stm32h5x Nucleo_64.menu.pnum.NUCLEO_H503RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd # NUCLEO_L010RB board @@ -664,7 +693,7 @@ Nucleo_64.menu.pnum.NUCLEO_L010RB.build.series=STM32L0xx Nucleo_64.menu.pnum.NUCLEO_L010RB.build.product_line=STM32L010xB Nucleo_64.menu.pnum.NUCLEO_L010RB.build.variant=STM32L0xx/L010RBT Nucleo_64.menu.pnum.NUCLEO_L010RB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_L010RB.debug.server.openocd.scripts.2=target/stm32l0x.cfg +Nucleo_64.menu.pnum.NUCLEO_L010RB.openocd.target=stm32l0 Nucleo_64.menu.pnum.NUCLEO_L010RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L0x0.svd # NUCLEO_L053R8 board @@ -678,7 +707,7 @@ Nucleo_64.menu.pnum.NUCLEO_L053R8.build.series=STM32L0xx Nucleo_64.menu.pnum.NUCLEO_L053R8.build.product_line=STM32L053xx Nucleo_64.menu.pnum.NUCLEO_L053R8.build.variant=STM32L0xx/L052R(6-8)T_L053R(6-8)T_L063R8T Nucleo_64.menu.pnum.NUCLEO_L053R8.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_L053R8.debug.server.openocd.scripts.2=target/stm32l0x.cfg +Nucleo_64.menu.pnum.NUCLEO_L053R8.openocd.target=stm32l0 Nucleo_64.menu.pnum.NUCLEO_L053R8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L053.svd # NUCLEO_L073RZ board @@ -692,7 +721,7 @@ Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.series=STM32L0xx Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.product_line=STM32L073xx Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T Nucleo_64.menu.pnum.NUCLEO_L073RZ.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_64.menu.pnum.NUCLEO_L073RZ.debug.server.openocd.scripts.2=target/stm32l0x.cfg +Nucleo_64.menu.pnum.NUCLEO_L073RZ.openocd.target=stm32l0 Nucleo_64.menu.pnum.NUCLEO_L073RZ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L0x3.svd # NUCLEO_L152RE board @@ -705,7 +734,7 @@ Nucleo_64.menu.pnum.NUCLEO_L152RE.build.board=NUCLEO_L152RE Nucleo_64.menu.pnum.NUCLEO_L152RE.build.series=STM32L1xx Nucleo_64.menu.pnum.NUCLEO_L152RE.build.product_line=STM32L152xE Nucleo_64.menu.pnum.NUCLEO_L152RE.build.variant=STM32L1xx/L151RET_L152RET_L162RET -Nucleo_64.menu.pnum.NUCLEO_L152RE.debug.server.openocd.scripts.2=target/stm32l1x.cfg +Nucleo_64.menu.pnum.NUCLEO_L152RE.openocd.target=stm32l1 Nucleo_64.menu.pnum.NUCLEO_L152RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L152.svd # NUCLEO_L433RC_P board @@ -720,7 +749,7 @@ Nucleo_64.menu.pnum.NUCLEO_L433RC_P.build.board=NUCLEO_L433RC_P Nucleo_64.menu.pnum.NUCLEO_L433RC_P.build.series=STM32L4xx Nucleo_64.menu.pnum.NUCLEO_L433RC_P.build.product_line=STM32L433xx Nucleo_64.menu.pnum.NUCLEO_L433RC_P.build.variant=STM32L4xx/L433RCTxP -Nucleo_64.menu.pnum.NUCLEO_L433RC_P.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_64.menu.pnum.NUCLEO_L433RC_P.openocd.target=stm32l4x Nucleo_64.menu.pnum.NUCLEO_L433RC_P.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4x3.svd # NUCLEO_L452RE board @@ -735,7 +764,7 @@ Nucleo_64.menu.pnum.NUCLEO_L452RE.build.board=NUCLEO_L452RE Nucleo_64.menu.pnum.NUCLEO_L452RE.build.series=STM32L4xx Nucleo_64.menu.pnum.NUCLEO_L452RE.build.product_line=STM32L452xx Nucleo_64.menu.pnum.NUCLEO_L452RE.build.variant=STM32L4xx/L452RC(I-T-Y)_L452RE(I-T-Y)x(P)_L462RE(I-T-Y) -Nucleo_64.menu.pnum.NUCLEO_L452RE.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_64.menu.pnum.NUCLEO_L452RE.openocd.target=stm32l4x Nucleo_64.menu.pnum.NUCLEO_L452RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4x2.svd # NUCLEO_L452RE-P board @@ -750,7 +779,7 @@ Nucleo_64.menu.pnum.NUCLEO_L452REP.build.board=NUCLEO_L452RE_P Nucleo_64.menu.pnum.NUCLEO_L452REP.build.series=STM32L4xx Nucleo_64.menu.pnum.NUCLEO_L452REP.build.product_line=STM32L452xx Nucleo_64.menu.pnum.NUCLEO_L452REP.build.variant=STM32L4xx/L452RETxP -Nucleo_64.menu.pnum.NUCLEO_L452REP.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_64.menu.pnum.NUCLEO_L452REP.openocd.target=stm32l4x Nucleo_64.menu.pnum.NUCLEO_L452REP.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4x2.svd # NUCLEO_L476RG board @@ -765,9 +794,23 @@ Nucleo_64.menu.pnum.NUCLEO_L476RG.build.board=NUCLEO_L476RG Nucleo_64.menu.pnum.NUCLEO_L476RG.build.series=STM32L4xx Nucleo_64.menu.pnum.NUCLEO_L476RG.build.product_line=STM32L476xx Nucleo_64.menu.pnum.NUCLEO_L476RG.build.variant=STM32L4xx/L475R(C-E-G)T_L476R(C-E-G)T_L486RGT -Nucleo_64.menu.pnum.NUCLEO_L476RG.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_64.menu.pnum.NUCLEO_L476RG.openocd.target=stm32l4x Nucleo_64.menu.pnum.NUCLEO_L476RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L476.svd +# NUCLEO_U083RC board +Nucleo_64.menu.pnum.NUCLEO_U083RC=Nucleo U083RC +Nucleo_64.menu.pnum.NUCLEO_U083RC.node=NOD_U083RC +Nucleo_64.menu.pnum.NUCLEO_U083RC.upload.maximum_size=262144 +Nucleo_64.menu.pnum.NUCLEO_U083RC.upload.maximum_data_size=40960 +Nucleo_64.menu.pnum.NUCLEO_U083RC.build.mcu=cortex-m0plus +Nucleo_64.menu.pnum.NUCLEO_U083RC.build.board=NUCLEO_U083RC +Nucleo_64.menu.pnum.NUCLEO_U083RC.build.series=STM32U0xx +Nucleo_64.menu.pnum.NUCLEO_U083RC.build.product_line=STM32U083xx +Nucleo_64.menu.pnum.NUCLEO_U083RC.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +Nucleo_64.menu.pnum.NUCLEO_U083RC.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 +Nucleo_64.menu.pnum.NUCLEO_U083RC.openocd.target=stm32u0x +Nucleo_64.menu.pnum.NUCLEO_U083RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U083.svd + # NUCLEO_WB15CC Nucleo_64.menu.pnum.NUCLEO_WB15CC=Nucleo WB15CC Nucleo_64.menu.pnum.NUCLEO_WB15CC.node="NOD_WB15CC" @@ -780,7 +823,7 @@ Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.board=NUCLEO_WB15CC Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.series=STM32WBxx Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.product_line=STM32WB15xx Nucleo_64.menu.pnum.NUCLEO_WB15CC.build.variant=STM32WBxx/WB15CCU -Nucleo_64.menu.pnum.NUCLEO_WB15CC.debug.server.openocd.scripts.2=target/stm32wbx.cfg +Nucleo_64.menu.pnum.NUCLEO_WB15CC.openocd.target=stm32wbx Nucleo_64.menu.pnum.NUCLEO_WB15CC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB15_CM4.svd # P_NUCLEO_WB55RG board @@ -795,7 +838,7 @@ Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.build.board=P_NUCLEO_WB55RG Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.build.series=STM32WBxx Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.build.product_line=STM32WB55xx Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.build.variant=STM32WBxx/WB55R(C-E-G)V -Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.debug.server.openocd.scripts.2=target/stm32wbx.cfg +Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.openocd.target=stm32wbx Nucleo_64.menu.pnum.P_NUCLEO_WB55RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd # P_NUCLEO_WB55 USB Dongle @@ -810,7 +853,7 @@ Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.board=P_NUCLEO_WB55_USB_DONGL Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.series=STM32WBxx Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.product_line=STM32WB55xx Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.variant=STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U -Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.debug.server.openocd.scripts.2=target/stm32wbx.cfg +Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.openocd.target=stm32wbx Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd # NUCLEO WBA55CG @@ -825,7 +868,7 @@ Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.board=NUCLEO_WBA55CG Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.series=STM32WBAxx Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.product_line=STM32WBA55xx Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.variant=STM32WBAxx/WBA55C(E-G)U -Nucleo_64.menu.pnum.NUCLEO_WBA55CG.debug.server.openocd.scripts.2=target/stm32wbax.cfg +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.openocd.target=stm32wbax Nucleo_64.menu.pnum.NUCLEO_WBA55CG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBAxx/STM32WBA55.svd # NUCLEO_WL55JC1 board @@ -839,7 +882,7 @@ Nucleo_64.menu.pnum.NUCLEO_WL55JC1.build.series=STM32WLxx Nucleo_64.menu.pnum.NUCLEO_WL55JC1.build.product_line=STM32WLE5xx Nucleo_64.menu.pnum.NUCLEO_WL55JC1.build.variant=STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I Nucleo_64.menu.pnum.NUCLEO_WL55JC1.build.st_extra_flags=-D{build.product_line} -DUSE_CM4_STARTUP_FILE {build.xSerial} -Nucleo_64.menu.pnum.NUCLEO_WL55JC1.debug.server.openocd.scripts.2=target/stm32wlx.cfg +Nucleo_64.menu.pnum.NUCLEO_WL55JC1.openocd.target=stm32wlx Nucleo_64.menu.pnum.NUCLEO_WL55JC1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd # Upload menu @@ -852,6 +895,11 @@ Nucleo_64.menu.upload_method.swdMethod.upload.protocol=swd Nucleo_64.menu.upload_method.swdMethod.upload.options= Nucleo_64.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Nucleo_64.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Nucleo_64.menu.upload_method.jlinkMethod.upload.protocol=jlink +Nucleo_64.menu.upload_method.jlinkMethod.upload.options= +Nucleo_64.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Nucleo_64.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Nucleo_64.menu.upload_method.serialMethod.upload.protocol=serial Nucleo_64.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -862,6 +910,14 @@ Nucleo_64.menu.upload_method.dfuMethod.upload.protocol=dfu Nucleo_64.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Nucleo_64.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Nucleo_64.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Nucleo_64.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Nucleo_64.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Nucleo_64.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Nucleo_64.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Nucleo_64.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Nucleo 32 boards @@ -902,7 +958,7 @@ Nucleo_32.menu.pnum.NUCLEO_F031K6.build.board=NUCLEO_F031K6 Nucleo_32.menu.pnum.NUCLEO_F031K6.build.series=STM32F0xx Nucleo_32.menu.pnum.NUCLEO_F031K6.build.product_line=STM32F031x6 Nucleo_32.menu.pnum.NUCLEO_F031K6.build.variant=STM32F0xx/F031K6T -Nucleo_32.menu.pnum.NUCLEO_F031K6.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Nucleo_32.menu.pnum.NUCLEO_F031K6.openocd.target=stm32f0x Nucleo_32.menu.pnum.NUCLEO_F031K6.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x1.svd # NUCLEO_F042K6 board @@ -915,7 +971,7 @@ Nucleo_32.menu.pnum.NUCLEO_F042K6.build.board=NUCLEO_F042K6 Nucleo_32.menu.pnum.NUCLEO_F042K6.build.series=STM32F0xx Nucleo_32.menu.pnum.NUCLEO_F042K6.build.product_line=STM32F042x6 Nucleo_32.menu.pnum.NUCLEO_F042K6.build.variant=STM32F0xx/F042K(4-6)T -Nucleo_32.menu.pnum.NUCLEO_F042K6.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Nucleo_32.menu.pnum.NUCLEO_F042K6.openocd.target=stm32f0x Nucleo_32.menu.pnum.NUCLEO_F042K6.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd # NUCLEO_F303K8 board @@ -930,7 +986,7 @@ Nucleo_32.menu.pnum.NUCLEO_F303K8.build.board=NUCLEO_F303K8 Nucleo_32.menu.pnum.NUCLEO_F303K8.build.series=STM32F3xx Nucleo_32.menu.pnum.NUCLEO_F303K8.build.product_line=STM32F303x8 Nucleo_32.menu.pnum.NUCLEO_F303K8.build.variant=STM32F3xx/F303K(6-8)T_F334K(4-6-8)T -Nucleo_32.menu.pnum.NUCLEO_F303K8.debug.server.openocd.scripts.2=target/stm32f3x.cfg +Nucleo_32.menu.pnum.NUCLEO_F303K8.openocd.target=stm32f3x Nucleo_32.menu.pnum.NUCLEO_F303K8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F303.svd # NUCLEO_G031K8 board @@ -944,7 +1000,7 @@ Nucleo_32.menu.pnum.NUCLEO_G031K8.build.series=STM32G0xx Nucleo_32.menu.pnum.NUCLEO_G031K8.build.product_line=STM32G031xx Nucleo_32.menu.pnum.NUCLEO_G031K8.build.variant=STM32G0xx/G031K(4-6-8)(T-U)_G041K(6-8)(T-U) Nucleo_32.menu.pnum.NUCLEO_G031K8.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Nucleo_32.menu.pnum.NUCLEO_G031K8.debug.server.openocd.scripts.2=target/stm32g0x.cfg +Nucleo_32.menu.pnum.NUCLEO_G031K8.openocd.target=stm32g0x Nucleo_32.menu.pnum.NUCLEO_G031K8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G0xx/STM32G031.svd # NUCLEO_G431KB board @@ -959,7 +1015,7 @@ Nucleo_32.menu.pnum.NUCLEO_G431KB.build.board=NUCLEO_G431KB Nucleo_32.menu.pnum.NUCLEO_G431KB.build.series=STM32G4xx Nucleo_32.menu.pnum.NUCLEO_G431KB.build.product_line=STM32G431xx Nucleo_32.menu.pnum.NUCLEO_G431KB.build.variant=STM32G4xx/G431K(6-8-B)(T-U)_G441KB(T-U) -Nucleo_32.menu.pnum.NUCLEO_G431KB.debug.server.openocd.scripts.2=target/stm32g4x.cfg +Nucleo_32.menu.pnum.NUCLEO_G431KB.openocd.target=stm32g4x Nucleo_32.menu.pnum.NUCLEO_G431KB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # NUCLEO_L031K6 board @@ -972,7 +1028,7 @@ Nucleo_32.menu.pnum.NUCLEO_L031K6.build.board=NUCLEO_L031K6 Nucleo_32.menu.pnum.NUCLEO_L031K6.build.series=STM32L0xx Nucleo_32.menu.pnum.NUCLEO_L031K6.build.product_line=STM32L031xx Nucleo_32.menu.pnum.NUCLEO_L031K6.build.variant=STM32L0xx/L031K(4-6)T_L041K6T -Nucleo_32.menu.pnum.NUCLEO_L031K6.debug.server.openocd.scripts.2=target/stm32l0x.cfg +Nucleo_32.menu.pnum.NUCLEO_L031K6.openocd.target=stm32l0 Nucleo_32.menu.pnum.NUCLEO_L031K6.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L0x1.svd # NUCLEO_L412KB board @@ -987,7 +1043,7 @@ Nucleo_32.menu.pnum.NUCLEO_L412KB.build.board=NUCLEO_L412KB Nucleo_32.menu.pnum.NUCLEO_L412KB.build.series=STM32L4xx Nucleo_32.menu.pnum.NUCLEO_L412KB.build.product_line=STM32L412xx Nucleo_32.menu.pnum.NUCLEO_L412KB.build.variant=STM32L4xx/L412K(8-B)(T-U)_L422KB(T-U) -Nucleo_32.menu.pnum.NUCLEO_L412KB.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_32.menu.pnum.NUCLEO_L412KB.openocd.target=stm32l4x Nucleo_32.menu.pnum.NUCLEO_L412KB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L412.svd # NUCLEO_L432KC board @@ -1002,7 +1058,7 @@ Nucleo_32.menu.pnum.NUCLEO_L432KC.build.board=NUCLEO_L432KC Nucleo_32.menu.pnum.NUCLEO_L432KC.build.series=STM32L4xx Nucleo_32.menu.pnum.NUCLEO_L432KC.build.product_line=STM32L432xx Nucleo_32.menu.pnum.NUCLEO_L432KC.build.variant=STM32L4xx/L432K(B-C)U_L442KCU -Nucleo_32.menu.pnum.NUCLEO_L432KC.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Nucleo_32.menu.pnum.NUCLEO_L432KC.openocd.target=stm32l4x Nucleo_32.menu.pnum.NUCLEO_L432KC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4x2.svd # Upload menu @@ -1015,6 +1071,11 @@ Nucleo_32.menu.upload_method.swdMethod.upload.protocol=swd Nucleo_32.menu.upload_method.swdMethod.upload.options= Nucleo_32.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Nucleo_32.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Nucleo_32.menu.upload_method.jlinkMethod.upload.protocol=jlink +Nucleo_32.menu.upload_method.jlinkMethod.upload.options= +Nucleo_32.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Nucleo_32.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Nucleo_32.menu.upload_method.serialMethod.upload.protocol=serial Nucleo_32.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -1025,6 +1086,14 @@ Nucleo_32.menu.upload_method.dfuMethod.upload.protocol=dfu Nucleo_32.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Nucleo_32.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Nucleo_32.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Nucleo_32.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Nucleo_32.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Nucleo_32.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Nucleo_32.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Nucleo_32.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Discovery boards @@ -1068,7 +1137,7 @@ Disco.menu.pnum.B_G431B_ESC1.build.series=STM32G4xx Disco.menu.pnum.B_G431B_ESC1.build.product_line=STM32G431xx Disco.menu.pnum.B_G431B_ESC1.build.variant=STM32G4xx/G431C(6-8-B)U_G441CBU Disco.menu.pnum.B_G431B_ESC1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.B_G431B_ESC1.debug.server.openocd.scripts.2=target/stm32g4x.cfg +Disco.menu.pnum.B_G431B_ESC1.openocd.target=stm32g4x Disco.menu.pnum.B_G431B_ESC1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # B-L072Z-LRWAN1 board @@ -1083,7 +1152,7 @@ Disco.menu.pnum.B_L072Z_LRWAN1.build.product_line=STM32L072xx Disco.menu.pnum.B_L072Z_LRWAN1.build.variant=STM32L0xx/L072CBY_L072CZ(E-Y)_L073CZY_L082CZY Disco.menu.pnum.B_L072Z_LRWAN1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Disco.menu.pnum.B_L072Z_LRWAN1.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -Disco.menu.pnum.B_L072Z_LRWAN1.debug.server.openocd.scripts.2=target/stm32l0x.cfg +Disco.menu.pnum.B_L072Z_LRWAN1.openocd.target=stm32l0 Disco.menu.pnum.B_L072Z_LRWAN1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L0x2.svd # B-L475E-IOT01A board @@ -1099,7 +1168,7 @@ Disco.menu.pnum.B_L475E_IOT01A.build.series=STM32L4xx Disco.menu.pnum.B_L475E_IOT01A.build.product_line=STM32L475xx Disco.menu.pnum.B_L475E_IOT01A.build.variant=STM32L4xx/L475V(C-E-G)T_L476V(C-E-G)T_L486VGT Disco.menu.pnum.B_L475E_IOT01A.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.B_L475E_IOT01A.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Disco.menu.pnum.B_L475E_IOT01A.openocd.target=stm32l4x Disco.menu.pnum.B_L475E_IOT01A.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4x5.svd # B_L4S5I_IOT01A board @@ -1115,7 +1184,7 @@ Disco.menu.pnum.B_L4S5I_IOT01A.build.series=STM32L4xx Disco.menu.pnum.B_L4S5I_IOT01A.build.product_line=STM32L4S5xx Disco.menu.pnum.B_L4S5I_IOT01A.build.variant=STM32L4xx/L4R5V(G-I)T_L4R7VIT_L4S5VIT_L4S7VIT Disco.menu.pnum.B_L4S5I_IOT01A.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.B_L4S5I_IOT01A.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Disco.menu.pnum.B_L4S5I_IOT01A.openocd.target=stm32l4x Disco.menu.pnum.B_L4S5I_IOT01A.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4S5.svd # B_U585I_IOT02A board @@ -1131,7 +1200,7 @@ Disco.menu.pnum.B_U585I_IOT02A.build.series=STM32U5xx Disco.menu.pnum.B_U585I_IOT02A.build.product_line=STM32U585xx Disco.menu.pnum.B_U585I_IOT02A.build.variant=STM32U5xx/U575A(G-I)IxQ_U585AIIxQ Disco.menu.pnum.B_U585I_IOT02A.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.B_U585I_IOT02A.debug.server.openocd.scripts.2=target/stm32u5x.cfg +Disco.menu.pnum.B_U585I_IOT02A.openocd.target=stm32u5x Disco.menu.pnum.B_U585I_IOT02A.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U585.svd # STM32C0316-DK board @@ -1145,7 +1214,7 @@ Disco.menu.pnum.STM32C0116_DK.build.series=STM32C0xx Disco.menu.pnum.STM32C0116_DK.build.product_line=STM32C011xx Disco.menu.pnum.STM32C0116_DK.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P Disco.menu.pnum.STM32C0116_DK.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 -Disco.menu.pnum.STM32C0116_DK.debug.server.openocd.scripts.2=target/stm32c0x.cfg +Disco.menu.pnum.STM32C0116_DK.openocd.target=stm32c0x Disco.menu.pnum.STM32C0116_DK.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C011.svd # STM32C0316-DK board @@ -1159,7 +1228,7 @@ Disco.menu.pnum.STM32C0316_DK.build.series=STM32C0xx Disco.menu.pnum.STM32C0316_DK.build.product_line=STM32C031xx Disco.menu.pnum.STM32C0316_DK.build.variant=STM32C0xx/C031C(4-6)(T-U) Disco.menu.pnum.STM32C0316_DK.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 -Disco.menu.pnum.STM32C0316_DK.debug.server.openocd.scripts.2=target/stm32c0x.cfg +Disco.menu.pnum.STM32C0316_DK.openocd.target=stm32c0x Disco.menu.pnum.STM32C0316_DK.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd # DISCO_F030R8 board @@ -1172,7 +1241,7 @@ Disco.menu.pnum.DISCO_F030R8.build.board=DISCO_F030R8 Disco.menu.pnum.DISCO_F030R8.build.series=STM32F0xx Disco.menu.pnum.DISCO_F030R8.build.product_line=STM32F030x8 Disco.menu.pnum.DISCO_F030R8.build.variant=STM32F0xx/F030R8T -Disco.menu.pnum.DISCO_F030R8.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Disco.menu.pnum.DISCO_F030R8.openocd.target=stm32f0x Disco.menu.pnum.DISCO_F030R8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x0.svd # DISCO_F072RB board @@ -1185,7 +1254,7 @@ Disco.menu.pnum.DISCO_F072RB.build.board=DISCO_F072RB Disco.menu.pnum.DISCO_F072RB.build.series=STM32F0xx Disco.menu.pnum.DISCO_F072RB.build.product_line=STM32F072xB Disco.menu.pnum.DISCO_F072RB.build.variant=STM32F0xx/F072R8T_F072RB(H-I-T) -Disco.menu.pnum.DISCO_F072RB.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Disco.menu.pnum.DISCO_F072RB.openocd.target=stm32f0x Disco.menu.pnum.DISCO_F072RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd # DISCO_F100RB board @@ -1198,7 +1267,7 @@ Disco.menu.pnum.DISCO_F100RB.build.board=DISCO_F100RB Disco.menu.pnum.DISCO_F100RB.build.series=STM32F1xx Disco.menu.pnum.DISCO_F100RB.build.product_line=STM32F100xB Disco.menu.pnum.DISCO_F100RB.build.variant=STM32F1xx/F100R(8-B)T -Disco.menu.pnum.DISCO_F100RB.debug.server.openocd.scripts.2=target/stm32f1x.cfg +Disco.menu.pnum.DISCO_F100RB.openocd.target=stm32f1x Disco.menu.pnum.DISCO_F100RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F100.svd # DISCO_F303VC board @@ -1213,7 +1282,7 @@ Disco.menu.pnum.DISCO_F303VC.build.board=DISCO_F303VC Disco.menu.pnum.DISCO_F303VC.build.series=STM32F3xx Disco.menu.pnum.DISCO_F303VC.build.product_line=STM32F303xC Disco.menu.pnum.DISCO_F303VC.build.variant=STM32F3xx/F303V(B-C)T -Disco.menu.pnum.DISCO_F303VC.debug.server.openocd.scripts.2=target/stm32f3x.cfg +Disco.menu.pnum.DISCO_F303VC.openocd.target=stm32f3x Disco.menu.pnum.DISCO_F303VC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F303.svd # DISCO_F407VG board @@ -1228,7 +1297,7 @@ Disco.menu.pnum.DISCO_F407VG.build.board=DISCO_F407VG Disco.menu.pnum.DISCO_F407VG.build.series=STM32F4xx Disco.menu.pnum.DISCO_F407VG.build.product_line=STM32F407xx Disco.menu.pnum.DISCO_F407VG.build.variant=STM32F4xx/F407V(E-G)T_F417V(E-G)T -Disco.menu.pnum.DISCO_F407VG.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Disco.menu.pnum.DISCO_F407VG.openocd.target=stm32f4x Disco.menu.pnum.DISCO_F407VG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F407.svd # DISCO_F413ZH board @@ -1244,7 +1313,7 @@ Disco.menu.pnum.DISCO_F413ZH.build.series=STM32F4xx Disco.menu.pnum.DISCO_F413ZH.build.product_line=STM32F413xx Disco.menu.pnum.DISCO_F413ZH.build.variant=STM32F4xx/F413Z(G-H)(J-T)_F423ZH(J-T) Disco.menu.pnum.DISCO_F413ZH.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.DISCO_F413ZH.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Disco.menu.pnum.DISCO_F413ZH.openocd.target=stm32f4x Disco.menu.pnum.DISCO_F413ZH.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F413.svd # DISCO_F746NG board @@ -1260,7 +1329,7 @@ Disco.menu.pnum.DISCO_F746NG.build.series=STM32F7xx Disco.menu.pnum.DISCO_F746NG.build.product_line=STM32F746xx Disco.menu.pnum.DISCO_F746NG.build.variant=STM32F7xx/F746B(E-G)T_F746N(E-G)H_F750N8H_F756BGT_F756NGH Disco.menu.pnum.DISCO_F746NG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.DISCO_F746NG.debug.server.openocd.scripts.2=target/stm32f7x.cfg +Disco.menu.pnum.DISCO_F746NG.openocd.target=stm32f7x Disco.menu.pnum.DISCO_F746NG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F746.svd # DISCO_G0316 board @@ -1274,7 +1343,7 @@ Disco.menu.pnum.DISCO_G0316.build.series=STM32G0xx Disco.menu.pnum.DISCO_G0316.build.product_line=STM32G031xx Disco.menu.pnum.DISCO_G0316.build.variant=STM32G0xx/G031J(4-6)M_G041J6M Disco.menu.pnum.DISCO_G0316.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC=0 -Disco.menu.pnum.DISCO_G0316.debug.server.openocd.scripts.2=target/stm32g0x.cfg +Disco.menu.pnum.DISCO_G0316.openocd.target=stm32g0x Disco.menu.pnum.DISCO_G0316.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G0xx/STM32G031.svd # STM32H573I-DK @@ -1290,7 +1359,7 @@ Disco.menu.pnum.STM32H573I_DK.build.series=STM32H5xx Disco.menu.pnum.STM32H573I_DK.build.product_line=STM32H573xx Disco.menu.pnum.STM32H573I_DK.build.variant=STM32H5xx/H563IIKxQ_H573IIKxQ Disco.menu.pnum.STM32H573I_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.STM32H573I_DK.debug.server.openocd.scripts.2=target/stm32h5x.cfg +Disco.menu.pnum.STM32H573I_DK.openocd.target=stm32h5x Disco.menu.pnum.STM32H573I_DK.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H573.svd # STM32H747I-DISCO @@ -1307,7 +1376,7 @@ Disco.menu.pnum.STM32H747I_DISCO.build.product_line=STM32H747xx Disco.menu.pnum.STM32H747I_DISCO.build.variant=STM32H7xx/H742X(G-I)H_H743X(G-I)H_H745X(G-I)H_H747X(G-I)H_H750XBH_H753XIH_H755XIH_H757XIH Disco.menu.pnum.STM32H747I_DISCO.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -DCORE_CM7 Disco.menu.pnum.STM32H747I_DISCO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.STM32H747I_DISCO.debug.server.openocd.scripts.2=target/stm32h7x.cfg +Disco.menu.pnum.STM32H747I_DISCO.openocd.target=stm32h7x Disco.menu.pnum.STM32H747I_DISCO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H7xx/STM32H747_CM7.svd # STM32WB5MM-DK board @@ -1323,7 +1392,7 @@ Disco.menu.pnum.STM32WB5MM_DK.build.series=STM32WBxx Disco.menu.pnum.STM32WB5MM_DK.build.product_line=STM32WB5Mxx Disco.menu.pnum.STM32WB5MM_DK.build.variant=STM32WBxx/WB5MMGH Disco.menu.pnum.STM32WB5MM_DK.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Disco.menu.pnum.STM32WB5MM_DK.debug.server.openocd.scripts.2=target/stm32wbx.cfg +Disco.menu.pnum.STM32WB5MM_DK.openocd.target=stm32wbx Disco.menu.pnum.STM32WB5MM_DK.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd # Upload menu @@ -1336,6 +1405,11 @@ Disco.menu.upload_method.swdMethod.upload.protocol=swd Disco.menu.upload_method.swdMethod.upload.options= Disco.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Disco.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Disco.menu.upload_method.jlinkMethod.upload.protocol=jlink +Disco.menu.upload_method.jlinkMethod.upload.options= +Disco.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Disco.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Disco.menu.upload_method.serialMethod.upload.protocol=serial Disco.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -1346,6 +1420,14 @@ Disco.menu.upload_method.dfuMethod.upload.protocol=dfu Disco.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Disco.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Disco.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Disco.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Disco.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Disco.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Disco.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Disco.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Eval boards @@ -1388,7 +1470,7 @@ Eval.menu.pnum.STEVAL_MKSBOX1V1.build.series=STM32L4xx Eval.menu.pnum.STEVAL_MKSBOX1V1.build.product_line=STM32L4R9xx Eval.menu.pnum.STEVAL_MKSBOX1V1.build.variant=STM32L4xx/L4R9Z(G-I)J_L4S9ZIJ Eval.menu.pnum.STEVAL_MKSBOX1V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Eval.menu.pnum.STEVAL_MKSBOX1V1.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Eval.menu.pnum.STEVAL_MKSBOX1V1.openocd.target=stm32l4x Eval.menu.pnum.STEVAL_MKSBOX1V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4R9.svd # STEVAL_MKBOXPRO board @@ -1403,7 +1485,7 @@ Eval.menu.pnum.STEVAL_MKBOXPRO.build.series=STM32U5xx Eval.menu.pnum.STEVAL_MKBOXPRO.build.product_line=STM32U585xx Eval.menu.pnum.STEVAL_MKBOXPRO.build.variant=STM32U5xx/U575A(G-I)IxQ_U585AIIxQ Eval.menu.pnum.STEVAL_MKBOXPRO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Eval.menu.pnum.STEVAL_MKBOXPRO.debug.server.openocd.scripts.2=target/stm32u5x.cfg +Eval.menu.pnum.STEVAL_MKBOXPRO.openocd.target=stm32u5x Eval.menu.pnum.STEVAL_MKBOXPRO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U585.svd # Upload menu @@ -1412,11 +1494,24 @@ Eval.menu.upload_method.swdMethod.upload.protocol=swd Eval.menu.upload_method.swdMethod.upload.options= Eval.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Eval.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Eval.menu.upload_method.jlinkMethod.upload.protocol=jlink +Eval.menu.upload_method.jlinkMethod.upload.options= +Eval.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Eval.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Eval.menu.upload_method.dfuMethod.upload.protocol=dfu Eval.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Eval.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Eval.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Eval.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Eval.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Eval.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Eval.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Eval.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # STM32MP1 microprocessor series (MPU + MCU) @@ -1470,7 +1565,7 @@ GenC0.build.st_extra_flags=-D{build.product_line} {build.xSerial} -D__CORTEX_SC= GenC0.build.flash_offset=0x0 GenC0.upload.maximum_size=0 GenC0.upload.maximum_data_size=0 -GenC0.debug.server.openocd.scripts.2=target/stm32c0x.cfg +GenC0.openocd.target=stm32c0x # Generic C011D6Yx GenC0.menu.pnum.GENERIC_C011D6YX=Generic C011D6Yx @@ -1589,17 +1684,48 @@ GenC0.menu.pnum.GENERIC_C031F6PX.build.product_line=STM32C031xx GenC0.menu.pnum.GENERIC_C031F6PX.build.variant=STM32C0xx/C011D6Y_C011F(4-6)(P-U)_C031F(4-6)P GenC0.menu.pnum.GENERIC_C031F6PX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C031.svd +# Generic C071R8Tx +GenC0.menu.pnum.GENERIC_C071R8TX=Generic C071R8Tx +GenC0.menu.pnum.GENERIC_C071R8TX.upload.maximum_size=65536 +GenC0.menu.pnum.GENERIC_C071R8TX.upload.maximum_data_size=24576 +GenC0.menu.pnum.GENERIC_C071R8TX.build.board=GENERIC_C071R8TX +GenC0.menu.pnum.GENERIC_C071R8TX.build.product_line=STM32C071xx +GenC0.menu.pnum.GENERIC_C071R8TX.build.variant=STM32C0xx/C071R(8-B)T +GenC0.menu.pnum.GENERIC_C071R8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd + +# Generic C071RBTx +GenC0.menu.pnum.GENERIC_C071RBTX=Generic C071RBTx +GenC0.menu.pnum.GENERIC_C071RBTX.upload.maximum_size=131072 +GenC0.menu.pnum.GENERIC_C071RBTX.upload.maximum_data_size=24576 +GenC0.menu.pnum.GENERIC_C071RBTX.build.board=GENERIC_C071RBTX +GenC0.menu.pnum.GENERIC_C071RBTX.build.product_line=STM32C071xx +GenC0.menu.pnum.GENERIC_C071RBTX.build.variant=STM32C0xx/C071R(8-B)T +GenC0.menu.pnum.GENERIC_C071RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32C0xx/STM32C071.svd + # Upload menu GenC0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) GenC0.menu.upload_method.swdMethod.upload.protocol=swd GenC0.menu.upload_method.swdMethod.upload.options= GenC0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenC0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenC0.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenC0.menu.upload_method.jlinkMethod.upload.options= +GenC0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenC0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenC0.menu.upload_method.serialMethod.upload.protocol=serial GenC0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} GenC0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg +GenC0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenC0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenC0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenC0.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenC0.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenC0.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ############################### # Generic F0 GenF0.name=Generic STM32F0 series @@ -1612,7 +1738,7 @@ GenF0.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSer GenF0.build.flash_offset=0x0 GenF0.upload.maximum_size=0 GenF0.upload.maximum_data_size=0 -GenF0.debug.server.openocd.scripts.2=target/stm32f0x.cfg +GenF0.openocd.target=stm32f0x GenF0.vid.0=0x0483 GenF0.pid.0=0x5740 @@ -2498,6 +2624,11 @@ GenF0.menu.upload_method.swdMethod.upload.protocol=swd GenF0.menu.upload_method.swdMethod.upload.options= GenF0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenF0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenF0.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenF0.menu.upload_method.jlinkMethod.upload.options= +GenF0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenF0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF0.menu.upload_method.serialMethod.upload.protocol=serial GenF0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -2508,6 +2639,14 @@ GenF0.menu.upload_method.dfuMethod.upload.protocol=dfu GenF0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenF0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenF0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenF0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenF0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenF0.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenF0.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenF0.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic F1 GenF1.name=Generic STM32F1 series @@ -2520,7 +2659,7 @@ GenF1.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSer GenF1.build.flash_offset=0x0 GenF1.upload.maximum_size=0 GenF1.upload.maximum_data_size=0 -GenF1.debug.server.openocd.scripts.2=target/stm32f1x.cfg +GenF1.openocd.target=stm32f1x GenF1.vid.0=0x0483 GenF1.pid.0=0x5740 # DFU mode on built-in bootloader not available, assuming using STM32duino-bootloader @@ -3318,6 +3457,11 @@ GenF1.menu.upload_method.swdMethod.upload.protocol=swd GenF1.menu.upload_method.swdMethod.upload.options= GenF1.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenF1.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenF1.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenF1.menu.upload_method.jlinkMethod.upload.options= +GenF1.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenF1.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF1.menu.upload_method.serialMethod.upload.protocol=serial GenF1.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -3352,6 +3496,14 @@ GenF1.menu.upload_method.dfuoMethod.upload.altID=1 GenF1.menu.upload_method.dfuoMethod.build.flash_offset=0x5000 GenF1.menu.upload_method.dfuoMethod.build.bootloader_flags=-DBL_LEGACY_LEAF +GenF1.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenF1.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenF1.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenF1.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenF1.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenF1.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic F2 GenF2.name=Generic STM32F2 series @@ -3364,7 +3516,7 @@ GenF2.build.series=STM32F2xx GenF2.build.flash_offset=0x0 GenF2.upload.maximum_size=0 GenF2.upload.maximum_data_size=0 -GenF2.debug.server.openocd.scripts.2=target/stm32f2x.cfg +GenF2.openocd.target=stm32f2x GenF2.vid.0=0x0483 GenF2.pid.0=0x5740 @@ -3797,6 +3949,11 @@ GenF2.menu.upload_method.swdMethod.upload.protocol=swd GenF2.menu.upload_method.swdMethod.upload.options= GenF2.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenF2.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenF2.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenF2.menu.upload_method.jlinkMethod.upload.options= +GenF2.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenF2.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF2.menu.upload_method.serialMethod.upload.protocol=serial GenF2.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -3807,6 +3964,14 @@ GenF2.menu.upload_method.dfuMethod.upload.protocol=dfu GenF2.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenF2.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenF2.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenF2.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenF2.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenF2.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenF2.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenF2.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic F3 @@ -3822,7 +3987,7 @@ GenF3.build.series=STM32F3xx GenF3.build.flash_offset=0x0 GenF3.upload.maximum_size=0 GenF3.upload.maximum_data_size=0 -GenF3.debug.server.openocd.scripts.2=target/stm32f3x.cfg +GenF3.openocd.target=stm32f3x GenF3.vid.0=0x0483 GenF3.pid.0=0x5740 @@ -4248,6 +4413,11 @@ GenF3.menu.upload_method.swdMethod.upload.protocol=swd GenF3.menu.upload_method.swdMethod.upload.options= GenF3.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenF3.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenF3.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenF3.menu.upload_method.jlinkMethod.upload.options= +GenF3.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenF3.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF3.menu.upload_method.serialMethod.upload.protocol=serial GenF3.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -4262,6 +4432,14 @@ GenF3.menu.upload_method.bmpMethod=BMP (Black Magic Probe) GenF3.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp GenF3.menu.upload_method.bmpMethod.upload.tool=bmp_upload +GenF3.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenF3.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenF3.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenF3.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenF3.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenF3.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic F4 @@ -4277,7 +4455,7 @@ GenF4.build.series=STM32F4xx GenF4.build.flash_offset=0x0 GenF4.upload.maximum_size=0 GenF4.upload.maximum_data_size=0 -GenF4.debug.server.openocd.scripts.2=target/stm32f4x.cfg +GenF4.openocd.target=stm32f4x GenF4.vid.0=0x0483 GenF4.pid.0=0x5740 @@ -5257,6 +5435,11 @@ GenF4.menu.upload_method.swdMethod.upload.protocol=swd GenF4.menu.upload_method.swdMethod.upload.options= GenF4.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenF4.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenF4.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenF4.menu.upload_method.jlinkMethod.upload.options= +GenF4.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenF4.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF4.menu.upload_method.serialMethod.upload.protocol=serial GenF4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -5277,6 +5460,14 @@ GenF4.menu.upload_method.hidMethod.upload.tool=hid_upload GenF4.menu.upload_method.hidMethod.build.flash_offset=0x4000 GenF4.menu.upload_method.hidMethod.build.bootloader_flags=-DBL_HID +GenF4.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenF4.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenF4.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenF4.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenF4.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenF4.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic F7 @@ -5292,7 +5483,7 @@ GenF7.build.series=STM32F7xx GenF7.build.flash_offset=0x0 GenF7.upload.maximum_size=0 GenF7.upload.maximum_data_size=0 -GenF7.debug.server.openocd.scripts.2=target/stm32f7x.cfg +GenF7.openocd.target=stm32f7x GenF7.vid.0=0x0483 GenF7.pid.0=0x5740 @@ -5797,6 +5988,11 @@ GenF7.menu.upload_method.swdMethod.upload.protocol=swd GenF7.menu.upload_method.swdMethod.upload.options= GenF7.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenF7.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenF7.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenF7.menu.upload_method.jlinkMethod.upload.options= +GenF7.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenF7.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenF7.menu.upload_method.serialMethod.upload.protocol=serial GenF7.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -5807,6 +6003,14 @@ GenF7.menu.upload_method.dfuMethod.upload.protocol=dfu GenF7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenF7.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenF7.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenF7.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenF7.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenF7.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenF7.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenF7.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ############################### # Generic G0 GenG0.name=Generic STM32G0 series @@ -5819,7 +6023,7 @@ GenG0.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSer GenG0.build.flash_offset=0x0 GenG0.upload.maximum_size=0 GenG0.upload.maximum_data_size=0 -GenG0.debug.server.openocd.scripts.2=target/stm32g0x.cfg +GenG0.openocd.target=stm32g0x GenG0.vid.0=0x0483 GenG0.pid.0=0x5740 @@ -7208,6 +7412,11 @@ GenG0.menu.upload_method.swdMethod.upload.protocol=swd GenG0.menu.upload_method.swdMethod.upload.options= GenG0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenG0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenG0.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenG0.menu.upload_method.jlinkMethod.upload.options= +GenG0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenG0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenG0.menu.upload_method.serialMethod.upload.protocol=serial GenG0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -7218,6 +7427,14 @@ GenG0.menu.upload_method.dfuMethod.upload.protocol=dfu GenG0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenG0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenG0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenG0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenG0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenG0.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenG0.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenG0.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ############################### # Generic G4 GenG4.name=Generic STM32G4 series @@ -7232,7 +7449,7 @@ GenG4.build.series=STM32G4xx GenG4.build.flash_offset=0x0 GenG4.upload.maximum_size=0 GenG4.upload.maximum_data_size=0 -GenG4.debug.server.openocd.scripts.2=target/stm32g4x.cfg +GenG4.openocd.target=stm32g4x GenG4.vid.0=0x0483 GenG4.pid.0=0x5740 @@ -7377,7 +7594,7 @@ GenG4.menu.pnum.GENERIC_G431R6IX.upload.maximum_size=32768 GenG4.menu.pnum.GENERIC_G431R6IX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G431R6IX.build.board=GENERIC_G431R6IX GenG4.menu.pnum.GENERIC_G431R6IX.build.product_line=STM32G431xx -GenG4.menu.pnum.GENERIC_G431R6IX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431R6IX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G431R6IX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G431R8Ix @@ -7386,7 +7603,7 @@ GenG4.menu.pnum.GENERIC_G431R8IX.upload.maximum_size=65536 GenG4.menu.pnum.GENERIC_G431R8IX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G431R8IX.build.board=GENERIC_G431R8IX GenG4.menu.pnum.GENERIC_G431R8IX.build.product_line=STM32G431xx -GenG4.menu.pnum.GENERIC_G431R8IX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431R8IX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G431R8IX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G431RBIx @@ -7395,7 +7612,7 @@ GenG4.menu.pnum.GENERIC_G431RBIX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G431RBIX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G431RBIX.build.board=GENERIC_G431RBIX GenG4.menu.pnum.GENERIC_G431RBIX.build.product_line=STM32G431xx -GenG4.menu.pnum.GENERIC_G431RBIX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431RBIX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G431RBIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G431R6Tx @@ -7404,7 +7621,7 @@ GenG4.menu.pnum.GENERIC_G431R6TX.upload.maximum_size=32768 GenG4.menu.pnum.GENERIC_G431R6TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G431R6TX.build.board=GENERIC_G431R6TX GenG4.menu.pnum.GENERIC_G431R6TX.build.product_line=STM32G431xx -GenG4.menu.pnum.GENERIC_G431R6TX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431R6TX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G431R6TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G431R8Tx @@ -7413,7 +7630,7 @@ GenG4.menu.pnum.GENERIC_G431R8TX.upload.maximum_size=65536 GenG4.menu.pnum.GENERIC_G431R8TX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G431R8TX.build.board=GENERIC_G431R8TX GenG4.menu.pnum.GENERIC_G431R8TX.build.product_line=STM32G431xx -GenG4.menu.pnum.GENERIC_G431R8TX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431R8TX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G431R8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd # Generic G431RBTx @@ -7422,9 +7639,18 @@ GenG4.menu.pnum.GENERIC_G431RBTX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G431RBTX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G431RBTX.build.board=GENERIC_G431RBTX GenG4.menu.pnum.GENERIC_G431RBTX.build.product_line=STM32G431xx -GenG4.menu.pnum.GENERIC_G431RBTX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431RBTX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G431RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd +# Generic G431RBTxZ +GenG4.menu.pnum.GENERIC_G431RBTXZ=Generic G431RBTxZ +GenG4.menu.pnum.GENERIC_G431RBTXZ.upload.maximum_size=131072 +GenG4.menu.pnum.GENERIC_G431RBTXZ.upload.maximum_data_size=32768 +GenG4.menu.pnum.GENERIC_G431RBTXZ.build.board=GENERIC_G431RBTXZ +GenG4.menu.pnum.GENERIC_G431RBTXZ.build.product_line=STM32G431xx +GenG4.menu.pnum.GENERIC_G431RBTXZ.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G431RBTXZ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G431.svd + # Generic G431V6Tx GenG4.menu.pnum.GENERIC_G431V6TX=Generic G431V6Tx GenG4.menu.pnum.GENERIC_G431V6TX.upload.maximum_size=32768 @@ -7503,7 +7729,7 @@ GenG4.menu.pnum.GENERIC_G441RBIX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G441RBIX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G441RBIX.build.board=GENERIC_G441RBIX GenG4.menu.pnum.GENERIC_G441RBIX.build.product_line=STM32G441xx -GenG4.menu.pnum.GENERIC_G441RBIX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G441RBIX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G441RBIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G441.svd # Generic G441RBTx @@ -7512,7 +7738,7 @@ GenG4.menu.pnum.GENERIC_G441RBTX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G441RBTX.upload.maximum_data_size=32768 GenG4.menu.pnum.GENERIC_G441RBTX.build.board=GENERIC_G441RBTX GenG4.menu.pnum.GENERIC_G441RBTX.build.product_line=STM32G441xx -GenG4.menu.pnum.GENERIC_G441RBTX.build.variant=STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T) +GenG4.menu.pnum.GENERIC_G441RBTX.build.variant=STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T) GenG4.menu.pnum.GENERIC_G441RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G441.svd # Generic G441VBTx @@ -7737,7 +7963,7 @@ GenG4.menu.pnum.GENERIC_G473RBTX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G473RBTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G473RBTX.build.board=GENERIC_G473RBTX GenG4.menu.pnum.GENERIC_G473RBTX.build.product_line=STM32G473xx -GenG4.menu.pnum.GENERIC_G473RBTX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G473RBTX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G473RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd # Generic G473RCTx @@ -7746,7 +7972,7 @@ GenG4.menu.pnum.GENERIC_G473RCTX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G473RCTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G473RCTX.build.board=GENERIC_G473RCTX GenG4.menu.pnum.GENERIC_G473RCTX.build.product_line=STM32G473xx -GenG4.menu.pnum.GENERIC_G473RCTX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G473RCTX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G473RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd # Generic G473RETx @@ -7755,7 +7981,7 @@ GenG4.menu.pnum.GENERIC_G473RETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G473RETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G473RETX.build.board=GENERIC_G473RETX GenG4.menu.pnum.GENERIC_G473RETX.build.product_line=STM32G473xx -GenG4.menu.pnum.GENERIC_G473RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G473RETX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G473RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd # Generic G473QBTx @@ -7764,7 +7990,7 @@ GenG4.menu.pnum.GENERIC_G473QBTX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G473QBTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G473QBTX.build.board=GENERIC_G473QBTX GenG4.menu.pnum.GENERIC_G473QBTX.build.product_line=STM32G473xx -GenG4.menu.pnum.GENERIC_G473QBTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G473QBTX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G473QBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd # Generic G473QCTx @@ -7773,7 +7999,7 @@ GenG4.menu.pnum.GENERIC_G473QCTX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G473QCTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G473QCTX.build.board=GENERIC_G473QCTX GenG4.menu.pnum.GENERIC_G473QCTX.build.product_line=STM32G473xx -GenG4.menu.pnum.GENERIC_G473QCTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G473QCTX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G473QCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd # Generic G473QETx @@ -7782,9 +8008,18 @@ GenG4.menu.pnum.GENERIC_G473QETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G473QETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G473QETX.build.board=GENERIC_G473QETX GenG4.menu.pnum.GENERIC_G473QETX.build.product_line=STM32G473xx -GenG4.menu.pnum.GENERIC_G473QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G473QETX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G473QETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd +# Generic G473QETxZ +GenG4.menu.pnum.GENERIC_G473QETXZ=Generic G473QETxZ +GenG4.menu.pnum.GENERIC_G473QETXZ.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G473QETXZ.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G473QETXZ.build.board=GENERIC_G473QETXZ +GenG4.menu.pnum.GENERIC_G473QETXZ.build.product_line=STM32G473xx +GenG4.menu.pnum.GENERIC_G473QETXZ.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G473QETXZ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd + # Generic G473VBHx GenG4.menu.pnum.GENERIC_G473VBHX=Generic G473VBHx GenG4.menu.pnum.GENERIC_G473VBHX.upload.maximum_size=131072 @@ -7926,7 +8161,7 @@ GenG4.menu.pnum.GENERIC_G474RBTX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G474RBTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G474RBTX.build.board=GENERIC_G474RBTX GenG4.menu.pnum.GENERIC_G474RBTX.build.product_line=STM32G474xx -GenG4.menu.pnum.GENERIC_G474RBTX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G474RBTX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G474RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd # Generic G474RCTx @@ -7935,7 +8170,7 @@ GenG4.menu.pnum.GENERIC_G474RCTX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G474RCTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G474RCTX.build.board=GENERIC_G474RCTX GenG4.menu.pnum.GENERIC_G474RCTX.build.product_line=STM32G474xx -GenG4.menu.pnum.GENERIC_G474RCTX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G474RCTX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G474RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd # Generic G474RETx @@ -7944,16 +8179,25 @@ GenG4.menu.pnum.GENERIC_G474RETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G474RETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G474RETX.build.board=GENERIC_G474RETX GenG4.menu.pnum.GENERIC_G474RETX.build.product_line=STM32G474xx -GenG4.menu.pnum.GENERIC_G474RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G474RETX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G474RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd +# Generic G473RETxZ +GenG4.menu.pnum.GENERIC_G473RETXZ=Generic G473RETxZ +GenG4.menu.pnum.GENERIC_G473RETXZ.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G473RETXZ.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G473RETXZ.build.board=GENERIC_G473RETXZ +GenG4.menu.pnum.GENERIC_G473RETXZ.build.product_line=STM32G473xx +GenG4.menu.pnum.GENERIC_G473RETXZ.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G473RETXZ.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G473.svd + # Generic G474QBTx GenG4.menu.pnum.GENERIC_G474QBTX=Generic G474QBTx GenG4.menu.pnum.GENERIC_G474QBTX.upload.maximum_size=131072 GenG4.menu.pnum.GENERIC_G474QBTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G474QBTX.build.board=GENERIC_G474QBTX GenG4.menu.pnum.GENERIC_G474QBTX.build.product_line=STM32G474xx -GenG4.menu.pnum.GENERIC_G474QBTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G474QBTX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G474QBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd # Generic G474QCTx @@ -7962,7 +8206,7 @@ GenG4.menu.pnum.GENERIC_G474QCTX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G474QCTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G474QCTX.build.board=GENERIC_G474QCTX GenG4.menu.pnum.GENERIC_G474QCTX.build.product_line=STM32G474xx -GenG4.menu.pnum.GENERIC_G474QCTX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G474QCTX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G474QCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd # Generic G474QETx @@ -7971,7 +8215,7 @@ GenG4.menu.pnum.GENERIC_G474QETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G474QETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G474QETX.build.board=GENERIC_G474QETX GenG4.menu.pnum.GENERIC_G474QETX.build.product_line=STM32G474xx -GenG4.menu.pnum.GENERIC_G474QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G474QETX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G474QETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G474.svd # Generic G474VBHx @@ -8061,7 +8305,7 @@ GenG4.menu.pnum.GENERIC_G483RETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G483RETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G483RETX.build.board=GENERIC_G483RETX GenG4.menu.pnum.GENERIC_G483RETX.build.product_line=STM32G483xx -GenG4.menu.pnum.GENERIC_G483RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G483RETX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G483RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G483.svd # Generic G483QETx @@ -8070,7 +8314,7 @@ GenG4.menu.pnum.GENERIC_G483QETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G483QETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G483QETX.build.board=GENERIC_G483QETX GenG4.menu.pnum.GENERIC_G483QETX.build.product_line=STM32G483xx -GenG4.menu.pnum.GENERIC_G483QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G483QETX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G483QETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G483.svd # Generic G483VEHx @@ -8124,7 +8368,7 @@ GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G484QETX.build.board=GENERIC_G484QETX GenG4.menu.pnum.GENERIC_G484QETX.build.product_line=STM32G484xx -GenG4.menu.pnum.GENERIC_G484QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET +GenG4.menu.pnum.GENERIC_G484QETX.build.variant=STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET GenG4.menu.pnum.GENERIC_G484QETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd # Generic G484RETx @@ -8133,7 +8377,7 @@ GenG4.menu.pnum.GENERIC_G484RETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G484RETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G484RETX.build.board=GENERIC_G484RETX GenG4.menu.pnum.GENERIC_G484RETX.build.product_line=STM32G484xx -GenG4.menu.pnum.GENERIC_G484RETX.build.variant=STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET +GenG4.menu.pnum.GENERIC_G484RETX.build.variant=STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET GenG4.menu.pnum.GENERIC_G484RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd # Generic G484VEHx @@ -8154,15 +8398,6 @@ GenG4.menu.pnum.GENERIC_G484VETX.build.product_line=STM32G484xx GenG4.menu.pnum.GENERIC_G484VETX.build.variant=STM32G4xx/G473V(B-C-E)(H-T)_G474V(B-C-E)(H-T)_G483VE(H-T)_G484VE(H-T) GenG4.menu.pnum.GENERIC_G484VETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd -# Generic G484QETx -GenG4.menu.pnum.GENERIC_G484QETX=Generic G484QETx -GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_size=524288 -GenG4.menu.pnum.GENERIC_G484QETX.upload.maximum_data_size=131072 -GenG4.menu.pnum.GENERIC_G484QETX.build.board=GENERIC_G484QETX -GenG4.menu.pnum.GENERIC_G484QETX.build.product_line=STM32G484xx -GenG4.menu.pnum.GENERIC_G484QETX.build.variant=STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET -GenG4.menu.pnum.GENERIC_G484QETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G484.svd - # Generic G491CCTx GenG4.menu.pnum.GENERIC_G491CCTX=Generic G491CCTx GenG4.menu.pnum.GENERIC_G491CCTX.upload.maximum_size=262144 @@ -8241,7 +8476,7 @@ GenG4.menu.pnum.GENERIC_G491RCIX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G491RCIX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491RCIX.build.board=GENERIC_G491RCIX GenG4.menu.pnum.GENERIC_G491RCIX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491RCIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G491RCIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G491RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd # Generic G491REIx @@ -8250,7 +8485,7 @@ GenG4.menu.pnum.GENERIC_G491REIX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G491REIX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491REIX.build.board=GENERIC_G491REIX GenG4.menu.pnum.GENERIC_G491REIX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G491REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G491REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd # Generic G491RCTx @@ -8259,7 +8494,7 @@ GenG4.menu.pnum.GENERIC_G491RCTX.upload.maximum_size=262144 GenG4.menu.pnum.GENERIC_G491RCTX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491RCTX.build.board=GENERIC_G491RCTX GenG4.menu.pnum.GENERIC_G491RCTX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491RCTX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G491RCTX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G491RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd # Generic G491RETx @@ -8268,16 +8503,24 @@ GenG4.menu.pnum.GENERIC_G491RETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G491RETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491RETX.build.board=GENERIC_G491RETX GenG4.menu.pnum.GENERIC_G491RETX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491RETX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G491RETX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G491RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd +# Generic G491RETxZ +GenG4.menu.pnum.GENERIC_G491RETXZ=Generic G491RETxZ +GenG4.menu.pnum.GENERIC_G491RETXZ.upload.maximum_size=524288 +GenG4.menu.pnum.GENERIC_G491RETXZ.upload.maximum_data_size=131072 +GenG4.menu.pnum.GENERIC_G491RETXZ.build.board=GENERIC_G491RETXZ +GenG4.menu.pnum.GENERIC_G491RETXZ.build.product_line=STM32G491xx +GenG4.menu.pnum.GENERIC_G491RETXZ.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) + # Generic G491REYx GenG4.menu.pnum.GENERIC_G491REYX=Generic G491REYx GenG4.menu.pnum.GENERIC_G491REYX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G491REYX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G491REYX.build.board=GENERIC_G491REYX GenG4.menu.pnum.GENERIC_G491REYX.build.product_line=STM32G491xx -GenG4.menu.pnum.GENERIC_G491REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G491REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G491REYX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G491.svd # Generic G491VCTx @@ -8304,7 +8547,7 @@ GenG4.menu.pnum.GENERIC_G4A1REIX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G4A1REIX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G4A1REIX.build.board=GENERIC_G4A1REIX GenG4.menu.pnum.GENERIC_G4A1REIX.build.product_line=STM32G4A1xx -GenG4.menu.pnum.GENERIC_G4A1REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G4A1REIX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G4A1REIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G4A1.svd # Generic G4A1CETx @@ -8349,7 +8592,7 @@ GenG4.menu.pnum.GENERIC_G4A1RETX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G4A1RETX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G4A1RETX.build.board=GENERIC_G4A1RETX GenG4.menu.pnum.GENERIC_G4A1RETX.build.product_line=STM32G4A1xx -GenG4.menu.pnum.GENERIC_G4A1RETX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G4A1RETX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G4A1RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G4A1.svd # Generic G4A1REYx @@ -8358,7 +8601,7 @@ GenG4.menu.pnum.GENERIC_G4A1REYX.upload.maximum_size=524288 GenG4.menu.pnum.GENERIC_G4A1REYX.upload.maximum_data_size=131072 GenG4.menu.pnum.GENERIC_G4A1REYX.build.board=GENERIC_G4A1REYX GenG4.menu.pnum.GENERIC_G4A1REYX.build.product_line=STM32G4A1xx -GenG4.menu.pnum.GENERIC_G4A1REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y) +GenG4.menu.pnum.GENERIC_G4A1REYX.build.variant=STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y) GenG4.menu.pnum.GENERIC_G4A1REYX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G4xx/STM32G4A1.svd # Generic G4A1VETx @@ -8376,6 +8619,11 @@ GenG4.menu.upload_method.swdMethod.upload.protocol=swd GenG4.menu.upload_method.swdMethod.upload.options= GenG4.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenG4.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenG4.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenG4.menu.upload_method.jlinkMethod.upload.options= +GenG4.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenG4.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenG4.menu.upload_method.serialMethod.upload.protocol=serial GenG4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -8386,6 +8634,14 @@ GenG4.menu.upload_method.dfuMethod.upload.protocol=dfu GenG4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenG4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenG4.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenG4.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenG4.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenG4.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenG4.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenG4.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic H5 GenH5.name=Generic STM32H5 series @@ -8401,10 +8657,39 @@ GenH5.build.flash_offset=0x0 GenH5.upload.maximum_size=0 GenH5.upload.maximum_data_size=0 # Current openocd version does not support H5 -# GenH5.debug.server.openocd.scripts.2=target/stm32h5x.cfg +# GenH5.openocd.target=stm32h5x GenH5.vid.0=0x0483 GenH5.pid.0=0x5740 +# WeAct H562RGT +GenH5.menu.pnum.WEACT_H562RG=WeAct H562RGT +GenH5.menu.pnum.WEACT_H562RG.upload.maximum_size=1048576 +GenH5.menu.pnum.WEACT_H562RG.upload.maximum_data_size=655360 +GenH5.menu.pnum.WEACT_H562RG.build.board=WEACT_H562RG +GenH5.menu.pnum.WEACT_H562RG.build.product_line=STM32H562xx +GenH5.menu.pnum.WEACT_H562RG.build.variant=STM32H5xx/H562R(G-I)T +GenH5.menu.pnum.WEACT_H562RG.build.variant_h=variant_WEACT_H562RG.h +GenH5.menu.pnum.WEACT_H562RG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +GenH5.menu.pnum.WEACT_H562RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd + +# Generic H503CBTx +GenH5.menu.pnum.GENERIC_H503CBTX=Generic H503CBTx +GenH5.menu.pnum.GENERIC_H503CBTX.upload.maximum_size=131072 +GenH5.menu.pnum.GENERIC_H503CBTX.upload.maximum_data_size=32768 +GenH5.menu.pnum.GENERIC_H503CBTX.build.board=GENERIC_H503CBTX +GenH5.menu.pnum.GENERIC_H503CBTX.build.product_line=STM32H503xx +GenH5.menu.pnum.GENERIC_H503CBTX.build.variant=STM32H5xx/H503CB(T-U) +GenH5.menu.pnum.GENERIC_H503CBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd + +# Generic H503CBUx +GenH5.menu.pnum.GENERIC_H503CBUX=Generic H503CBUx +GenH5.menu.pnum.GENERIC_H503CBUX.upload.maximum_size=131072 +GenH5.menu.pnum.GENERIC_H503CBUX.upload.maximum_data_size=32768 +GenH5.menu.pnum.GENERIC_H503CBUX.build.board=GENERIC_H503CBUX +GenH5.menu.pnum.GENERIC_H503CBUX.build.product_line=STM32H503xx +GenH5.menu.pnum.GENERIC_H503CBUX.build.variant=STM32H5xx/H503CB(T-U) +GenH5.menu.pnum.GENERIC_H503CBUX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd + # Generic H503KBUx GenH5.menu.pnum.GENERIC_H503KBUX=Generic H503KBUx GenH5.menu.pnum.GENERIC_H503KBUX.upload.maximum_size=131072 @@ -8423,6 +8708,24 @@ GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT GenH5.menu.pnum.GENERIC_H503RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd +# Generic H562RGTx +GenH5.menu.pnum.GENERIC_H562RGTX=Generic H562RGTx +GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_size=1048576 +GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H562RGTX.build.board=GENERIC_H562RGTX +GenH5.menu.pnum.GENERIC_H562RGTX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H562RGTX.build.variant=STM32H5xx/H562R(G-I)T +GenH5.menu.pnum.GENERIC_H562RGTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd + +# Generic H562RITx +GenH5.menu.pnum.GENERIC_H562RITX=Generic H562RITx +GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_size=2097152 +GenH5.menu.pnum.GENERIC_H562RITX.upload.maximum_data_size=655360 +GenH5.menu.pnum.GENERIC_H562RITX.build.board=GENERIC_H562RITX +GenH5.menu.pnum.GENERIC_H562RITX.build.product_line=STM32H562xx +GenH5.menu.pnum.GENERIC_H562RITX.build.variant=STM32H5xx/H562R(G-I)T +GenH5.menu.pnum.GENERIC_H562RITX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H562.svd + # Generic H563IIKxQ GenH5.menu.pnum.GENERIC_H563IIKXQ=Generic H563IIKxQ GenH5.menu.pnum.GENERIC_H563IIKXQ.upload.maximum_size=2097152 @@ -8501,6 +8804,11 @@ GenH5.menu.upload_method.swdMethod.upload.protocol=swd GenH5.menu.upload_method.swdMethod.upload.options= GenH5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenH5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenH5.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenH5.menu.upload_method.jlinkMethod.upload.options= +GenH5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenH5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenH5.menu.upload_method.serialMethod.upload.protocol=serial GenH5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -8511,6 +8819,14 @@ GenH5.menu.upload_method.dfuMethod.upload.protocol=dfu GenH5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenH5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +#GenH5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +#GenH5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +#GenH5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +#GenH5.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +#GenH5.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +#GenH5.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic H7 GenH7.name=Generic STM32H7 Series @@ -8525,7 +8841,7 @@ GenH7.build.mcu=cortex-m7 GenH7.build.flash_offset=0x0 GenH7.upload.maximum_size=0 GenH7.upload.maximum_data_size=0 -GenH7.debug.server.openocd.scripts.2=target/stm32h7x.cfg +GenH7.openocd.target=stm32h7x GenH7.vid.0=0x0483 GenH7.pid.0=0x5740 @@ -9137,6 +9453,11 @@ GenH7.menu.upload_method.swdMethod.upload.protocol=swd GenH7.menu.upload_method.swdMethod.upload.options= GenH7.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenH7.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenH7.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenH7.menu.upload_method.jlinkMethod.upload.options= +GenH7.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenH7.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenH7.menu.upload_method.serialMethod.upload.protocol=serial GenH7.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -9147,6 +9468,14 @@ GenH7.menu.upload_method.dfuMethod.upload.protocol=dfu GenH7.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenH7.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenH7.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenH7.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenH7.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenH7.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenH7.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenH7.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic L0 GenL0.name=Generic STM32L0 series @@ -9159,7 +9488,7 @@ GenL0.build.series=STM32L0xx GenL0.build.flash_offset=0x0 GenL0.upload.maximum_size=0 GenL0.upload.maximum_data_size=0 -GenL0.debug.server.openocd.scripts.2=target/stm32l0x.cfg +GenL0.openocd.target=stm32l0 GenL0.vid.0=0x0483 GenL0.pid.0=0x5740 @@ -10415,6 +10744,11 @@ GenL0.menu.upload_method.swdMethod.upload.protocol=swd GenL0.menu.upload_method.swdMethod.upload.options= GenL0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenL0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenL0.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenL0.menu.upload_method.jlinkMethod.upload.options= +GenL0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenL0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL0.menu.upload_method.serialMethod.upload.protocol=serial GenL0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -10429,6 +10763,14 @@ GenL0.menu.upload_method.bmpMethod=BMP (Black Magic Probe) GenL0.menu.upload_method.bmpMethod.upload.protocol=gdb_bmp GenL0.menu.upload_method.bmpMethod.upload.tool=bmp_upload +GenL0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenL0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenL0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenL0.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenL0.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenL0.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic L1 GenL1.name=Generic STM32L1 series @@ -10441,7 +10783,7 @@ GenL1.build.series=STM32L1xx GenL1.build.flash_offset=0x0 GenL1.upload.maximum_size=0 GenL1.upload.maximum_data_size=0 -GenL1.debug.server.openocd.scripts.2=target/stm32l1x.cfg +GenL1.openocd.target=stm32l1 GenL1.vid.0=0x0483 GenL1.pid.0=0x5740 @@ -10739,6 +11081,11 @@ GenL1.menu.upload_method.swdMethod.upload.protocol=swd GenL1.menu.upload_method.swdMethod.upload.options= GenL1.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenL1.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenL1.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenL1.menu.upload_method.jlinkMethod.upload.options= +GenL1.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenL1.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL1.menu.upload_method.serialMethod.upload.protocol=serial GenL1.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -10749,6 +11096,14 @@ GenL1.menu.upload_method.dfuMethod.upload.protocol=dfu GenL1.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenL1.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenL1.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenL1.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenL1.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenL1.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenL1.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenL1.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic L4 GenL4.name=Generic STM32L4 series @@ -10763,7 +11118,7 @@ GenL4.build.series=STM32L4xx GenL4.build.flash_offset=0x0 GenL4.upload.maximum_size=0 GenL4.upload.maximum_data_size=0 -GenL4.debug.server.openocd.scripts.2=target/stm32l4x.cfg +GenL4.openocd.target=stm32l4x GenL4.vid.0=0x0483 GenL4.pid.0=0x5740 @@ -11539,6 +11894,11 @@ GenL4.menu.upload_method.swdMethod.upload.protocol=swd GenL4.menu.upload_method.swdMethod.upload.options= GenL4.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenL4.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenL4.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenL4.menu.upload_method.jlinkMethod.upload.options= +GenL4.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenL4.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL4.menu.upload_method.serialMethod.upload.protocol=serial GenL4.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -11549,6 +11909,14 @@ GenL4.menu.upload_method.dfuMethod.upload.protocol=dfu GenL4.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenL4.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenL4.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenL4.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenL4.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenL4.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenL4.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenL4.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic L5 GenL5.name=Generic STM32L5 series @@ -11563,7 +11931,7 @@ GenL5.build.series=STM32L5xx GenL5.build.flash_offset=0x0 GenL5.upload.maximum_size=0 GenL5.upload.maximum_data_size=0 -GenL5.debug.server.openocd.scripts.2=target/stm32l5x.cfg +GenL5.openocd.target=stm32l5x GenL5.vid.0=0x0483 GenL5.pid.0=0x5740 @@ -11600,6 +11968,11 @@ GenL5.menu.upload_method.swdMethod.upload.protocol=swd GenL5.menu.upload_method.swdMethod.upload.options= GenL5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenL5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenL5.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenL5.menu.upload_method.jlinkMethod.upload.options= +GenL5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenL5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenL5.menu.upload_method.serialMethod.upload.protocol=serial GenL5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -11610,6 +11983,132 @@ GenL5.menu.upload_method.dfuMethod.upload.protocol=dfu GenL5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenL5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenL5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenL5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenL5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenL5.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenL5.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenL5.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + +############################### +# Generic U0 +GenU0.name=Generic STM32U0 series + +GenU0.build.core=arduino +GenU0.build.board=GenG0 +GenU0.build.mcu=cortex-m0plus +GenU0.build.series=STM32U0xx +GenU0.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 +GenU0.build.flash_offset=0x0 +GenU0.upload.maximum_size=0 +GenU0.upload.maximum_data_size=0 +# Current openocd version does not support U0 +# GenU0.openocd.target=stm32u0x +GenU0.vid.0=0x0483 +GenU0.pid.0=0x5740 + +# Generic U073R8Ix +GenU0.menu.pnum.GENERIC_U073R8IX=Generic U073R8Ix +GenU0.menu.pnum.GENERIC_U073R8IX.upload.maximum_size=65536 +GenU0.menu.pnum.GENERIC_U073R8IX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U073R8IX.build.board=GENERIC_U073R8IX +GenU0.menu.pnum.GENERIC_U073R8IX.build.product_line=STM32U073xx +GenU0.menu.pnum.GENERIC_U073R8IX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U073R8IX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U073.svd + +# Generic U073R8Tx +GenU0.menu.pnum.GENERIC_U073R8TX=Generic U073R8Tx +GenU0.menu.pnum.GENERIC_U073R8TX.upload.maximum_size=65536 +GenU0.menu.pnum.GENERIC_U073R8TX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U073R8TX.build.board=GENERIC_U073R8TX +GenU0.menu.pnum.GENERIC_U073R8TX.build.product_line=STM32U073xx +GenU0.menu.pnum.GENERIC_U073R8TX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U073R8TX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U073.svd + +# Generic U073RBIx +GenU0.menu.pnum.GENERIC_U073RBIX=Generic U073RBIx +GenU0.menu.pnum.GENERIC_U073RBIX.upload.maximum_size=131072 +GenU0.menu.pnum.GENERIC_U073RBIX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U073RBIX.build.board=GENERIC_U073RBIX +GenU0.menu.pnum.GENERIC_U073RBIX.build.product_line=STM32U073xx +GenU0.menu.pnum.GENERIC_U073RBIX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U073RBIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U073.svd + +# Generic U073RBTx +GenU0.menu.pnum.GENERIC_U073RBTX=Generic U073RBTx +GenU0.menu.pnum.GENERIC_U073RBTX.upload.maximum_size=131072 +GenU0.menu.pnum.GENERIC_U073RBTX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U073RBTX.build.board=GENERIC_U073RBTX +GenU0.menu.pnum.GENERIC_U073RBTX.build.product_line=STM32U073xx +GenU0.menu.pnum.GENERIC_U073RBTX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U073RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U073.svd + +# Generic U073RCIx +GenU0.menu.pnum.GENERIC_U073RCIX=Generic U073RCIx +GenU0.menu.pnum.GENERIC_U073RCIX.upload.maximum_size=262144 +GenU0.menu.pnum.GENERIC_U073RCIX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U073RCIX.build.board=GENERIC_U073RCIX +GenU0.menu.pnum.GENERIC_U073RCIX.build.product_line=STM32U073xx +GenU0.menu.pnum.GENERIC_U073RCIX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U073RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U073.svd + +# Generic U073RCTx +GenU0.menu.pnum.GENERIC_U073RCTX=Generic U073RCTx +GenU0.menu.pnum.GENERIC_U073RCTX.upload.maximum_size=262144 +GenU0.menu.pnum.GENERIC_U073RCTX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U073RCTX.build.board=GENERIC_U073RCTX +GenU0.menu.pnum.GENERIC_U073RCTX.build.product_line=STM32U073xx +GenU0.menu.pnum.GENERIC_U073RCTX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U073RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U073.svd + +# Generic U083RCIx +GenU0.menu.pnum.GENERIC_U083RCIX=Generic U083RCIx +GenU0.menu.pnum.GENERIC_U083RCIX.upload.maximum_size=262144 +GenU0.menu.pnum.GENERIC_U083RCIX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U083RCIX.build.board=GENERIC_U083RCIX +GenU0.menu.pnum.GENERIC_U083RCIX.build.product_line=STM32U083xx +GenU0.menu.pnum.GENERIC_U083RCIX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U083RCIX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U083.svd + +# Generic U083RCTx +GenU0.menu.pnum.GENERIC_U083RCTX=Generic U083RCTx +GenU0.menu.pnum.GENERIC_U083RCTX.upload.maximum_size=262144 +GenU0.menu.pnum.GENERIC_U083RCTX.upload.maximum_data_size=40960 +GenU0.menu.pnum.GENERIC_U083RCTX.build.board=GENERIC_U083RCTX +GenU0.menu.pnum.GENERIC_U083RCTX.build.product_line=STM32U083xx +GenU0.menu.pnum.GENERIC_U083RCTX.build.variant=STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T) +GenU0.menu.pnum.GENERIC_U083RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U0xx/STM32U083.svd + +# Upload menu +GenU0.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) +GenU0.menu.upload_method.swdMethod.upload.protocol=swd +GenU0.menu.upload_method.swdMethod.upload.options= +GenU0.menu.upload_method.swdMethod.upload.tool=stm32CubeProg + +GenU0.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenU0.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenU0.menu.upload_method.jlinkMethod.upload.options= +GenU0.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + +GenU0.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) +GenU0.menu.upload_method.serialMethod.upload.protocol=serial +GenU0.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} +GenU0.menu.upload_method.serialMethod.upload.tool=stm32CubeProg + +GenU0.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) +GenU0.menu.upload_method.dfuMethod.upload.protocol=dfu +GenU0.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} +GenU0.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg + +#GenU0.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +#GenU0.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +#GenU0.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +#GenU0.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +#GenU0.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +#GenU0.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic U5 GenU5.name=Generic STM32U5 series @@ -11624,7 +12123,7 @@ GenU5.build.series=STM32U5xx GenU5.build.flash_offset=0x0 GenU5.upload.maximum_size=0 GenU5.upload.maximum_data_size=0 -GenU5.debug.server.openocd.scripts.2=target/stm32u5x.cfg +GenU5.openocd.target=stm32u5x GenU5.vid.0=0x0483 GenU5.pid.0=0x5740 @@ -11724,6 +12223,11 @@ GenU5.menu.upload_method.swdMethod.upload.protocol=swd GenU5.menu.upload_method.swdMethod.upload.options= GenU5.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenU5.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenU5.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenU5.menu.upload_method.jlinkMethod.upload.options= +GenU5.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenU5.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenU5.menu.upload_method.serialMethod.upload.protocol=serial GenU5.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -11734,6 +12238,14 @@ GenU5.menu.upload_method.dfuMethod.upload.protocol=dfu GenU5.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenU5.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenU5.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenU5.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenU5.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenU5.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenU5.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenU5.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic WB GenWB.name=Generic STM32WB series @@ -11748,7 +12260,7 @@ GenWB.build.series=STM32WBxx GenWB.build.flash_offset=0x0 GenWB.upload.maximum_size=0 GenWB.upload.maximum_data_size=0 -GenWB.debug.server.openocd.scripts.2=target/stm32wbx.cfg +GenWB.openocd.target=stm32wbx GenWB.vid.0=0x0483 GenWB.pid.0=0x5740 @@ -11830,6 +12342,11 @@ GenWB.menu.upload_method.swdMethod.upload.protocol=swd GenWB.menu.upload_method.swdMethod.upload.options= GenWB.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenWB.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenWB.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenWB.menu.upload_method.jlinkMethod.upload.options= +GenWB.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenWB.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWB.menu.upload_method.serialMethod.upload.protocol=serial GenWB.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -11840,6 +12357,14 @@ GenWB.menu.upload_method.dfuMethod.upload.protocol=dfu GenWB.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenWB.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenWB.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenWB.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenWB.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenWB.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenWB.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenWB.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic WBA GenWBA.name=Generic STM32WBA series @@ -11854,7 +12379,7 @@ GenWBA.build.series=STM32WBAxx GenWBA.build.flash_offset=0x0 GenWBA.upload.maximum_size=0 GenWBA.upload.maximum_data_size=0 -GenWBA.debug.server.openocd.scripts.2=target/stm32wbax.cfg +GenWBA.openocd.target=stm32wbax # Generic WBA55CEUx GenWBA.menu.pnum.GENERIC_WBA55CEUX=Generic WBA55CEUx @@ -11880,11 +12405,24 @@ GenWBA.menu.upload_method.swdMethod.upload.protocol=swd GenWBA.menu.upload_method.swdMethod.upload.options= GenWBA.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenWBA.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenWBA.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenWBA.menu.upload_method.jlinkMethod.upload.options= +GenWBA.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenWBA.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWBA.menu.upload_method.serialMethod.upload.protocol=serial GenWBA.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} GenWBA.menu.upload_method.serialMethod.upload.tool=stm32CubeProg +GenWBA.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenWBA.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenWBA.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenWBA.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenWBA.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenWBA.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Generic WL GenWL.name=Generic STM32WL series @@ -11899,7 +12437,7 @@ GenWL.build.series=STM32WLxx GenWL.build.flash_offset=0x0 GenWL.upload.maximum_size=0 GenWL.upload.maximum_data_size=0 -GenWL.debug.server.openocd.scripts.2=target/stm32wlx.cfg +GenWL.openocd.target=stm32wlx # Generic WL54CCUx GenWL.menu.pnum.GENERIC_WL54CCUX=Generic WL54CCUx @@ -12051,6 +12589,11 @@ GenWL.menu.upload_method.swdMethod.upload.protocol=swd GenWL.menu.upload_method.swdMethod.upload.options= GenWL.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenWL.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenWL.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenWL.menu.upload_method.jlinkMethod.upload.options= +GenWL.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenWL.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenWL.menu.upload_method.serialMethod.upload.protocol=serial GenWL.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12061,6 +12604,14 @@ GenWL.menu.upload_method.dfuMethod.upload.protocol=dfu GenWL.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +GenWL.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenWL.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenWL.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenWL.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenWL.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenWL.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # 3D printer boards @@ -12088,7 +12639,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.ARMED_V1.build.product_line=STM32F407xx 3dprinter.menu.pnum.ARMED_V1.build.variant=STM32F4xx/F407V(E-G)T_F417V(E-G)T 3dprinter.menu.pnum.ARMED_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.ARMED_V1.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.ARMED_V1.openocd.target=stm32f4x 3dprinter.menu.pnum.ARMED_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F407.svd # Big Tree Tech EBB42_V1_1 board @@ -12101,7 +12652,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.EBB42_V1_1.build.product_line=STM32G0B1xx 3dprinter.menu.pnum.EBB42_V1_1.build.variant=STM32G0xx/G0B1C(B-C-E)(T-U)_G0C1C(C-E)(T-U) 3dprinter.menu.pnum.EBB42_V1_1.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -3dprinter.menu.pnum.EBB42_V1_1.debug.server.openocd.scripts.2=target/stm32g0x.cfg +3dprinter.menu.pnum.EBB42_V1_1.openocd.target=stm32g0x 3dprinter.menu.pnum.EBB42_V1_1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32G0xx/STM32G0B1.svd # REMRAM_V1 board @@ -12116,7 +12667,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.REMRAM_V1.build.product_line=STM32F765xx 3dprinter.menu.pnum.REMRAM_V1.build.variant=STM32F7xx/F765V(G-I)(H-T)_F767V(G-I)(H-T)_F777VI(H-T) 3dprinter.menu.pnum.REMRAM_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.REMRAM_V1.debug.server.openocd.scripts.2=target/stm32f7x.cfg +3dprinter.menu.pnum.REMRAM_V1.openocd.target=stm32f7x 3dprinter.menu.pnum.REMRAM_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F765.svd # RUMBA32 board @@ -12131,7 +12682,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.RUMBA32.build.product_line=STM32F446xx 3dprinter.menu.pnum.RUMBA32.build.variant=STM32F4xx/F446V(C-E)T 3dprinter.menu.pnum.RUMBA32.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.RUMBA32.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.RUMBA32.openocd.target=stm32f4x 3dprinter.menu.pnum.RUMBA32.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F446.svd # STEVAL-3DP001V1 board @@ -12146,7 +12697,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.ST3DP001_EVAL.build.product_line=STM32F401xE 3dprinter.menu.pnum.ST3DP001_EVAL.build.variant=STM32F4xx/F401V(B-C-D-E)T 3dprinter.menu.pnum.ST3DP001_EVAL.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.ST3DP001_EVAL.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.ST3DP001_EVAL.openocd.target=stm32f4x 3dprinter.menu.pnum.ST3DP001_EVAL.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F401.svd # PRNTR_V1 board @@ -12161,7 +12712,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.PRNTR_V1.build.product_line=STM32F407xx 3dprinter.menu.pnum.PRNTR_V1.build.variant=STM32F4xx/F407V(E-G)T_F417V(E-G)T 3dprinter.menu.pnum.PRNTR_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.PRNTR_V1.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.PRNTR_V1.openocd.target=stm32f4x 3dprinter.menu.pnum.PRNTR_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F407.svd # PRNTR_V2 board @@ -12178,7 +12729,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.PRNTR_V2.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS 3dprinter.menu.pnum.PRNTR_V2.build.flash_offset=0x8000 3dprinter.menu.pnum.PRNTR_V2.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -3dprinter.menu.pnum.PRNTR_V2.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.PRNTR_V2.openocd.target=stm32f4x 3dprinter.menu.pnum.PRNTR_V2.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F407.svd # EEXTR_F030_V1 board @@ -12191,7 +12742,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.EEXTR_F030_V1.build.product_line=STM32F030x8 3dprinter.menu.pnum.EEXTR_F030_V1.build.variant=STM32F0xx/F030C8T 3dprinter.menu.pnum.EEXTR_F030_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.EEXTR_F030_V1.debug.server.openocd.scripts.2=target/stm32f0x.cfg +3dprinter.menu.pnum.EEXTR_F030_V1.openocd.target=stm32f0x 3dprinter.menu.pnum.EEXTR_F030_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x0.svd # MALYANM200_F103CB board @@ -12207,7 +12758,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.MALYANM200_F103CB.build.startup_file=-DCUSTOM_STARTUP_FILE 3dprinter.menu.pnum.MALYANM200_F103CB.build.flash_offset=0x2000 3dprinter.menu.pnum.MALYANM200_F103CB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -3dprinter.menu.pnum.MALYANM200_F103CB.debug.server.openocd.scripts.2=target/stm32f1x.cfg +3dprinter.menu.pnum.MALYANM200_F103CB.openocd.target=stm32f1x 3dprinter.menu.pnum.MALYANM200_F103CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd # MALYANM200_F070CB board @@ -12224,7 +12775,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.MALYANM200_F070CB.build.ldscript=MALYANMx00_F070CB.ld 3dprinter.menu.pnum.MALYANM200_F070CB.build.flash_offset=0x2000 3dprinter.menu.pnum.MALYANM200_F070CB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -3dprinter.menu.pnum.MALYANM200_F070CB.debug.server.openocd.scripts.2=target/stm32f0x.cfg +3dprinter.menu.pnum.MALYANM200_F070CB.openocd.target=stm32f0x 3dprinter.menu.pnum.MALYANM200_F070CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x0.svd # MALYANM300_F070CB board @@ -12241,7 +12792,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.MALYANM200_F070CB.build.ldscript=MALYANMx00_F070CB.ld 3dprinter.menu.pnum.MALYANM300_F070CB.build.flash_offset=0x2000 3dprinter.menu.pnum.MALYANM300_F070CB.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -3dprinter.menu.pnum.MALYANM300_F070CB.debug.server.openocd.scripts.2=target/stm32f0x.cfg +3dprinter.menu.pnum.MALYANM300_F070CB.openocd.target=stm32f0x 3dprinter.menu.pnum.MALYANM300_F070CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x0.svd # VAkE v1.0 @@ -12256,7 +12807,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.VAKE_V1.build.product_line=STM32F446xx 3dprinter.menu.pnum.VAKE_V1.build.variant=STM32F4xx/F446V(C-E)T 3dprinter.menu.pnum.VAKE_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -3dprinter.menu.pnum.VAKE_V1.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.VAKE_V1.openocd.target=stm32f4x 3dprinter.menu.pnum.VAKE_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F446.svd # FYSETC_S6 board @@ -12273,7 +12824,7 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.pnum.FYSETC_S6.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS 3dprinter.menu.pnum.FYSETC_S6.build.flash_offset=0x10000 3dprinter.menu.pnum.FYSETC_S6.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -3dprinter.menu.pnum.FYSETC_S6.debug.server.openocd.scripts.2=target/stm32f4x.cfg +3dprinter.menu.pnum.FYSETC_S6.openocd.target=stm32f4x 3dprinter.menu.pnum.FYSETC_S6.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F446.svd # Upload menu @@ -12282,6 +12833,11 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.upload_method.swdMethod.upload.options= 3dprinter.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +3dprinter.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +3dprinter.menu.upload_method.jlinkMethod.upload.protocol=jlink +3dprinter.menu.upload_method.jlinkMethod.upload.options= +3dprinter.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + 3dprinter.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) 3dprinter.menu.upload_method.serialMethod.upload.protocol=serial 3dprinter.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12292,6 +12848,14 @@ GenWL.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg 3dprinter.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} 3dprinter.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +3dprinter.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +3dprinter.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +3dprinter.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +3dprinter.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +3dprinter.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +3dprinter.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Blues boards @@ -12304,7 +12868,6 @@ Blues.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSer Blues.build.flash_offset=0x0 Blues.upload.maximum_size=0 Blues.upload.maximum_data_size=0 -Blues.vid.0=0x30A4 # Swan R5 board Blues.menu.pnum.SWAN_R5=Swan R5 @@ -12318,8 +12881,9 @@ Blues.menu.pnum.SWAN_R5.build.series=STM32L4xx Blues.menu.pnum.SWAN_R5.build.product_line=STM32L4R5xx Blues.menu.pnum.SWAN_R5.build.variant=STM32L4xx/L4R5Z(G-I)Y_L4R9Z(G-I)Y_L4S5ZIY_L4S9ZIY Blues.menu.pnum.SWAN_R5.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS +Blues.menu.pnum.SWAN_R5.vid.0=0x30A4 Blues.menu.pnum.SWAN_R5.pid.0=0x0002 -Blues.menu.pnum.SWAN_R5.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Blues.menu.pnum.SWAN_R5.openocd.target=stm32l4x Blues.menu.pnum.SWAN_R5.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4R5.svd # Cygnet board @@ -12334,8 +12898,9 @@ Blues.menu.pnum.CYGNET.build.series=STM32L4xx Blues.menu.pnum.CYGNET.build.product_line=STM32L433xx Blues.menu.pnum.CYGNET.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U) Blues.menu.pnum.CYGNET.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Blues.menu.pnum.CYGNET.build.pid=0x0003 -Blues.menu.pnum.CYGNET.debug.server.openocd.scripts.2=target/stm32l4x.cfg +Blues.menu.pnum.CYGNET.vid.0=0x30A4 +Blues.menu.pnum.CYGNET.pid.0=0x0003 +Blues.menu.pnum.CYGNET.openocd.target=stm32l4x Blues.menu.pnum.CYGNET.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L4xx/STM32L4x3.svd # Upload menu @@ -12344,6 +12909,11 @@ Blues.menu.upload_method.swdMethod.upload.protocol=swd Blues.menu.upload_method.swdMethod.upload.options= Blues.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Blues.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Blues.menu.upload_method.jlinkMethod.upload.protocol=jlink +Blues.menu.upload_method.jlinkMethod.upload.options= +Blues.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Blues.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Blues.menu.upload_method.serialMethod.upload.protocol=serial Blues.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12354,6 +12924,14 @@ Blues.menu.upload_method.dfuMethod.upload.protocol=dfu Blues.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Blues.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Blues.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Blues.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Blues.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Blues.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Blues.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Blues.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Elecgator boards @@ -12381,7 +12959,7 @@ Elecgator.menu.pnum.ETHERCAT_DUINO.build.series=STM32F7xx Elecgator.menu.pnum.ETHERCAT_DUINO.build.product_line=STM32F746xx Elecgator.menu.pnum.ETHERCAT_DUINO.build.variant=STM32F7xx/F745Z(E-G)T_F746Z(E-G)(T-Y)_F750Z8T_F756ZG(T-Y) Elecgator.menu.pnum.ETHERCAT_DUINO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Elecgator.menu.pnum.ETHERCAT_DUINO.debug.server.openocd.scripts.2=target/stm32f7x.cfg +Elecgator.menu.pnum.ETHERCAT_DUINO.openocd.target=stm32f7x Elecgator.menu.pnum.ETHERCAT_DUINO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F746.svd # Upload menu @@ -12390,11 +12968,24 @@ Elecgator.menu.upload_method.swdMethod.upload.protocol=swd Elecgator.menu.upload_method.swdMethod.upload.options= Elecgator.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Elecgator.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Elecgator.menu.upload_method.jlinkMethod.upload.protocol=jlink +Elecgator.menu.upload_method.jlinkMethod.upload.options= +Elecgator.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Elecgator.menu.upload_method.dfuMethod=STM32CubeProgrammer (DFU) Elecgator.menu.upload_method.dfuMethod.upload.protocol=dfu Elecgator.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Elecgator.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Elecgator.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Elecgator.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Elecgator.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Elecgator.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Elecgator.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Elecgator.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Electronic Speed Controller boards @@ -12420,7 +13011,7 @@ ESC_board.menu.pnum.WRAITH32_V1.build.series=STM32F0xx ESC_board.menu.pnum.WRAITH32_V1.build.product_line=STM32F051x8 ESC_board.menu.pnum.WRAITH32_V1.build.variant=STM32F0xx/F051K(6-8)U ESC_board.menu.pnum.WRAITH32_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -ESC_board.menu.pnum.WRAITH32_V1.debug.server.openocd.scripts.2=target/stm32f0x.cfg +ESC_board.menu.pnum.WRAITH32_V1.openocd.target=stm32f0x ESC_board.menu.pnum.WRAITH32_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x1.svd # STORM32_V1_RC board @@ -12433,7 +13024,7 @@ ESC_board.menu.pnum.STORM32_V1_31_RC.build.series=STM32F1xx ESC_board.menu.pnum.STORM32_V1_31_RC.build.product_line=STM32F103xE ESC_board.menu.pnum.STORM32_V1_31_RC.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS ESC_board.menu.pnum.STORM32_V1_31_RC.build.variant=STM32F1xx/F103R(C-D-E)T -ESC_board.menu.pnum.STORM32_V1_31_RC.debug.server.openocd.scripts.2=target/stm32f1x.cfg +ESC_board.menu.pnum.STORM32_V1_31_RC.openocd.target=stm32f1x ESC_board.menu.pnum.STORM32_V1_31_RC.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd # Upload menu @@ -12442,6 +13033,11 @@ ESC_board.menu.upload_method.swdMethod.upload.protocol=swd ESC_board.menu.upload_method.swdMethod.upload.options= ESC_board.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +ESC_board.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +ESC_board.menu.upload_method.jlinkMethod.upload.protocol=jlink +ESC_board.menu.upload_method.jlinkMethod.upload.options= +ESC_board.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + ESC_board.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) ESC_board.menu.upload_method.serialMethod.upload.protocol=serial ESC_board.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12452,6 +13048,14 @@ ESC_board.menu.upload_method.dfuMethod.upload.protocol=dfu ESC_board.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} ESC_board.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +ESC_board.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +ESC_board.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +ESC_board.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +ESC_board.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +ESC_board.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +ESC_board.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Garatronic-McHobby STM32 boards @@ -12477,7 +13081,7 @@ Garatronic.menu.pnum.PYBSTICK26_DUINO.build.series=STM32F0xx Garatronic.menu.pnum.PYBSTICK26_DUINO.build.product_line=STM32F072xB Garatronic.menu.pnum.PYBSTICK26_DUINO.build.variant=STM32F0xx/F072R8T_F072RB(H-I-T) Garatronic.menu.pnum.PYBSTICK26_DUINO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -Garatronic.menu.pnum.PYBSTICK26_DUINO.debug.server.openocd.scripts.2=target/stm32f0x.cfg +Garatronic.menu.pnum.PYBSTICK26_DUINO.openocd.target=stm32f0x Garatronic.menu.pnum.PYBSTICK26_DUINO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd # PYBSTICK26(LITE) board with F401CE @@ -12492,7 +13096,7 @@ Garatronic.menu.pnum.PYBSTICK26_LITE.build.variant=STM32F4xx/F401CC(F-U-Y)_F401C Garatronic.menu.pnum.PYBSTICK26_LITE.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Garatronic.menu.pnum.PYBSTICK26_LITE.build.fpu=-mfpu=fpv4-sp-d16 Garatronic.menu.pnum.PYBSTICK26_LITE.build.float-abi=-mfloat-abi=hard -Garatronic.menu.pnum.PYBSTICK26_LITE.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Garatronic.menu.pnum.PYBSTICK26_LITE.openocd.target=stm32f4x Garatronic.menu.pnum.PYBSTICK26_LITE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F401.svd # PYBSTICK26(STD/Programmez!) board with F411RE @@ -12507,7 +13111,7 @@ Garatronic.menu.pnum.PYBSTICK26_STD.build.variant=STM32F4xx/F411R(C-E)T Garatronic.menu.pnum.PYBSTICK26_STD.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Garatronic.menu.pnum.PYBSTICK26_STD.build.fpu=-mfpu=fpv4-sp-d16 Garatronic.menu.pnum.PYBSTICK26_STD.build.float-abi=-mfloat-abi=hard -Garatronic.menu.pnum.PYBSTICK26_STD.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Garatronic.menu.pnum.PYBSTICK26_STD.openocd.target=stm32f4x Garatronic.menu.pnum.PYBSTICK26_STD.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F411.svd # PYBSTICK26(PRO) board with F412RE @@ -12522,7 +13126,7 @@ Garatronic.menu.pnum.PYBSTICK26_PRO.build.variant=STM32F4xx/F412R(E-G)(T-Y)x(P) Garatronic.menu.pnum.PYBSTICK26_PRO.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Garatronic.menu.pnum.PYBSTICK26_PRO.build.fpu=-mfpu=fpv4-sp-d16 Garatronic.menu.pnum.PYBSTICK26_PRO.build.float-abi=-mfloat-abi=hard -Garatronic.menu.pnum.PYBSTICK26_PRO.debug.server.openocd.scripts.2=target/stm32f4x.cfg +Garatronic.menu.pnum.PYBSTICK26_PRO.openocd.target=stm32f4x Garatronic.menu.pnum.PYBSTICK26_PRO.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F412.svd # PYBSTICK26 boards upload method @@ -12558,7 +13162,7 @@ GenFlight.menu.pnum.AFROFLIGHT_F103CB.build.variant=STM32F1xx/F103C8T_F103CB(T-U GenFlight.menu.pnum.AFROFLIGHT_F103CB.build.variant_h=variant_AFROFLIGHT_F103CB_XX.h GenFlight.menu.pnum.AFROFLIGHT_F103CB.upload.vid.0=0x1eaf GenFlight.menu.pnum.AFROFLIGHT_F103CB.upload.pid.0=0x0003 -GenFlight.menu.pnum.AFROFLIGHT_F103CB.debug.server.openocd.scripts.2=target/stm32f1x.cfg +GenFlight.menu.pnum.AFROFLIGHT_F103CB.openocd.target=stm32f1x GenFlight.menu.pnum.AFROFLIGHT_F103CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M=Afro Flight Rev5 (12MHz) @@ -12572,7 +13176,7 @@ GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.build.variant=STM32F1xx/F103C8T_F103CB GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.build.variant_h=variant_AFROFLIGHT_F103CB_XX.h GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.upload.vid.0=0x1eaf GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.upload.pid.0=0x0003 -GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.debug.server.openocd.scripts.2=target/stm32f1x.cfg +GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.openocd.target=stm32f1x GenFlight.menu.pnum.AFROFLIGHT_F103CB_12M.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F1xx/STM32F103.svd # Sparky_V1 board @@ -12587,7 +13191,7 @@ GenFlight.menu.pnum.Sparky_V1.build.fpu=-mfpu=fpv4-sp-d16 GenFlight.menu.pnum.Sparky_V1.build.float-abi=-mfloat-abi=hard GenFlight.menu.pnum.Sparky_V1.build.variant=STM32F3xx/F303C(B-C)T GenFlight.menu.pnum.Sparky_V1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -GenFlight.menu.pnum.Sparky_V1.debug.server.openocd.scripts.2=target/stm32f3x.cfg +GenFlight.menu.pnum.Sparky_V1.openocd.target=stm32f3x GenFlight.menu.pnum.Sparky_V1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F3xx/STM32F303.svd # Upload menu @@ -12596,6 +13200,11 @@ GenFlight.menu.upload_method.swdMethod.upload.protocol=swd GenFlight.menu.upload_method.swdMethod.upload.options= GenFlight.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +GenFlight.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +GenFlight.menu.upload_method.jlinkMethod.upload.protocol=jlink +GenFlight.menu.upload_method.jlinkMethod.upload.options= +GenFlight.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + GenFlight.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) GenFlight.menu.upload_method.serialMethod.upload.protocol=serial GenFlight.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12630,6 +13239,14 @@ GenFlight.menu.upload_method.dfuoMethod.upload.altID=1 GenFlight.menu.upload_method.dfuoMethod.build.flash_offset=0x5000 GenFlight.menu.upload_method.dfuoMethod.build.bootloader_flags=-DBL_LEGACY_LEAF +GenFlight.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +GenFlight.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +GenFlight.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +GenFlight.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +GenFlight.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +GenFlight.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # IoT continuum Boards @@ -12655,7 +13272,7 @@ IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.series=STM32U5xx IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.product_line=STM32U585xx IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.variant=STM32U5xx/U575C(G-I)(T-U)_U585CI(T-U) IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.debug.server.openocd.scripts.2=target/stm32u5x.cfg +IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.openocd.target=stm32u5x IotContinuum.menu.pnum.DEVKIT_IOT_CONTINUUM.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32U5xx/STM32U585.svd # Upload menu @@ -12664,6 +13281,11 @@ IotContinuum.menu.upload_method.swdMethod.upload.protocol=swd IotContinuum.menu.upload_method.swdMethod.upload.options= IotContinuum.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +IotContinuum.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +IotContinuum.menu.upload_method.jlinkMethod.upload.protocol=jlink +IotContinuum.menu.upload_method.jlinkMethod.upload.options= +IotContinuum.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + IotContinuum.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) IotContinuum.menu.upload_method.serialMethod.upload.protocol=serial IotContinuum.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12674,6 +13296,14 @@ IotContinuum.menu.upload_method.dfuMethod.upload.protocol=dfu IotContinuum.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} IotContinuum.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +IotContinuum.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +IotContinuum.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +IotContinuum.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +IotContinuum.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +IotContinuum.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +IotContinuum.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # LoRa boards @@ -12699,7 +13329,7 @@ LoRa.menu.pnum.ACSIP_S76S.build.product_line=STM32L073xx LoRa.menu.pnum.ACSIP_S76S.build.variant=STM32L0xx/L072R(B-Z)T_L073R(B-Z)T_L083R(B-Z)T LoRa.menu.pnum.ACSIP_S76S.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.ACSIP_S76S.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -LoRa.menu.pnum.ACSIP_S76S.debug.server.openocd.scripts.2=target/stm32l0x.cfg +LoRa.menu.pnum.ACSIP_S76S.openocd.target=stm32l0 LoRa.menu.pnum.ACSIP_S76S.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L0x3.svd # Generic node SE by The Things Industries @@ -12713,7 +13343,7 @@ LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.product_line=STM32WL55xx LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.variant_h=variant_GENERIC_NODE_SE_TTI.h LoRa.menu.pnum.GENERIC_NODE_SE_TTI.build.st_extra_flags=-D{build.product_line} -DUSE_CM4_STARTUP_FILE {build.xSerial} -LoRa.menu.pnum.GENERIC_NODE_SE_TTI.debug.server.openocd.scripts.2=target/stm32wlx.cfg +LoRa.menu.pnum.GENERIC_NODE_SE_TTI.openocd.target=stm32wlx LoRa.menu.pnum.GENERIC_NODE_SE_TTI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WL5x_CM4.svd # LORA_E5_MINI board @@ -12727,7 +13357,7 @@ LoRa.menu.pnum.LORA_E5_MINI.build.product_line=STM32WLE5xx LoRa.menu.pnum.LORA_E5_MINI.build.variant=STM32WLxx/WL54JCI_WL55JCI_WLE4J(8-B-C)I_WLE5J(8-B-C)I LoRa.menu.pnum.LORA_E5_MINI.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.LORA_E5_MINI.build.variant_h=variant_LORA_E5_MINI.h -LoRa.menu.pnum.LORA_E5_MINI.debug.server.openocd.scripts.2=target/stm32wlx.cfg +LoRa.menu.pnum.LORA_E5_MINI.openocd.target=stm32wlx LoRa.menu.pnum.LORA_E5_MINI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd # RAK3172 module @@ -12740,7 +13370,7 @@ LoRa.menu.pnum.RAK3172_MODULE.build.series=STM32WLxx LoRa.menu.pnum.RAK3172_MODULE.build.product_line=STM32WLE5xx LoRa.menu.pnum.RAK3172_MODULE.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U LoRa.menu.pnum.RAK3172_MODULE.build.variant_h=variant_RAK3172_MODULE.h -LoRa.menu.pnum.RAK3172_MODULE.debug.server.openocd.scripts.2=target/stm32wlx.cfg +LoRa.menu.pnum.RAK3172_MODULE.openocd.target=stm32wlx LoRa.menu.pnum.RAK3172_MODULE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd # RAK3172T module @@ -12753,7 +13383,7 @@ LoRa.menu.pnum.RAK3172T_MODULE.build.series=STM32WLxx LoRa.menu.pnum.RAK3172T_MODULE.build.product_line=STM32WLE5xx LoRa.menu.pnum.RAK3172T_MODULE.build.variant=STM32WLxx/WL54CCU_WL55CCU_WLE4C(8-B-C)U_WLE5C(8-B-C)U LoRa.menu.pnum.RAK3172T_MODULE.build.variant_h=variant_RAK3172_MODULE.h -LoRa.menu.pnum.RAK3172T_MODULE.debug.server.openocd.scripts.2=target/stm32wlx.cfg +LoRa.menu.pnum.RAK3172T_MODULE.openocd.target=stm32wlx LoRa.menu.pnum.RAK3172T_MODULE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd # RAK811_TRACKER board @@ -12766,7 +13396,7 @@ LoRa.menu.pnum.RAK811_TRACKER.build.series=STM32L1xx LoRa.menu.pnum.RAK811_TRACKER.build.product_line=STM32L151xB LoRa.menu.pnum.RAK811_TRACKER.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) LoRa.menu.pnum.RAK811_TRACKER.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -LoRa.menu.pnum.RAK811_TRACKER.debug.server.openocd.scripts.2=target/stm32l1x.cfg +LoRa.menu.pnum.RAK811_TRACKER.openocd.target=stm32l1 LoRa.menu.pnum.RAK811_TRACKER.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L1xx/STM32L151.svd LoRa.menu.pnum.RAK811_TRACKERA=RAK811 LoRa Tracker (32kb RAM) @@ -12779,7 +13409,7 @@ LoRa.menu.pnum.RAK811_TRACKERA.build.product_line=STM32L151xBA LoRa.menu.pnum.RAK811_TRACKERA.build.variant=STM32L1xx/L100C6Ux(A)_L151C(6-8-B)(T-U)x(A)_L152C(6-8-B)(T-U)x(A) LoRa.menu.pnum.RAK811_TRACKERA.build.variant_h=variant_RAK811_TRACKER.h LoRa.menu.pnum.RAK811_TRACKERA.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS -LoRa.menu.pnum.RAK811_TRACKERA.debug.server.openocd.scripts.2=target/stm32l1x.cfg +LoRa.menu.pnum.RAK811_TRACKERA.openocd.target=stm32l1 # RHF76_052 board LoRa.menu.pnum.RHF76_052=RHF76 052 @@ -12792,7 +13422,7 @@ LoRa.menu.pnum.RHF76_052.build.product_line=STM32L051xx LoRa.menu.pnum.RHF76_052.build.variant=STM32L0xx/L051C(6-8)(T-U) LoRa.menu.pnum.RHF76_052.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.RHF76_052.build.st_extra_flags=-D{build.product_line} {build.enable_usb} {build.xSerial} -D__CORTEX_SC=0 -LoRa.menu.pnum.RHF76_052.debug.server.openocd.scripts.2=target/stm32l0x.cfg +LoRa.menu.pnum.RHF76_052.openocd.target=stm32l0 LoRa.menu.pnum.RHF76_052.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32L0xx/STM32L0x1.svd # ELEKTOR_F072C8 @@ -12807,7 +13437,7 @@ LoRa.menu.pnum.ELEKTOR_F072C8.build.variant=STM32F0xx/F072C8(T-U)_F072CB(T-U-Y) LoRa.menu.pnum.ELEKTOR_F072C8.build.variant_h=variant_ELEKTOR_F072Cx.h LoRa.menu.pnum.ELEKTOR_F072C8.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.ELEKTOR_F072C8.build.st_extra_flags=-D{build.product_line} {build.xSerial} -LoRa.menu.pnum.ELEKTOR_F072C8.debug.server.openocd.scripts.2=target/stm32f0x.cfg +LoRa.menu.pnum.ELEKTOR_F072C8.openocd.target=stm32f0x LoRa.menu.pnum.ELEKTOR_F072C8.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd # ELEKTOR_F072CB @@ -12822,7 +13452,7 @@ LoRa.menu.pnum.ELEKTOR_F072CB.build.variant=STM32F0xx/F072C8(T-U)_F072CB(T-U-Y) LoRa.menu.pnum.ELEKTOR_F072CB.build.variant_h=variant_ELEKTOR_F072Cx.h LoRa.menu.pnum.ELEKTOR_F072CB.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS LoRa.menu.pnum.ELEKTOR_F072CB.build.st_extra_flags=-D{build.product_line} {build.xSerial} -LoRa.menu.pnum.ELEKTOR_F072CB.debug.server.openocd.scripts.2=target/stm32f0x.cfg +LoRa.menu.pnum.ELEKTOR_F072CB.openocd.target=stm32f0x LoRa.menu.pnum.ELEKTOR_F072CB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F0xx/STM32F0x2.svd # Upload menu @@ -12831,6 +13461,11 @@ LoRa.menu.upload_method.swdMethod.upload.protocol=swd LoRa.menu.upload_method.swdMethod.upload.options= LoRa.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +LoRa.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +LoRa.menu.upload_method.jlinkMethod.upload.protocol=jlink +LoRa.menu.upload_method.jlinkMethod.upload.options= +LoRa.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + LoRa.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) LoRa.menu.upload_method.serialMethod.upload.protocol=serial LoRa.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12841,6 +13476,14 @@ LoRa.menu.upload_method.dfuMethod.upload.protocol=dfu LoRa.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} LoRa.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +LoRa.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +LoRa.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +LoRa.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +LoRa.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +LoRa.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +LoRa.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # Midatronics boards @@ -12868,7 +13511,7 @@ Midatronics.menu.pnum.MKR_SHARKY.build.board=MKR_SHARKY Midatronics.menu.pnum.MKR_SHARKY.build.series=STM32WBxx Midatronics.menu.pnum.MKR_SHARKY.build.product_line=STM32WB55xx Midatronics.menu.pnum.MKR_SHARKY.build.variant=STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U -Midatronics.menu.pnum.MKR_SHARKY.debug.server.openocd.scripts.2=target/stm32wbx.cfg +Midatronics.menu.pnum.MKR_SHARKY.openocd.target=stm32wbx Midatronics.menu.pnum.MKR_SHARKY.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd # Upload menu @@ -12881,6 +13524,11 @@ Midatronics.menu.upload_method.swdMethod.upload.protocol=swd Midatronics.menu.upload_method.swdMethod.upload.options= Midatronics.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +Midatronics.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +Midatronics.menu.upload_method.jlinkMethod.upload.protocol=jlink +Midatronics.menu.upload_method.jlinkMethod.upload.options= +Midatronics.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + Midatronics.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) Midatronics.menu.upload_method.serialMethod.upload.protocol=serial Midatronics.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12891,6 +13539,14 @@ Midatronics.menu.upload_method.dfuMethod.upload.protocol=dfu Midatronics.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} Midatronics.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +Midatronics.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +Midatronics.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +Midatronics.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +Midatronics.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +Midatronics.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +Midatronics.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # SparkFun Boards @@ -12920,7 +13576,7 @@ SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.build.variant=STM32WBxx/WB5MMGH SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.vid.0=0x1B4F SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.pid.0=0x0034 -SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.debug.server.openocd.scripts.2=target/stm32wbx.cfg +SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.openocd.target=stm32wbx SparkFun.menu.pnum.SFE_MMPB_STM32WB5MMG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd # SparkFun MicroMod STM32F405 Board @@ -12938,7 +13594,7 @@ SparkFun.menu.pnum.MICROMOD_F405.build.variant=STM32F4xx/F405RGT_F415RGT SparkFun.menu.pnum.MICROMOD_F405.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS SparkFun.menu.pnum.MICROMOD_F405.vid.0=0x1B4F SparkFun.menu.pnum.MICROMOD_F405.pid.0=0x0029 -SparkFun.menu.pnum.MICROMOD_F405.debug.server.openocd.scripts.2=target/stm32f4x.cfg +SparkFun.menu.pnum.MICROMOD_F405.openocd.target=stm32f4x SparkFun.menu.pnum.MICROMOD_F405.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F405.svd # Upload menu @@ -12947,6 +13603,11 @@ SparkFun.menu.upload_method.swdMethod.upload.protocol=swd SparkFun.menu.upload_method.swdMethod.upload.options= SparkFun.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +SparkFun.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) +SparkFun.menu.upload_method.jlinkMethod.upload.protocol=jlink +SparkFun.menu.upload_method.jlinkMethod.upload.options= +SparkFun.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + SparkFun.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) SparkFun.menu.upload_method.serialMethod.upload.protocol=serial SparkFun.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} @@ -12957,6 +13618,14 @@ SparkFun.menu.upload_method.dfuMethod.upload.protocol=dfu SparkFun.menu.upload_method.dfuMethod.upload.options=-v {upload.vid} -p {upload.pid} SparkFun.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +SparkFun.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +SparkFun.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +SparkFun.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + +SparkFun.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +SparkFun.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +SparkFun.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + ################################################################################ # ELV Modular System boards @@ -12979,7 +13648,7 @@ ELV_Modular_System.menu.pnum.ELV_BM_TRX1.build.variant=STM32WLxx/WL54JCI_WL55JCI ELV_Modular_System.menu.pnum.ELV_BM_TRX1.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS ELV_Modular_System.menu.pnum.ELV_BM_TRX1.build.flash_offset=0x800 ELV_Modular_System.menu.pnum.ELV_BM_TRX1.build.st_extra_flags=-D{build.product_line} -DUSE_CM4_STARTUP_FILE {build.xSerial} -ELV_Modular_System.menu.pnum.ELV_BM_TRX1.debug.server.openocd.scripts.2=target/stm32wlx.cfg +ELV_Modular_System.menu.pnum.ELV_BM_TRX1.openocd.target=stm32wlx ELV_Modular_System.menu.pnum.ELV_BM_TRX1.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WLxx/STM32WLE5_CM4.svd # Upload menu @@ -12988,11 +13657,57 @@ ELV_Modular_System.menu.upload_method.swdMethod.upload.protocol=swd ELV_Modular_System.menu.upload_method.swdMethod.upload.options= ELV_Modular_System.menu.upload_method.swdMethod.upload.tool=stm32CubeProg +ELV_Modular_System.menu.upload_method.jlinkMethod=STM32CubeProgrammer (J-Link) with Bootloader +ELV_Modular_System.menu.upload_method.jlinkMethod.upload.protocol=jlink +ELV_Modular_System.menu.upload_method.jlinkMethod.upload.options= +ELV_Modular_System.menu.upload_method.jlinkMethod.upload.tool=stm32CubeProg + ELV_Modular_System.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) with Bootloader ELV_Modular_System.menu.upload_method.serialMethod.upload.protocol=serial ELV_Modular_System.menu.upload_method.serialMethod.upload.options=-c {serial.port.file} ELV_Modular_System.menu.upload_method.serialMethod.upload.tool=stm32CubeProg +################################################################################ +# STeaMi board +STeaMi.name=STeaMi Board +STeaMi.build.core=arduino +STeaMi.build.variant_h=variant_{build.board}.h +STeaMi.build.st_extra_flags=-D{build.product_line} {build.xSerial} +STeaMi.build.flash_offset=0x0 +STeaMi.upload.maximum_size=0 +STeaMi.upload.maximum_data_size=0 +STeaMi.vid.0=0x0d28 +STeaMi.pid.0=0x0204 + +STeaMi.menu.pnum.STEAM32_WB55RG=STeaMi +STeaMi.menu.pnum.STEAM32_WB55RG.node="STeaMi,DAPLINK" +STeaMi.menu.pnum.STEAM32_WB55RG.upload.maximum_size=524288 +STeaMi.menu.pnum.STEAM32_WB55RG.upload.maximum_data_size=196608 +STeaMi.menu.pnum.STEAM32_WB55RG.build.mcu=cortex-m4 +STeaMi.menu.pnum.STEAM32_WB55RG.build.fpu=-mfpu=fpv4-sp-d16 +STeaMi.menu.pnum.STEAM32_WB55RG.build.float-abi=-mfloat-abi=hard +STeaMi.menu.pnum.STEAM32_WB55RG.build.board=STEAM32_WB55RG +STeaMi.menu.pnum.STEAM32_WB55RG.build.series=STM32WBxx +STeaMi.menu.pnum.STEAM32_WB55RG.build.product_line=STM32WB55xx +STeaMi.menu.pnum.STEAM32_WB55RG.build.variant=STM32WBxx/WB55R(C-E-G)V +STeaMi.menu.pnum.STEAM32_WB55RG.debug.server.openocd.scripts.0=interface/cmsis-dap.cfg +STeaMi.menu.pnum.STEAM32_WB55RG.debug.server.openocd.scripts.1={runtime.platform.path}/debugger/select_swd.cfg +STeaMi.menu.pnum.STEAM32_WB55RG.openocd.target=stm32wbx +STeaMi.menu.pnum.STEAM32_WB55RG.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32WBxx/STM32WB55_CM4.svd + +# Upload menu +STeaMi.menu.upload_method.MassStorage=Mass Storage +STeaMi.menu.upload_method.MassStorage.upload.protocol= +STeaMi.menu.upload_method.MassStorage.upload.tool=massStorageCopy + +STeaMi.menu.upload_method.OpenOCDDapLink=OpenOCD DapLink (SWD) +STeaMi.menu.upload_method.OpenOCDDapLink.upload.protocol=cmsis-dap +STeaMi.menu.upload_method.OpenOCDDapLink.upload.tool=openocd_upload + +STeaMi.menu.upload_method.OpenOCDSTLink=OpenOCD STLink (SWD) +STeaMi.menu.upload_method.OpenOCDSTLink.upload.protocol=stlink +STeaMi.menu.upload_method.OpenOCDSTLink.upload.tool=openocd_upload + ################################################################################ # Serialx activation Nucleo_144.menu.xserial.generic=Enabled (generic 'Serial') @@ -13129,6 +13844,12 @@ GenL5.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE GenL5.menu.xserial.disabled=Disabled (no Serial support) GenL5.menu.xserial.disabled.build.xSerial= +GenU0.menu.xserial.generic=Enabled (generic 'Serial') +GenU0.menu.xserial.none=Enabled (no generic 'Serial') +GenU0.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +GenU0.menu.xserial.disabled=Disabled (no Serial support) +GenU0.menu.xserial.disabled.build.xSerial= + GenU5.menu.xserial.generic=Enabled (generic 'Serial') GenU5.menu.xserial.none=Enabled (no generic 'Serial') GenU5.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -13219,6 +13940,12 @@ ELV_Modular_System.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DH ELV_Modular_System.menu.xserial.disabled=Disabled (no Serial support) ELV_Modular_System.menu.xserial.disabled.build.xSerial= +STeaMi.menu.xserial.generic=Enabled (generic 'Serial') +STeaMi.menu.xserial.none=Enabled (no generic 'Serial') +STeaMi.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +STeaMi.menu.xserial.disabled=Disabled (no Serial support) +STeaMi.menu.xserial.disabled.build.xSerial= + # USB connectivity Nucleo_144.menu.usb.none=None Nucleo_144.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) @@ -13447,6 +14174,14 @@ GenL5.menu.xusb.HS.build.usb_speed=-DUSE_USB_HS GenL5.menu.xusb.HSFS=High Speed in Full Speed mode GenL5.menu.xusb.HSFS.build.usb_speed=-DUSE_USB_HS -DUSE_USB_HS_IN_FS +GenU0.menu.usb.none=None +GenU0.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) +GenU0.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC +GenU0.menu.usb.CDC=CDC (no generic 'Serial') +GenU0.menu.usb.CDC.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB +GenU0.menu.usb.HID=HID (keyboard and mouse) +GenU0.menu.usb.HID.build.enable_usb={build.usb_flags} -DUSBD_USE_HID_COMPOSITE + GenU5.menu.usb.none=None GenU5.menu.usb.CDCgen=CDC (generic 'Serial' supersede U(S)ART) GenU5.menu.usb.CDCgen.build.enable_usb={build.usb_flags} -DUSBD_USE_CDC @@ -13988,6 +14723,27 @@ GenL5.menu.opt.ogstd.build.flags.optimize=-Og GenL5.menu.opt.o0std=No Optimization (-O0) GenL5.menu.opt.o0std.build.flags.optimize=-O0 +GenU0.menu.opt.osstd=Smallest (-Os default) +GenU0.menu.opt.osstd.build.flags.optimize=-Os +GenU0.menu.opt.oslto=Smallest (-Os) with LTO +GenU0.menu.opt.oslto.build.flags.optimize=-Os -flto +GenU0.menu.opt.o1std=Fast (-O1) +GenU0.menu.opt.o1std.build.flags.optimize=-O1 +GenU0.menu.opt.o1lto=Fast (-O1) with LTO +GenU0.menu.opt.o1lto.build.flags.optimize=-O1 -flto +GenU0.menu.opt.o2std=Faster (-O2) +GenU0.menu.opt.o2std.build.flags.optimize=-O2 +GenU0.menu.opt.o2lto=Faster (-O2) with LTO +GenU0.menu.opt.o2lto.build.flags.optimize=-O2 -flto +GenU0.menu.opt.o3std=Fastest (-O3) +GenU0.menu.opt.o3std.build.flags.optimize=-O3 +GenU0.menu.opt.o3lto=Fastest (-O3) with LTO +GenU0.menu.opt.o3lto.build.flags.optimize=-O3 -flto +GenU0.menu.opt.ogstd=Debug (-Og) +GenU0.menu.opt.ogstd.build.flags.optimize=-Og +GenU0.menu.opt.o0std=No Optimization (-O0) +GenU0.menu.opt.o0std.build.flags.optimize=-O0 + GenU5.menu.opt.osstd=Smallest (-Os default) GenU5.menu.opt.osstd.build.flags.optimize=-Os GenU5.menu.opt.oslto=Smallest (-Os) with LTO @@ -14289,6 +15045,26 @@ ELV_Modular_System.menu.opt.ogstd.build.flags.optimize=-Og ELV_Modular_System.menu.opt.o0std=No Optimization (-O0) ELV_Modular_System.menu.opt.o0std.build.flags.optimize=-O0 +STeaMi.menu.opt.osstd=Smallest (-Os default) +STeaMi.menu.opt.oslto=Smallest (-Os) with LTO +STeaMi.menu.opt.oslto.build.flags.optimize=-Os -flto +STeaMi.menu.opt.o1std=Fast (-O1) +STeaMi.menu.opt.o1std.build.flags.optimize=-O1 +STeaMi.menu.opt.o1lto=Fast (-O1) with LTO +STeaMi.menu.opt.o1lto.build.flags.optimize=-O1 -flto +STeaMi.menu.opt.o2std=Faster (-O2) +STeaMi.menu.opt.o2std.build.flags.optimize=-O2 +STeaMi.menu.opt.o2lto=Faster (-O2) with LTO +STeaMi.menu.opt.o2lto.build.flags.optimize=-O2 -flto +STeaMi.menu.opt.o3std=Fastest (-O3) +STeaMi.menu.opt.o3std.build.flags.optimize=-O3 +STeaMi.menu.opt.o3lto=Fastest (-O3) with LTO +STeaMi.menu.opt.o3lto.build.flags.optimize=-O3 -flto +STeaMi.menu.opt.ogstd=Debug (-Og) +STeaMi.menu.opt.ogstd.build.flags.optimize=-Og +STeaMi.menu.opt.o0std=No Optimization (-O0) +STeaMi.menu.opt.o0std.build.flags.optimize=-O0 + # Debug information Nucleo_144.menu.dbg.none=None Nucleo_144.menu.dbg.enable_sym=Symbols Enabled (-g) @@ -14454,6 +15230,22 @@ GenL5.menu.dbg.enable_log.build.flags.debug= GenL5.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) GenL5.menu.dbg.enable_all.build.flags.debug=-g +GenU0.menu.dbg.none=None +GenU0.menu.dbg.enable_sym=Symbols Enabled (-g) +GenU0.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG +GenU0.menu.dbg.enable_log=Core logs Enabled +GenU0.menu.dbg.enable_log.build.flags.debug= +GenU0.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) +GenU0.menu.dbg.enable_all.build.flags.debug=-g + +GenU5.menu.dbg.none=None +GenU5.menu.dbg.enable_sym=Symbols Enabled (-g) +GenU5.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG +GenU5.menu.dbg.enable_log=Core logs Enabled +GenU5.menu.dbg.enable_log.build.flags.debug= +GenU5.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) +GenU5.menu.dbg.enable_all.build.flags.debug=-g + GenWB.menu.dbg.none=None GenWB.menu.dbg.enable_sym=Symbols Enabled (-g) GenWB.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG @@ -14566,6 +15358,14 @@ ELV_Modular_System.menu.dbg.enable_log.build.flags.debug= ELV_Modular_System.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) ELV_Modular_System.menu.dbg.enable_all.build.flags.debug=-g +STeaMi.menu.dbg.none=None +STeaMi.menu.dbg.enable_sym=Symbols Enabled (-g) +STeaMi.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG +STeaMi.menu.dbg.enable_log=Core logs Enabled +STeaMi.menu.dbg.enable_log.build.flags.debug= +STeaMi.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) +STeaMi.menu.dbg.enable_all.build.flags.debug=-g + # C Runtime Library Nucleo_144.menu.rtlib.nano=Newlib Nano (default) Nucleo_144.menu.rtlib.nanofp=Newlib Nano + Float Printf @@ -14777,6 +15577,16 @@ GenL5.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float GenL5.menu.rtlib.full=Newlib Standard GenL5.menu.rtlib.full.build.flags.ldspecs= +GenU0.menu.rtlib.nano=Newlib Nano (default) +GenU0.menu.rtlib.nanofp=Newlib Nano + Float Printf +GenU0.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +GenU0.menu.rtlib.nanofs=Newlib Nano + Float Scanf +GenU0.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +GenU0.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +GenU0.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +GenU0.menu.rtlib.full=Newlib Standard +GenU0.menu.rtlib.full.build.flags.ldspecs= + GenU5.menu.rtlib.nano=Newlib Nano (default) GenU5.menu.rtlib.nanofp=Newlib Nano + Float Printf GenU5.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float @@ -14926,3 +15736,13 @@ ELV_Modular_System.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf ELV_Modular_System.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float ELV_Modular_System.menu.rtlib.full=Newlib Standard ELV_Modular_System.menu.rtlib.full.build.flags.ldspecs= + +STeaMi.menu.rtlib.nano=Newlib Nano (default) +STeaMi.menu.rtlib.nanofp=Newlib Nano + Float Printf +STeaMi.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +STeaMi.menu.rtlib.nanofs=Newlib Nano + Float Scanf +STeaMi.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +STeaMi.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +STeaMi.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +STeaMi.menu.rtlib.full=Newlib Standard +STeaMi.menu.rtlib.full.build.flags.ldspecs= diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index 266ac7a225..660aa29fa5 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -7130,6 +7130,114 @@ target_compile_options(GENERIC_C031F6PX_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +# GENERIC_C071R8TX +# ----------------------------------------------------------------------------- + +set(GENERIC_C071R8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C071R(8-B)T") +set(GENERIC_C071R8TX_MAXSIZE 65536) +set(GENERIC_C071R8TX_MAXDATASIZE 24576) +set(GENERIC_C071R8TX_MCU cortex-m0plus) +set(GENERIC_C071R8TX_FPCONF "-") +add_library(GENERIC_C071R8TX INTERFACE) +target_compile_options(GENERIC_C071R8TX INTERFACE + "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C071R8TX_MCU} +) +target_compile_definitions(GENERIC_C071R8TX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C071R8TX" + "BOARD_NAME=\"GENERIC_C071R8TX\"" + "BOARD_ID=GENERIC_C071R8TX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C071R8TX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C071R8TX_VARIANT_PATH} +) + +target_link_options(GENERIC_C071R8TX INTERFACE + "LINKER:--default-script=${GENERIC_C071R8TX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=24576" + "SHELL: " + -mcpu=${GENERIC_C071R8TX_MCU} +) + +add_library(GENERIC_C071R8TX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C071R8TX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C071R8TX_serial_generic INTERFACE) +target_compile_options(GENERIC_C071R8TX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C071R8TX_serial_none INTERFACE) +target_compile_options(GENERIC_C071R8TX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_C071RBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_C071RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C071R(8-B)T") +set(GENERIC_C071RBTX_MAXSIZE 131072) +set(GENERIC_C071RBTX_MAXDATASIZE 24576) +set(GENERIC_C071RBTX_MCU cortex-m0plus) +set(GENERIC_C071RBTX_FPCONF "-") +add_library(GENERIC_C071RBTX INTERFACE) +target_compile_options(GENERIC_C071RBTX INTERFACE + "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_C071RBTX_MCU} +) +target_compile_definitions(GENERIC_C071RBTX INTERFACE + "STM32C0xx" + "ARDUINO_GENERIC_C071RBTX" + "BOARD_NAME=\"GENERIC_C071RBTX\"" + "BOARD_ID=GENERIC_C071RBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_C071RBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${GENERIC_C071RBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_C071RBTX INTERFACE + "LINKER:--default-script=${GENERIC_C071RBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=24576" + "SHELL: " + -mcpu=${GENERIC_C071RBTX_MCU} +) + +add_library(GENERIC_C071RBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_C071RBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_C071RBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_C071RBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_C071RBTX_serial_none INTERFACE) +target_compile_options(GENERIC_C071RBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + # GENERIC_F030C6TX # ----------------------------------------------------------------------------- @@ -63829,7 +63937,7 @@ target_compile_options(GENERIC_G431MBTX_xusb_HSFS INTERFACE # GENERIC_G431R6IX # ----------------------------------------------------------------------------- -set(GENERIC_G431R6IX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G431R6IX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G431R6IX_MAXSIZE 32768) set(GENERIC_G431R6IX_MAXDATASIZE 32768) set(GENERIC_G431R6IX_MCU cortex-m4) @@ -63911,7 +64019,7 @@ target_compile_options(GENERIC_G431R6IX_xusb_HSFS INTERFACE # GENERIC_G431R6TX # ----------------------------------------------------------------------------- -set(GENERIC_G431R6TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G431R6TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G431R6TX_MAXSIZE 32768) set(GENERIC_G431R6TX_MAXDATASIZE 32768) set(GENERIC_G431R6TX_MCU cortex-m4) @@ -63993,7 +64101,7 @@ target_compile_options(GENERIC_G431R6TX_xusb_HSFS INTERFACE # GENERIC_G431R8IX # ----------------------------------------------------------------------------- -set(GENERIC_G431R8IX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G431R8IX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G431R8IX_MAXSIZE 65536) set(GENERIC_G431R8IX_MAXDATASIZE 32768) set(GENERIC_G431R8IX_MCU cortex-m4) @@ -64075,7 +64183,7 @@ target_compile_options(GENERIC_G431R8IX_xusb_HSFS INTERFACE # GENERIC_G431R8TX # ----------------------------------------------------------------------------- -set(GENERIC_G431R8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G431R8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G431R8TX_MAXSIZE 65536) set(GENERIC_G431R8TX_MAXDATASIZE 32768) set(GENERIC_G431R8TX_MCU cortex-m4) @@ -64157,7 +64265,7 @@ target_compile_options(GENERIC_G431R8TX_xusb_HSFS INTERFACE # GENERIC_G431RBIX # ----------------------------------------------------------------------------- -set(GENERIC_G431RBIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G431RBIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G431RBIX_MAXSIZE 131072) set(GENERIC_G431RBIX_MAXDATASIZE 32768) set(GENERIC_G431RBIX_MCU cortex-m4) @@ -64239,7 +64347,7 @@ target_compile_options(GENERIC_G431RBIX_xusb_HSFS INTERFACE # GENERIC_G431RBTX # ----------------------------------------------------------------------------- -set(GENERIC_G431RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G431RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G431RBTX_MAXSIZE 131072) set(GENERIC_G431RBTX_MAXDATASIZE 32768) set(GENERIC_G431RBTX_MCU cortex-m4) @@ -64318,6 +64426,88 @@ target_compile_options(GENERIC_G431RBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G431RBTXZ +# ----------------------------------------------------------------------------- + +set(GENERIC_G431RBTXZ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") +set(GENERIC_G431RBTXZ_MAXSIZE 131072) +set(GENERIC_G431RBTXZ_MAXDATASIZE 32768) +set(GENERIC_G431RBTXZ_MCU cortex-m4) +set(GENERIC_G431RBTXZ_FPCONF "-") +add_library(GENERIC_G431RBTXZ INTERFACE) +target_compile_options(GENERIC_G431RBTXZ INTERFACE + "SHELL:-DSTM32G431xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G431RBTXZ_MCU} +) +target_compile_definitions(GENERIC_G431RBTXZ INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G431RBTXZ" + "BOARD_NAME=\"GENERIC_G431RBTXZ\"" + "BOARD_ID=GENERIC_G431RBTXZ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G431RBTXZ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G431RBTXZ_VARIANT_PATH} +) + +target_link_options(GENERIC_G431RBTXZ INTERFACE + "LINKER:--default-script=${GENERIC_G431RBTXZ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G431RBTXZ_MCU} +) + +add_library(GENERIC_G431RBTXZ_serial_disabled INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G431RBTXZ_serial_generic INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G431RBTXZ_serial_none INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G431RBTXZ_usb_CDC INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G431RBTXZ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G431RBTXZ_usb_HID INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G431RBTXZ_usb_none INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G431RBTXZ_xusb_FS INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G431RBTXZ_xusb_HS INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G431RBTXZ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G431RBTXZ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G431V6TX # ----------------------------------------------------------------------------- @@ -64977,7 +65167,7 @@ target_compile_options(GENERIC_G441MBTX_xusb_HSFS INTERFACE # GENERIC_G441RBIX # ----------------------------------------------------------------------------- -set(GENERIC_G441RBIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G441RBIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G441RBIX_MAXSIZE 131072) set(GENERIC_G441RBIX_MAXDATASIZE 32768) set(GENERIC_G441RBIX_MCU cortex-m4) @@ -65059,7 +65249,7 @@ target_compile_options(GENERIC_G441RBIX_xusb_HSFS INTERFACE # GENERIC_G441RBTX # ----------------------------------------------------------------------------- -set(GENERIC_G441RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(GENERIC_G441RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(GENERIC_G441RBTX_MAXSIZE 131072) set(GENERIC_G441RBTX_MAXDATASIZE 32768) set(GENERIC_G441RBTX_MCU cortex-m4) @@ -67109,7 +67299,7 @@ target_compile_options(GENERIC_G473PEIX_xusb_HSFS INTERFACE # GENERIC_G473QBTX # ----------------------------------------------------------------------------- -set(GENERIC_G473QBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G473QBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G473QBTX_MAXSIZE 131072) set(GENERIC_G473QBTX_MAXDATASIZE 131072) set(GENERIC_G473QBTX_MCU cortex-m4) @@ -67191,7 +67381,7 @@ target_compile_options(GENERIC_G473QBTX_xusb_HSFS INTERFACE # GENERIC_G473QCTX # ----------------------------------------------------------------------------- -set(GENERIC_G473QCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G473QCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G473QCTX_MAXSIZE 262144) set(GENERIC_G473QCTX_MAXDATASIZE 131072) set(GENERIC_G473QCTX_MCU cortex-m4) @@ -67273,7 +67463,7 @@ target_compile_options(GENERIC_G473QCTX_xusb_HSFS INTERFACE # GENERIC_G473QETX # ----------------------------------------------------------------------------- -set(GENERIC_G473QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G473QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G473QETX_MAXSIZE 524288) set(GENERIC_G473QETX_MAXDATASIZE 131072) set(GENERIC_G473QETX_MCU cortex-m4) @@ -67352,10 +67542,92 @@ target_compile_options(GENERIC_G473QETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G473QETXZ +# ----------------------------------------------------------------------------- + +set(GENERIC_G473QETXZ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G473QETXZ_MAXSIZE 524288) +set(GENERIC_G473QETXZ_MAXDATASIZE 131072) +set(GENERIC_G473QETXZ_MCU cortex-m4) +set(GENERIC_G473QETXZ_FPCONF "-") +add_library(GENERIC_G473QETXZ INTERFACE) +target_compile_options(GENERIC_G473QETXZ INTERFACE + "SHELL:-DSTM32G473xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473QETXZ_MCU} +) +target_compile_definitions(GENERIC_G473QETXZ INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G473QETXZ" + "BOARD_NAME=\"GENERIC_G473QETXZ\"" + "BOARD_ID=GENERIC_G473QETXZ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G473QETXZ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G473QETXZ_VARIANT_PATH} +) + +target_link_options(GENERIC_G473QETXZ INTERFACE + "LINKER:--default-script=${GENERIC_G473QETXZ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473QETXZ_MCU} +) + +add_library(GENERIC_G473QETXZ_serial_disabled INTERFACE) +target_compile_options(GENERIC_G473QETXZ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G473QETXZ_serial_generic INTERFACE) +target_compile_options(GENERIC_G473QETXZ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G473QETXZ_serial_none INTERFACE) +target_compile_options(GENERIC_G473QETXZ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G473QETXZ_usb_CDC INTERFACE) +target_compile_options(GENERIC_G473QETXZ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G473QETXZ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G473QETXZ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G473QETXZ_usb_HID INTERFACE) +target_compile_options(GENERIC_G473QETXZ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G473QETXZ_usb_none INTERFACE) +target_compile_options(GENERIC_G473QETXZ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G473QETXZ_xusb_FS INTERFACE) +target_compile_options(GENERIC_G473QETXZ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G473QETXZ_xusb_HS INTERFACE) +target_compile_options(GENERIC_G473QETXZ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G473QETXZ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G473QETXZ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G473RBTX # ----------------------------------------------------------------------------- -set(GENERIC_G473RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G473RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G473RBTX_MAXSIZE 131072) set(GENERIC_G473RBTX_MAXDATASIZE 131072) set(GENERIC_G473RBTX_MCU cortex-m4) @@ -67437,7 +67709,7 @@ target_compile_options(GENERIC_G473RBTX_xusb_HSFS INTERFACE # GENERIC_G473RCTX # ----------------------------------------------------------------------------- -set(GENERIC_G473RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G473RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G473RCTX_MAXSIZE 262144) set(GENERIC_G473RCTX_MAXDATASIZE 131072) set(GENERIC_G473RCTX_MCU cortex-m4) @@ -67519,7 +67791,7 @@ target_compile_options(GENERIC_G473RCTX_xusb_HSFS INTERFACE # GENERIC_G473RETX # ----------------------------------------------------------------------------- -set(GENERIC_G473RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G473RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G473RETX_MAXSIZE 524288) set(GENERIC_G473RETX_MAXDATASIZE 131072) set(GENERIC_G473RETX_MCU cortex-m4) @@ -67598,6 +67870,88 @@ target_compile_options(GENERIC_G473RETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G473RETXZ +# ----------------------------------------------------------------------------- + +set(GENERIC_G473RETXZ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G473RETXZ_MAXSIZE 524288) +set(GENERIC_G473RETXZ_MAXDATASIZE 131072) +set(GENERIC_G473RETXZ_MCU cortex-m4) +set(GENERIC_G473RETXZ_FPCONF "-") +add_library(GENERIC_G473RETXZ INTERFACE) +target_compile_options(GENERIC_G473RETXZ INTERFACE + "SHELL:-DSTM32G473xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473RETXZ_MCU} +) +target_compile_definitions(GENERIC_G473RETXZ INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G473RETXZ" + "BOARD_NAME=\"GENERIC_G473RETXZ\"" + "BOARD_ID=GENERIC_G473RETXZ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G473RETXZ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G473RETXZ_VARIANT_PATH} +) + +target_link_options(GENERIC_G473RETXZ INTERFACE + "LINKER:--default-script=${GENERIC_G473RETXZ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G473RETXZ_MCU} +) + +add_library(GENERIC_G473RETXZ_serial_disabled INTERFACE) +target_compile_options(GENERIC_G473RETXZ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G473RETXZ_serial_generic INTERFACE) +target_compile_options(GENERIC_G473RETXZ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G473RETXZ_serial_none INTERFACE) +target_compile_options(GENERIC_G473RETXZ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G473RETXZ_usb_CDC INTERFACE) +target_compile_options(GENERIC_G473RETXZ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G473RETXZ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G473RETXZ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G473RETXZ_usb_HID INTERFACE) +target_compile_options(GENERIC_G473RETXZ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G473RETXZ_usb_none INTERFACE) +target_compile_options(GENERIC_G473RETXZ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G473RETXZ_xusb_FS INTERFACE) +target_compile_options(GENERIC_G473RETXZ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G473RETXZ_xusb_HS INTERFACE) +target_compile_options(GENERIC_G473RETXZ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G473RETXZ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G473RETXZ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G473VBHX # ----------------------------------------------------------------------------- @@ -68831,7 +69185,7 @@ target_compile_options(GENERIC_G474PEIX_xusb_HSFS INTERFACE # GENERIC_G474QBTX # ----------------------------------------------------------------------------- -set(GENERIC_G474QBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G474QBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G474QBTX_MAXSIZE 131072) set(GENERIC_G474QBTX_MAXDATASIZE 131072) set(GENERIC_G474QBTX_MCU cortex-m4) @@ -68913,7 +69267,7 @@ target_compile_options(GENERIC_G474QBTX_xusb_HSFS INTERFACE # GENERIC_G474QCTX # ----------------------------------------------------------------------------- -set(GENERIC_G474QCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G474QCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G474QCTX_MAXSIZE 262144) set(GENERIC_G474QCTX_MAXDATASIZE 131072) set(GENERIC_G474QCTX_MCU cortex-m4) @@ -68995,7 +69349,7 @@ target_compile_options(GENERIC_G474QCTX_xusb_HSFS INTERFACE # GENERIC_G474QETX # ----------------------------------------------------------------------------- -set(GENERIC_G474QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G474QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G474QETX_MAXSIZE 524288) set(GENERIC_G474QETX_MAXDATASIZE 131072) set(GENERIC_G474QETX_MCU cortex-m4) @@ -69077,7 +69431,7 @@ target_compile_options(GENERIC_G474QETX_xusb_HSFS INTERFACE # GENERIC_G474RBTX # ----------------------------------------------------------------------------- -set(GENERIC_G474RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G474RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G474RBTX_MAXSIZE 131072) set(GENERIC_G474RBTX_MAXDATASIZE 131072) set(GENERIC_G474RBTX_MCU cortex-m4) @@ -69159,7 +69513,7 @@ target_compile_options(GENERIC_G474RBTX_xusb_HSFS INTERFACE # GENERIC_G474RCTX # ----------------------------------------------------------------------------- -set(GENERIC_G474RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G474RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G474RCTX_MAXSIZE 262144) set(GENERIC_G474RCTX_MAXDATASIZE 131072) set(GENERIC_G474RCTX_MCU cortex-m4) @@ -69241,7 +69595,7 @@ target_compile_options(GENERIC_G474RCTX_xusb_HSFS INTERFACE # GENERIC_G474RETX # ----------------------------------------------------------------------------- -set(GENERIC_G474RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G474RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G474RETX_MAXSIZE 524288) set(GENERIC_G474RETX_MAXDATASIZE 131072) set(GENERIC_G474RETX_MCU cortex-m4) @@ -70061,7 +70415,7 @@ target_compile_options(GENERIC_G483PEIX_xusb_HSFS INTERFACE # GENERIC_G483QETX # ----------------------------------------------------------------------------- -set(GENERIC_G483QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G483QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G483QETX_MAXSIZE 524288) set(GENERIC_G483QETX_MAXDATASIZE 131072) set(GENERIC_G483QETX_MCU cortex-m4) @@ -70143,7 +70497,7 @@ target_compile_options(GENERIC_G483QETX_xusb_HSFS INTERFACE # GENERIC_G483RETX # ----------------------------------------------------------------------------- -set(GENERIC_G483RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G483RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G483RETX_MAXSIZE 524288) set(GENERIC_G483RETX_MAXDATASIZE 131072) set(GENERIC_G483RETX_MCU cortex-m4) @@ -70635,7 +70989,7 @@ target_compile_options(GENERIC_G484PEIX_xusb_HSFS INTERFACE # GENERIC_G484QETX # ----------------------------------------------------------------------------- -set(GENERIC_G484QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C-E)T_G474Q(B-C-E)T_G483QET_G484QET") +set(GENERIC_G484QETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473Q(B-C)T_G473QETx(Z)_G474Q(B-C-E)T_G483QET_G484QET") set(GENERIC_G484QETX_MAXSIZE 524288) set(GENERIC_G484QETX_MAXDATASIZE 131072) set(GENERIC_G484QETX_MCU cortex-m4) @@ -70717,7 +71071,7 @@ target_compile_options(GENERIC_G484QETX_xusb_HSFS INTERFACE # GENERIC_G484RETX # ----------------------------------------------------------------------------- -set(GENERIC_G484RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(GENERIC_G484RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(GENERIC_G484RETX_MAXSIZE 524288) set(GENERIC_G484RETX_MAXDATASIZE 131072) set(GENERIC_G484RETX_MCU cortex-m4) @@ -71619,7 +71973,7 @@ target_compile_options(GENERIC_G491METX_xusb_HSFS INTERFACE # GENERIC_G491RCIX # ----------------------------------------------------------------------------- -set(GENERIC_G491RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G491RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RCIX_MAXSIZE 262144) set(GENERIC_G491RCIX_MAXDATASIZE 131072) set(GENERIC_G491RCIX_MCU cortex-m4) @@ -71701,7 +72055,7 @@ target_compile_options(GENERIC_G491RCIX_xusb_HSFS INTERFACE # GENERIC_G491RCTX # ----------------------------------------------------------------------------- -set(GENERIC_G491RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G491RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RCTX_MAXSIZE 262144) set(GENERIC_G491RCTX_MAXDATASIZE 131072) set(GENERIC_G491RCTX_MCU cortex-m4) @@ -71783,7 +72137,7 @@ target_compile_options(GENERIC_G491RCTX_xusb_HSFS INTERFACE # GENERIC_G491REIX # ----------------------------------------------------------------------------- -set(GENERIC_G491REIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G491REIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491REIX_MAXSIZE 524288) set(GENERIC_G491REIX_MAXDATASIZE 131072) set(GENERIC_G491REIX_MCU cortex-m4) @@ -71865,7 +72219,7 @@ target_compile_options(GENERIC_G491REIX_xusb_HSFS INTERFACE # GENERIC_G491RETX # ----------------------------------------------------------------------------- -set(GENERIC_G491RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G491RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491RETX_MAXSIZE 524288) set(GENERIC_G491RETX_MAXDATASIZE 131072) set(GENERIC_G491RETX_MCU cortex-m4) @@ -71944,10 +72298,92 @@ target_compile_options(GENERIC_G491RETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_G491RETXZ +# ----------------------------------------------------------------------------- + +set(GENERIC_G491RETXZ_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") +set(GENERIC_G491RETXZ_MAXSIZE 524288) +set(GENERIC_G491RETXZ_MAXDATASIZE 131072) +set(GENERIC_G491RETXZ_MCU cortex-m4) +set(GENERIC_G491RETXZ_FPCONF "-") +add_library(GENERIC_G491RETXZ INTERFACE) +target_compile_options(GENERIC_G491RETXZ INTERFACE + "SHELL:-DSTM32G491xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G491RETXZ_MCU} +) +target_compile_definitions(GENERIC_G491RETXZ INTERFACE + "STM32G4xx" + "ARDUINO_GENERIC_G491RETXZ" + "BOARD_NAME=\"GENERIC_G491RETXZ\"" + "BOARD_ID=GENERIC_G491RETXZ" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_G491RETXZ INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32G4xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32G4xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/gcc/ + ${GENERIC_G491RETXZ_VARIANT_PATH} +) + +target_link_options(GENERIC_G491RETXZ INTERFACE + "LINKER:--default-script=${GENERIC_G491RETXZ_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_G491RETXZ_MCU} +) + +add_library(GENERIC_G491RETXZ_serial_disabled INTERFACE) +target_compile_options(GENERIC_G491RETXZ_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_G491RETXZ_serial_generic INTERFACE) +target_compile_options(GENERIC_G491RETXZ_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_G491RETXZ_serial_none INTERFACE) +target_compile_options(GENERIC_G491RETXZ_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_G491RETXZ_usb_CDC INTERFACE) +target_compile_options(GENERIC_G491RETXZ_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_G491RETXZ_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_G491RETXZ_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_G491RETXZ_usb_HID INTERFACE) +target_compile_options(GENERIC_G491RETXZ_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_G491RETXZ_usb_none INTERFACE) +target_compile_options(GENERIC_G491RETXZ_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_G491RETXZ_xusb_FS INTERFACE) +target_compile_options(GENERIC_G491RETXZ_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_G491RETXZ_xusb_HS INTERFACE) +target_compile_options(GENERIC_G491RETXZ_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_G491RETXZ_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_G491RETXZ_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_G491REYX # ----------------------------------------------------------------------------- -set(GENERIC_G491REYX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G491REYX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G491REYX_MAXSIZE 524288) set(GENERIC_G491REYX_MAXDATASIZE 131072) set(GENERIC_G491REYX_MCU cortex-m4) @@ -72521,7 +72957,7 @@ target_compile_options(GENERIC_G4A1METX_xusb_HSFS INTERFACE # GENERIC_G4A1REIX # ----------------------------------------------------------------------------- -set(GENERIC_G4A1REIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G4A1REIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G4A1REIX_MAXSIZE 524288) set(GENERIC_G4A1REIX_MAXDATASIZE 131072) set(GENERIC_G4A1REIX_MCU cortex-m4) @@ -72603,7 +73039,7 @@ target_compile_options(GENERIC_G4A1REIX_xusb_HSFS INTERFACE # GENERIC_G4A1RETX # ----------------------------------------------------------------------------- -set(GENERIC_G4A1RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G4A1RETX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G4A1RETX_MAXSIZE 524288) set(GENERIC_G4A1RETX_MAXDATASIZE 131072) set(GENERIC_G4A1RETX_MCU cortex-m4) @@ -72685,7 +73121,7 @@ target_compile_options(GENERIC_G4A1RETX_xusb_HSFS INTERFACE # GENERIC_G4A1REYX # ----------------------------------------------------------------------------- -set(GENERIC_G4A1REYX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)_G4A1RE(I-T-Y)") +set(GENERIC_G4A1REYX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G491RC(I-T)_G491RE(I-T-Y)x(Z)_G4A1RE(I-T-Y)") set(GENERIC_G4A1REYX_MAXSIZE 524288) set(GENERIC_G4A1REYX_MAXDATASIZE 131072) set(GENERIC_G4A1REYX_MCU cortex-m4) @@ -72846,6 +73282,170 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H503CBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H503CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503CB(T-U)") +set(GENERIC_H503CBTX_MAXSIZE 131072) +set(GENERIC_H503CBTX_MAXDATASIZE 32768) +set(GENERIC_H503CBTX_MCU cortex-m33) +set(GENERIC_H503CBTX_FPCONF "-") +add_library(GENERIC_H503CBTX INTERFACE) +target_compile_options(GENERIC_H503CBTX INTERFACE + "SHELL:-DSTM32H503xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H503CBTX_MCU} +) +target_compile_definitions(GENERIC_H503CBTX INTERFACE + "STM32H5xx" + "ARDUINO_GENERIC_H503CBTX" + "BOARD_NAME=\"GENERIC_H503CBTX\"" + "BOARD_ID=GENERIC_H503CBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H503CBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${GENERIC_H503CBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H503CBTX INTERFACE + "LINKER:--default-script=${GENERIC_H503CBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H503CBTX_MCU} +) + +add_library(GENERIC_H503CBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H503CBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H503CBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H503CBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H503CBTX_serial_none INTERFACE) +target_compile_options(GENERIC_H503CBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H503CBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H503CBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H503CBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H503CBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H503CBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H503CBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H503CBTX_usb_none INTERFACE) +target_compile_options(GENERIC_H503CBTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H503CBTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H503CBTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H503CBTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H503CBTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H503CBTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H503CBTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H503CBUX +# ----------------------------------------------------------------------------- + +set(GENERIC_H503CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503CB(T-U)") +set(GENERIC_H503CBUX_MAXSIZE 131072) +set(GENERIC_H503CBUX_MAXDATASIZE 32768) +set(GENERIC_H503CBUX_MCU cortex-m33) +set(GENERIC_H503CBUX_FPCONF "-") +add_library(GENERIC_H503CBUX INTERFACE) +target_compile_options(GENERIC_H503CBUX INTERFACE + "SHELL:-DSTM32H503xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H503CBUX_MCU} +) +target_compile_definitions(GENERIC_H503CBUX INTERFACE + "STM32H5xx" + "ARDUINO_GENERIC_H503CBUX" + "BOARD_NAME=\"GENERIC_H503CBUX\"" + "BOARD_ID=GENERIC_H503CBUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H503CBUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${GENERIC_H503CBUX_VARIANT_PATH} +) + +target_link_options(GENERIC_H503CBUX INTERFACE + "LINKER:--default-script=${GENERIC_H503CBUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=32768" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H503CBUX_MCU} +) + +add_library(GENERIC_H503CBUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H503CBUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H503CBUX_serial_generic INTERFACE) +target_compile_options(GENERIC_H503CBUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H503CBUX_serial_none INTERFACE) +target_compile_options(GENERIC_H503CBUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H503CBUX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H503CBUX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H503CBUX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H503CBUX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H503CBUX_usb_HID INTERFACE) +target_compile_options(GENERIC_H503CBUX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H503CBUX_usb_none INTERFACE) +target_compile_options(GENERIC_H503CBUX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H503CBUX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H503CBUX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H503CBUX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H503CBUX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H503CBUX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H503CBUX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H503KBUX # ----------------------------------------------------------------------------- @@ -73010,6 +73610,170 @@ target_compile_options(GENERIC_H503RBTX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_H562RGTX +# ----------------------------------------------------------------------------- + +set(GENERIC_H562RGTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H562R(G-I)T") +set(GENERIC_H562RGTX_MAXSIZE 1048576) +set(GENERIC_H562RGTX_MAXDATASIZE 655360) +set(GENERIC_H562RGTX_MCU cortex-m33) +set(GENERIC_H562RGTX_FPCONF "-") +add_library(GENERIC_H562RGTX INTERFACE) +target_compile_options(GENERIC_H562RGTX INTERFACE + "SHELL:-DSTM32H562xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H562RGTX_MCU} +) +target_compile_definitions(GENERIC_H562RGTX INTERFACE + "STM32H5xx" + "ARDUINO_GENERIC_H562RGTX" + "BOARD_NAME=\"GENERIC_H562RGTX\"" + "BOARD_ID=GENERIC_H562RGTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H562RGTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${GENERIC_H562RGTX_VARIANT_PATH} +) + +target_link_options(GENERIC_H562RGTX INTERFACE + "LINKER:--default-script=${GENERIC_H562RGTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=655360" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H562RGTX_MCU} +) + +add_library(GENERIC_H562RGTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H562RGTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H562RGTX_serial_generic INTERFACE) +target_compile_options(GENERIC_H562RGTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H562RGTX_serial_none INTERFACE) +target_compile_options(GENERIC_H562RGTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H562RGTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H562RGTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H562RGTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H562RGTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H562RGTX_usb_HID INTERFACE) +target_compile_options(GENERIC_H562RGTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H562RGTX_usb_none INTERFACE) +target_compile_options(GENERIC_H562RGTX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H562RGTX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H562RGTX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H562RGTX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H562RGTX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H562RGTX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H562RGTX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + +# GENERIC_H562RITX +# ----------------------------------------------------------------------------- + +set(GENERIC_H562RITX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H562R(G-I)T") +set(GENERIC_H562RITX_MAXSIZE 2097152) +set(GENERIC_H562RITX_MAXDATASIZE 655360) +set(GENERIC_H562RITX_MCU cortex-m33) +set(GENERIC_H562RITX_FPCONF "-") +add_library(GENERIC_H562RITX INTERFACE) +target_compile_options(GENERIC_H562RITX INTERFACE + "SHELL:-DSTM32H562xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H562RITX_MCU} +) +target_compile_definitions(GENERIC_H562RITX INTERFACE + "STM32H5xx" + "ARDUINO_GENERIC_H562RITX" + "BOARD_NAME=\"GENERIC_H562RITX\"" + "BOARD_ID=GENERIC_H562RITX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_H562RITX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${GENERIC_H562RITX_VARIANT_PATH} +) + +target_link_options(GENERIC_H562RITX INTERFACE + "LINKER:--default-script=${GENERIC_H562RITX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=2097152" + "LINKER:--defsym=LD_MAX_DATA_SIZE=655360" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_H562RITX_MCU} +) + +add_library(GENERIC_H562RITX_serial_disabled INTERFACE) +target_compile_options(GENERIC_H562RITX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_H562RITX_serial_generic INTERFACE) +target_compile_options(GENERIC_H562RITX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_H562RITX_serial_none INTERFACE) +target_compile_options(GENERIC_H562RITX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_H562RITX_usb_CDC INTERFACE) +target_compile_options(GENERIC_H562RITX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_H562RITX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_H562RITX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_H562RITX_usb_HID INTERFACE) +target_compile_options(GENERIC_H562RITX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_H562RITX_usb_none INTERFACE) +target_compile_options(GENERIC_H562RITX_usb_none INTERFACE + "SHELL:" +) +add_library(GENERIC_H562RITX_xusb_FS INTERFACE) +target_compile_options(GENERIC_H562RITX_xusb_FS INTERFACE + "SHELL:" +) +add_library(GENERIC_H562RITX_xusb_HS INTERFACE) +target_compile_options(GENERIC_H562RITX_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(GENERIC_H562RITX_xusb_HSFS INTERFACE) +target_compile_options(GENERIC_H562RITX_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # GENERIC_H563IIKXQ # ----------------------------------------------------------------------------- @@ -97370,6 +98134,566 @@ target_compile_options(GENERIC_NODE_SE_TTI_serial_none INTERFACE "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" ) +# GENERIC_U073R8IX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073R8IX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U073R8IX_MAXSIZE 65536) +set(GENERIC_U073R8IX_MAXDATASIZE 40960) +set(GENERIC_U073R8IX_MCU cortex-m0plus) +set(GENERIC_U073R8IX_FPCONF "-") +add_library(GENERIC_U073R8IX INTERFACE) +target_compile_options(GENERIC_U073R8IX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073R8IX_MCU} +) +target_compile_definitions(GENERIC_U073R8IX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073R8IX" + "BOARD_NAME=\"GENERIC_U073R8IX\"" + "BOARD_ID=GENERIC_U073R8IX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073R8IX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073R8IX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073R8IX INTERFACE + "LINKER:--default-script=${GENERIC_U073R8IX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073R8IX_MCU} +) + +add_library(GENERIC_U073R8IX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073R8IX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073R8IX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073R8IX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073R8IX_serial_none INTERFACE) +target_compile_options(GENERIC_U073R8IX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073R8IX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073R8IX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073R8IX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073R8IX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073R8IX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073R8IX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073R8IX_usb_none INTERFACE) +target_compile_options(GENERIC_U073R8IX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073R8TX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073R8TX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U073R8TX_MAXSIZE 65536) +set(GENERIC_U073R8TX_MAXDATASIZE 40960) +set(GENERIC_U073R8TX_MCU cortex-m0plus) +set(GENERIC_U073R8TX_FPCONF "-") +add_library(GENERIC_U073R8TX INTERFACE) +target_compile_options(GENERIC_U073R8TX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073R8TX_MCU} +) +target_compile_definitions(GENERIC_U073R8TX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073R8TX" + "BOARD_NAME=\"GENERIC_U073R8TX\"" + "BOARD_ID=GENERIC_U073R8TX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073R8TX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073R8TX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073R8TX INTERFACE + "LINKER:--default-script=${GENERIC_U073R8TX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=65536" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073R8TX_MCU} +) + +add_library(GENERIC_U073R8TX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073R8TX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073R8TX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073R8TX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073R8TX_serial_none INTERFACE) +target_compile_options(GENERIC_U073R8TX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073R8TX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073R8TX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073R8TX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073R8TX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073R8TX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073R8TX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073R8TX_usb_none INTERFACE) +target_compile_options(GENERIC_U073R8TX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073RBIX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073RBIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U073RBIX_MAXSIZE 131072) +set(GENERIC_U073RBIX_MAXDATASIZE 40960) +set(GENERIC_U073RBIX_MCU cortex-m0plus) +set(GENERIC_U073RBIX_FPCONF "-") +add_library(GENERIC_U073RBIX INTERFACE) +target_compile_options(GENERIC_U073RBIX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073RBIX_MCU} +) +target_compile_definitions(GENERIC_U073RBIX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073RBIX" + "BOARD_NAME=\"GENERIC_U073RBIX\"" + "BOARD_ID=GENERIC_U073RBIX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073RBIX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073RBIX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073RBIX INTERFACE + "LINKER:--default-script=${GENERIC_U073RBIX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073RBIX_MCU} +) + +add_library(GENERIC_U073RBIX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073RBIX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073RBIX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073RBIX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073RBIX_serial_none INTERFACE) +target_compile_options(GENERIC_U073RBIX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073RBIX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073RBIX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073RBIX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073RBIX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073RBIX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073RBIX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073RBIX_usb_none INTERFACE) +target_compile_options(GENERIC_U073RBIX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073RBTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073RBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U073RBTX_MAXSIZE 131072) +set(GENERIC_U073RBTX_MAXDATASIZE 40960) +set(GENERIC_U073RBTX_MCU cortex-m0plus) +set(GENERIC_U073RBTX_FPCONF "-") +add_library(GENERIC_U073RBTX INTERFACE) +target_compile_options(GENERIC_U073RBTX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073RBTX_MCU} +) +target_compile_definitions(GENERIC_U073RBTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073RBTX" + "BOARD_NAME=\"GENERIC_U073RBTX\"" + "BOARD_ID=GENERIC_U073RBTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073RBTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073RBTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073RBTX INTERFACE + "LINKER:--default-script=${GENERIC_U073RBTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073RBTX_MCU} +) + +add_library(GENERIC_U073RBTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073RBTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073RBTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073RBTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073RBTX_serial_none INTERFACE) +target_compile_options(GENERIC_U073RBTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073RBTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073RBTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073RBTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073RBTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073RBTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073RBTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073RBTX_usb_none INTERFACE) +target_compile_options(GENERIC_U073RBTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073RCIX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U073RCIX_MAXSIZE 262144) +set(GENERIC_U073RCIX_MAXDATASIZE 40960) +set(GENERIC_U073RCIX_MCU cortex-m0plus) +set(GENERIC_U073RCIX_FPCONF "-") +add_library(GENERIC_U073RCIX INTERFACE) +target_compile_options(GENERIC_U073RCIX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073RCIX_MCU} +) +target_compile_definitions(GENERIC_U073RCIX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073RCIX" + "BOARD_NAME=\"GENERIC_U073RCIX\"" + "BOARD_ID=GENERIC_U073RCIX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073RCIX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073RCIX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073RCIX INTERFACE + "LINKER:--default-script=${GENERIC_U073RCIX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073RCIX_MCU} +) + +add_library(GENERIC_U073RCIX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073RCIX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073RCIX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073RCIX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073RCIX_serial_none INTERFACE) +target_compile_options(GENERIC_U073RCIX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073RCIX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073RCIX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073RCIX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073RCIX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073RCIX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073RCIX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073RCIX_usb_none INTERFACE) +target_compile_options(GENERIC_U073RCIX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U073RCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U073RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U073RCTX_MAXSIZE 262144) +set(GENERIC_U073RCTX_MAXDATASIZE 40960) +set(GENERIC_U073RCTX_MCU cortex-m0plus) +set(GENERIC_U073RCTX_FPCONF "-") +add_library(GENERIC_U073RCTX INTERFACE) +target_compile_options(GENERIC_U073RCTX INTERFACE + "SHELL:-DSTM32U073xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U073RCTX_MCU} +) +target_compile_definitions(GENERIC_U073RCTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U073RCTX" + "BOARD_NAME=\"GENERIC_U073RCTX\"" + "BOARD_ID=GENERIC_U073RCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U073RCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U073RCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U073RCTX INTERFACE + "LINKER:--default-script=${GENERIC_U073RCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U073RCTX_MCU} +) + +add_library(GENERIC_U073RCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U073RCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U073RCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U073RCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U073RCTX_serial_none INTERFACE) +target_compile_options(GENERIC_U073RCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U073RCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U073RCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U073RCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U073RCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U073RCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U073RCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U073RCTX_usb_none INTERFACE) +target_compile_options(GENERIC_U073RCTX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U083RCIX +# ----------------------------------------------------------------------------- + +set(GENERIC_U083RCIX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U083RCIX_MAXSIZE 262144) +set(GENERIC_U083RCIX_MAXDATASIZE 40960) +set(GENERIC_U083RCIX_MCU cortex-m0plus) +set(GENERIC_U083RCIX_FPCONF "-") +add_library(GENERIC_U083RCIX INTERFACE) +target_compile_options(GENERIC_U083RCIX INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U083RCIX_MCU} +) +target_compile_definitions(GENERIC_U083RCIX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U083RCIX" + "BOARD_NAME=\"GENERIC_U083RCIX\"" + "BOARD_ID=GENERIC_U083RCIX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U083RCIX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U083RCIX_VARIANT_PATH} +) + +target_link_options(GENERIC_U083RCIX INTERFACE + "LINKER:--default-script=${GENERIC_U083RCIX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U083RCIX_MCU} +) + +add_library(GENERIC_U083RCIX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U083RCIX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U083RCIX_serial_generic INTERFACE) +target_compile_options(GENERIC_U083RCIX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U083RCIX_serial_none INTERFACE) +target_compile_options(GENERIC_U083RCIX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U083RCIX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U083RCIX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U083RCIX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U083RCIX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U083RCIX_usb_HID INTERFACE) +target_compile_options(GENERIC_U083RCIX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U083RCIX_usb_none INTERFACE) +target_compile_options(GENERIC_U083RCIX_usb_none INTERFACE + "SHELL:" +) + +# GENERIC_U083RCTX +# ----------------------------------------------------------------------------- + +set(GENERIC_U083RCTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(GENERIC_U083RCTX_MAXSIZE 262144) +set(GENERIC_U083RCTX_MAXDATASIZE 40960) +set(GENERIC_U083RCTX_MCU cortex-m0plus) +set(GENERIC_U083RCTX_FPCONF "-") +add_library(GENERIC_U083RCTX INTERFACE) +target_compile_options(GENERIC_U083RCTX INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${GENERIC_U083RCTX_MCU} +) +target_compile_definitions(GENERIC_U083RCTX INTERFACE + "STM32U0xx" + "ARDUINO_GENERIC_U083RCTX" + "BOARD_NAME=\"GENERIC_U083RCTX\"" + "BOARD_ID=GENERIC_U083RCTX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_U083RCTX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${GENERIC_U083RCTX_VARIANT_PATH} +) + +target_link_options(GENERIC_U083RCTX INTERFACE + "LINKER:--default-script=${GENERIC_U083RCTX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${GENERIC_U083RCTX_MCU} +) + +add_library(GENERIC_U083RCTX_serial_disabled INTERFACE) +target_compile_options(GENERIC_U083RCTX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_U083RCTX_serial_generic INTERFACE) +target_compile_options(GENERIC_U083RCTX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_U083RCTX_serial_none INTERFACE) +target_compile_options(GENERIC_U083RCTX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(GENERIC_U083RCTX_usb_CDC INTERFACE) +target_compile_options(GENERIC_U083RCTX_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(GENERIC_U083RCTX_usb_CDCgen INTERFACE) +target_compile_options(GENERIC_U083RCTX_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(GENERIC_U083RCTX_usb_HID INTERFACE) +target_compile_options(GENERIC_U083RCTX_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(GENERIC_U083RCTX_usb_none INTERFACE) +target_compile_options(GENERIC_U083RCTX_usb_none INTERFACE + "SHELL:" +) + # GENERIC_U575AGIXQ # ----------------------------------------------------------------------------- @@ -100850,6 +102174,88 @@ target_compile_options(NUCLEO_C031C6_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_C071RB +# ----------------------------------------------------------------------------- + +set(NUCLEO_C071RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32C0xx/C071R(8-B)T") +set(NUCLEO_C071RB_MAXSIZE 131072) +set(NUCLEO_C071RB_MAXDATASIZE 24576) +set(NUCLEO_C071RB_MCU cortex-m0plus) +set(NUCLEO_C071RB_FPCONF "-") +add_library(NUCLEO_C071RB INTERFACE) +target_compile_options(NUCLEO_C071RB INTERFACE + "SHELL:-DSTM32C071xx -D__CORTEX_SC=0" + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL: " + -mcpu=${NUCLEO_C071RB_MCU} +) +target_compile_definitions(NUCLEO_C071RB INTERFACE + "STM32C0xx" + "ARDUINO_NUCLEO_C071RB" + "BOARD_NAME=\"NUCLEO_C071RB\"" + "BOARD_ID=NUCLEO_C071RB" + "VARIANT_H=\"variant_NUCLEO_C071RB.h\"" +) +target_include_directories(NUCLEO_C071RB INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32C0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32C0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32C0xx/Source/Templates/gcc/ + ${NUCLEO_C071RB_VARIANT_PATH} +) + +target_link_options(NUCLEO_C071RB INTERFACE + "LINKER:--default-script=${NUCLEO_C071RB_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=131072" + "LINKER:--defsym=LD_MAX_DATA_SIZE=24576" + "SHELL: " + -mcpu=${NUCLEO_C071RB_MCU} +) + +add_library(NUCLEO_C071RB_serial_disabled INTERFACE) +target_compile_options(NUCLEO_C071RB_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_C071RB_serial_generic INTERFACE) +target_compile_options(NUCLEO_C071RB_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_C071RB_serial_none INTERFACE) +target_compile_options(NUCLEO_C071RB_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_C071RB_usb_CDC INTERFACE) +target_compile_options(NUCLEO_C071RB_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_C071RB_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_C071RB_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_C071RB_usb_HID INTERFACE) +target_compile_options(NUCLEO_C071RB_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_C071RB_usb_none INTERFACE) +target_compile_options(NUCLEO_C071RB_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_C071RB_xusb_FS INTERFACE) +target_compile_options(NUCLEO_C071RB_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_C071RB_xusb_HS INTERFACE) +target_compile_options(NUCLEO_C071RB_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_C071RB_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_C071RB_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_F030R8 # ----------------------------------------------------------------------------- @@ -103149,7 +104555,7 @@ target_compile_options(NUCLEO_G431KB_xusb_HSFS INTERFACE # NUCLEO_G431RB # ----------------------------------------------------------------------------- -set(NUCLEO_G431RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8-B)(I-T)_G441RB(I-T)") +set(NUCLEO_G431RB_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G431R(6-8)(I-T)_G431RB(I-T)x(Z)_G441RB(I-T)") set(NUCLEO_G431RB_MAXSIZE 131072) set(NUCLEO_G431RB_MAXDATASIZE 32768) set(NUCLEO_G431RB_MCU cortex-m4) @@ -103231,7 +104637,7 @@ target_compile_options(NUCLEO_G431RB_xusb_HSFS INTERFACE # NUCLEO_G474RE # ----------------------------------------------------------------------------- -set(NUCLEO_G474RE_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C-E)T_G474R(B-C-E)T_G483RET_G484RET") +set(NUCLEO_G474RE_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32G4xx/G473R(B-C)T_G473RETx(Z)_G474R(B-C-E)T_G483RET_G484RET") set(NUCLEO_G474RE_MAXSIZE 524288) set(NUCLEO_G474RE_MAXDATASIZE 131072) set(NUCLEO_G474RE_MCU cortex-m4) @@ -105114,6 +106520,88 @@ target_compile_options(NUCLEO_L552ZE_Q_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_U083RC +# ----------------------------------------------------------------------------- + +set(NUCLEO_U083RC_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32U0xx/U073R(8-B-C)(I-T)_U083RC(I-T)") +set(NUCLEO_U083RC_MAXSIZE 262144) +set(NUCLEO_U083RC_MAXDATASIZE 40960) +set(NUCLEO_U083RC_MCU cortex-m0plus) +set(NUCLEO_U083RC_FPCONF "-") +add_library(NUCLEO_U083RC INTERFACE) +target_compile_options(NUCLEO_U083RC INTERFACE + "SHELL:-DSTM32U083xx -D__CORTEX_SC=0" + "SHELL:" + "SHELL:" + "SHELL: " + -mcpu=${NUCLEO_U083RC_MCU} +) +target_compile_definitions(NUCLEO_U083RC INTERFACE + "STM32U0xx" + "ARDUINO_NUCLEO_U083RC" + "BOARD_NAME=\"NUCLEO_U083RC\"" + "BOARD_ID=NUCLEO_U083RC" + "VARIANT_H=\"variant_NUCLEO_U083RC.h\"" +) +target_include_directories(NUCLEO_U083RC INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32U0xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32U0xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32U0xx/Source/Templates/gcc/ + ${NUCLEO_U083RC_VARIANT_PATH} +) + +target_link_options(NUCLEO_U083RC INTERFACE + "LINKER:--default-script=${NUCLEO_U083RC_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=262144" + "LINKER:--defsym=LD_MAX_DATA_SIZE=40960" + "SHELL: " + -mcpu=${NUCLEO_U083RC_MCU} +) + +add_library(NUCLEO_U083RC_serial_disabled INTERFACE) +target_compile_options(NUCLEO_U083RC_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_U083RC_serial_generic INTERFACE) +target_compile_options(NUCLEO_U083RC_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_U083RC_serial_none INTERFACE) +target_compile_options(NUCLEO_U083RC_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_U083RC_usb_CDC INTERFACE) +target_compile_options(NUCLEO_U083RC_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_U083RC_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_U083RC_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_U083RC_usb_HID INTERFACE) +target_compile_options(NUCLEO_U083RC_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_U083RC_usb_none INTERFACE) +target_compile_options(NUCLEO_U083RC_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_U083RC_xusb_FS INTERFACE) +target_compile_options(NUCLEO_U083RC_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_U083RC_xusb_HS INTERFACE) +target_compile_options(NUCLEO_U083RC_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_U083RC_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_U083RC_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_U575ZI_Q # ----------------------------------------------------------------------------- @@ -106988,6 +108476,60 @@ target_compile_options(ST3DP001_EVAL_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# STEAM32_WB55RG +# ----------------------------------------------------------------------------- + +set(STEAM32_WB55RG_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBxx/WB55R(C-E-G)V") +set(STEAM32_WB55RG_MAXSIZE 524288) +set(STEAM32_WB55RG_MAXDATASIZE 196608) +set(STEAM32_WB55RG_MCU cortex-m4) +set(STEAM32_WB55RG_FPCONF "fpv4-sp-d16-hard") +add_library(STEAM32_WB55RG INTERFACE) +target_compile_options(STEAM32_WB55RG INTERFACE + "SHELL:-DSTM32WB55xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${STEAM32_WB55RG_MCU} +) +target_compile_definitions(STEAM32_WB55RG INTERFACE + "STM32WBxx" + "ARDUINO_STEAM32_WB55RG" + "BOARD_NAME=\"STEAM32_WB55RG\"" + "BOARD_ID=STEAM32_WB55RG" + "VARIANT_H=\"variant_STEAM32_WB55RG.h\"" +) +target_include_directories(STEAM32_WB55RG INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WBxx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBxx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/ + ${STEAM32_WB55RG_VARIANT_PATH} +) + +target_link_options(STEAM32_WB55RG INTERFACE + "LINKER:--default-script=${STEAM32_WB55RG_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=196608" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${STEAM32_WB55RG_MCU} +) + +add_library(STEAM32_WB55RG_serial_disabled INTERFACE) +target_compile_options(STEAM32_WB55RG_serial_disabled INTERFACE + "SHELL:" +) +add_library(STEAM32_WB55RG_serial_generic INTERFACE) +target_compile_options(STEAM32_WB55RG_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(STEAM32_WB55RG_serial_none INTERFACE) +target_compile_options(STEAM32_WB55RG_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + # STEVAL_MKBOXPRO # ----------------------------------------------------------------------------- @@ -108666,6 +110208,88 @@ target_link_options(VCCGND_F407ZG_MINI_hid INTERFACE ) +# WEACT_H562RG +# ----------------------------------------------------------------------------- + +set(WEACT_H562RG_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H562R(G-I)T") +set(WEACT_H562RG_MAXSIZE 1048576) +set(WEACT_H562RG_MAXDATASIZE 655360) +set(WEACT_H562RG_MCU cortex-m33) +set(WEACT_H562RG_FPCONF "-") +add_library(WEACT_H562RG INTERFACE) +target_compile_options(WEACT_H562RG INTERFACE + "SHELL:-DSTM32H562xx " + "SHELL:-DCUSTOM_PERIPHERAL_PINS" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${WEACT_H562RG_MCU} +) +target_compile_definitions(WEACT_H562RG INTERFACE + "STM32H5xx" + "ARDUINO_WEACT_H562RG" + "BOARD_NAME=\"WEACT_H562RG\"" + "BOARD_ID=WEACT_H562RG" + "VARIANT_H=\"variant_WEACT_H562RG.h\"" +) +target_include_directories(WEACT_H562RG INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/ + ${WEACT_H562RG_VARIANT_PATH} +) + +target_link_options(WEACT_H562RG INTERFACE + "LINKER:--default-script=${WEACT_H562RG_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=655360" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${WEACT_H562RG_MCU} +) + +add_library(WEACT_H562RG_serial_disabled INTERFACE) +target_compile_options(WEACT_H562RG_serial_disabled INTERFACE + "SHELL:" +) +add_library(WEACT_H562RG_serial_generic INTERFACE) +target_compile_options(WEACT_H562RG_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(WEACT_H562RG_serial_none INTERFACE) +target_compile_options(WEACT_H562RG_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(WEACT_H562RG_usb_CDC INTERFACE) +target_compile_options(WEACT_H562RG_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(WEACT_H562RG_usb_CDCgen INTERFACE) +target_compile_options(WEACT_H562RG_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(WEACT_H562RG_usb_HID INTERFACE) +target_compile_options(WEACT_H562RG_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(WEACT_H562RG_usb_none INTERFACE) +target_compile_options(WEACT_H562RG_usb_none INTERFACE + "SHELL:" +) +add_library(WEACT_H562RG_xusb_FS INTERFACE) +target_compile_options(WEACT_H562RG_xusb_FS INTERFACE + "SHELL:" +) +add_library(WEACT_H562RG_xusb_HS INTERFACE) +target_compile_options(WEACT_H562RG_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(WEACT_H562RG_xusb_HSFS INTERFACE) +target_compile_options(WEACT_H562RG_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # WeActMiniH743VITX # ----------------------------------------------------------------------------- diff --git a/cmake/scripts/cmake_easy_setup.py b/cmake/scripts/cmake_easy_setup.py old mode 100644 new mode 100755 diff --git a/cmake/scripts/update_boarddb.py b/cmake/scripts/update_boarddb.py index e0dd6fa469..0168c9aa71 100644 --- a/cmake/scripts/update_boarddb.py +++ b/cmake/scripts/update_boarddb.py @@ -13,7 +13,7 @@ def get_fpconf(config): def boardstxt_filter(key): - # Remove menu entry labels + # Remove menu entry labels and oopenocd config if any # In our data model, they conflict with the actual configuration # they are associated to # i.e. Nucleo_144.menu.pnum.NUCLEO_F207ZG would be both @@ -22,7 +22,8 @@ def boardstxt_filter(key): if key[-1] == "svd_file": return True - + if len(key) >= 5 and key[-2] == "scripts" and key[-3] == "openocd": + return True if key[0] == "menu": # menu.xserial=U(S)ART support return True @@ -41,9 +42,10 @@ def boardstxt_filter(key): def platformtxt_filter(key): - # reject everything but build.** - # and also build.info (that's specific to the build system, we'll hard-code it) - # we don't need anything else from platform.txt + # reject everything except build.**, vid.** and pid.** + # Note that build.info is also rejected + # (it is specific to the build system, it will be hard-coded) + # nothing else is needed from platform.txt # +additional stuff might confuse later parts of the script # e.g.: diff --git a/cores/arduino/HardwareSerial.cpp b/cores/arduino/HardwareSerial.cpp index 146cfa234e..1c89de7f61 100644 --- a/cores/arduino/HardwareSerial.cpp +++ b/cores/arduino/HardwareSerial.cpp @@ -30,7 +30,8 @@ #if defined(HAVE_HWSERIAL1) || defined(HAVE_HWSERIAL2) || defined(HAVE_HWSERIAL3) ||\ defined(HAVE_HWSERIAL4) || defined(HAVE_HWSERIAL5) || defined(HAVE_HWSERIAL6) ||\ defined(HAVE_HWSERIAL7) || defined(HAVE_HWSERIAL8) || defined(HAVE_HWSERIAL9) ||\ - defined(HAVE_HWSERIAL10) || defined(HAVE_HWSERIALLP1) || defined(HAVE_HWSERIALLP2) + defined(HAVE_HWSERIAL10) || defined(HAVE_HWSERIALLP1) || defined(HAVE_HWSERIALLP2) ||\ + defined(HAVE_HWSERIALLP3) // SerialEvent functions are weak, so when the user doesn't define them, // the linker just sets their address to 0 (which is checked below). #if defined(HAVE_HWSERIAL1) @@ -112,6 +113,10 @@ HardwareSerial SerialLP2(LPUART2); void serialEventLP2() __attribute__((weak)); #endif + #if defined(HAVE_HWSERIALLP3) + HardwareSerial SerialLP2(LPUART3); + void serialEventLP3() __attribute__((weak)); + #endif #endif // HAVE_HWSERIALx // Constructors //////////////////////////////////////////////////////////////// @@ -267,22 +272,30 @@ HardwareSerial::HardwareSerial(void *peripheral, HalfDuplexMode_t halfDuplex) setTx(PIN_SERIALLP2_TX); } else #endif +#if defined(PIN_SERIALLP3_TX) && defined(LPUART3_BASE) + if (peripheral == LPUART2) { +#if defined(PIN_SERIALLP3_RX) + setRx(PIN_SERIALLP3_RX); +#endif + setTx(PIN_SERIALLP3_TX); + } else +#endif #if defined(PIN_SERIAL_TX) - // If PIN_SERIAL_TX is defined but Serial is mapped on other peripheral - // (usually SerialUSB) use the pins defined for specified peripheral - // instead of the first one found - if ((pinmap_peripheral(digitalPinToPinName(PIN_SERIAL_TX), PinMap_UART_TX) == peripheral)) { + // If PIN_SERIAL_TX is defined but Serial is mapped on other peripheral + // (usually SerialUSB) use the pins defined for specified peripheral + // instead of the first one found + if ((pinmap_peripheral(digitalPinToPinName(PIN_SERIAL_TX), PinMap_UART_TX) == peripheral)) { #if defined(PIN_SERIAL_RX) - setRx(PIN_SERIAL_RX); + setRx(PIN_SERIAL_RX); #endif - setTx(PIN_SERIAL_TX); - } else + setTx(PIN_SERIAL_TX); + } else #endif - { - // else get the pins of the first peripheral occurrence in PinMap - _serial.pin_rx = pinmap_pin(peripheral, PinMap_UART_RX); - _serial.pin_tx = pinmap_pin(peripheral, PinMap_UART_TX); - } + { + // else get the pins of the first peripheral occurrence in PinMap + _serial.pin_rx = pinmap_pin(peripheral, PinMap_UART_RX); + _serial.pin_tx = pinmap_pin(peripheral, PinMap_UART_TX); + } if (halfDuplex == HALF_DUPLEX_ENABLED) { _serial.pin_rx = NC; } diff --git a/cores/arduino/HardwareSerial.h b/cores/arduino/HardwareSerial.h index bfd94620ba..f8a2884de0 100644 --- a/cores/arduino/HardwareSerial.h +++ b/cores/arduino/HardwareSerial.h @@ -35,11 +35,6 @@ // location from which to read. // NOTE: a "power of 2" buffer size is recommended to dramatically // optimize all the modulo operations for ring buffers. -// WARNING: When buffer sizes are increased to > 256, the buffer index -// variables are automatically increased in size, but the extra -// atomicity guards needed for that are not implemented. This will -// often work, but occasionally a race condition can occur that makes -// Serial behave erratically. See https://github.com/arduino/Arduino/issues/2405 #if !defined(SERIAL_TX_BUFFER_SIZE) #define SERIAL_TX_BUFFER_SIZE 64 #endif @@ -228,4 +223,7 @@ class HardwareSerial : public Stream { #if defined(LPUART2) extern HardwareSerial SerialLP2; #endif +#if defined(LPUART3) + extern HardwareSerial SerialLP3; +#endif #endif diff --git a/cores/arduino/Print.cpp b/cores/arduino/Print.cpp index e9267405a5..62623492df 100644 --- a/cores/arduino/Print.cpp +++ b/cores/arduino/Print.cpp @@ -374,46 +374,52 @@ size_t Print::printULLNumber(unsigned long long n64, uint8_t base) char buf[64]; uint8_t i = 0; uint8_t innerLoops = 0; + size_t bytes = 0; - // prevent crash if called with base == 1 - if (base < 2) { - base = 10; - } - - // process chunks that fit in "16 bit math". - uint16_t top = 0xFFFF / base; - uint16_t th16 = 1; - while (th16 < top) { - th16 *= base; - innerLoops++; - } + // Special case workaround https://github.com/arduino/ArduinoCore-API/issues/178 + if (n64 == 0) { + write('0'); + bytes = 1; + } else { + // prevent crash if called with base == 1 + if (base < 2) { + base = 10; + } - while (n64 > th16) { - // 64 bit math part - uint64_t q = n64 / th16; - uint16_t r = n64 - q * th16; - n64 = q; - - // 16 bit math loop to do remainder. (note buffer is filled reverse) - for (uint8_t j = 0; j < innerLoops; j++) { - uint16_t qq = r / base; - buf[i++] = r - qq * base; - r = qq; + // process chunks that fit in "16 bit math". + uint16_t top = 0xFFFF / base; + uint16_t th16 = 1; + while (th16 < top) { + th16 *= base; + innerLoops++; } - } - uint16_t n16 = n64; - while (n16 > 0) { - uint16_t qq = n16 / base; - buf[i++] = n16 - qq * base; - n16 = qq; - } + while (n64 > th16) { + // 64 bit math part + uint64_t q = n64 / th16; + uint16_t r = n64 - q * th16; + n64 = q; + + // 16 bit math loop to do remainder. (note buffer is filled reverse) + for (uint8_t j = 0; j < innerLoops; j++) { + uint16_t qq = r / base; + buf[i++] = r - qq * base; + r = qq; + } + } - size_t bytes = i; - for (; i > 0; i--) { - write((char)(buf[i - 1] < 10 ? - '0' + buf[i - 1] : - 'A' + buf[i - 1] - 10)); + uint16_t n16 = n64; + while (n16 > 0) { + uint16_t qq = n16 / base; + buf[i++] = n16 - qq * base; + n16 = qq; + } + bytes = i; + for (; i > 0; i--) { + write((char)(buf[i - 1] < 10 ? + '0' + buf[i - 1] : + 'A' + buf[i - 1] - 10)); + } } return bytes; } diff --git a/cores/arduino/WSerial.cpp b/cores/arduino/WSerial.cpp index 948bb432c6..6bb665b0d5 100644 --- a/cores/arduino/WSerial.cpp +++ b/cores/arduino/WSerial.cpp @@ -62,6 +62,11 @@ WEAK void serialEventRun(void) serialEventLP2(); } #endif +#if defined(HAVE_HWSERIALLP3) + if (serialEventLP3 && SerialLP3.available()) { + serialEventLP3(); + } +#endif #if defined(HAVE_SERIALUSB) if (serialEventUSB && SerialUSB.available()) { serialEventUSB(); diff --git a/cores/arduino/WSerial.h b/cores/arduino/WSerial.h index 44aed84409..658ce8a496 100644 --- a/cores/arduino/WSerial.h +++ b/cores/arduino/WSerial.h @@ -56,6 +56,12 @@ #define Serial SerialLP2 #define serialEvent serialEventLP2 #endif + #elif SERIAL_UART_INSTANCE == 103 + #define ENABLE_HWSERIALLP3 + #if !defined(Serial) + #define Serial SerialLP3 + #define serialEvent serialEventLP3 + #endif #elif SERIAL_UART_INSTANCE == 1 #define ENABLE_HWSERIAL1 #if !defined(Serial) @@ -133,6 +139,11 @@ #define HAVE_HWSERIALLP2 #endif #endif + #if defined(ENABLE_HWSERIALLP3) + #if defined(LPUART3_BASE) + #define HAVE_HWSERIALLP3 + #endif + #endif #if defined(ENABLE_HWSERIAL1) #if defined(USART1_BASE) #define HAVE_HWSERIAL1 @@ -220,6 +231,9 @@ #if defined(HAVE_HWSERIALLP2) extern void serialEventLP2(void) __attribute__((weak)); #endif + #if defined(HAVE_HWSERIALLP3) + extern void serialEventLP3(void) __attribute__((weak)); + #endif #endif /* HAL_UART_MODULE_ENABLED && !HAL_UART_MODULE_ONLY */ extern void serialEventRun(void); diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 5ac348f9dd..55026e1682 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -6,6 +6,8 @@ #define CMSIS_STARTUP_FILE "startup_stm32c011xx.s" #elif defined(STM32C031xx) #define CMSIS_STARTUP_FILE "startup_stm32c031xx.s" + #elif defined(STM32C071xx) + #define CMSIS_STARTUP_FILE "startup_stm32c071xx.s" #elif defined(STM32F030x6) #define CMSIS_STARTUP_FILE "startup_stm32f030x6.s" #elif defined(STM32F030x8) @@ -200,6 +202,12 @@ #define CMSIS_STARTUP_FILE "startup_stm32g0b1xx.s" #elif defined(STM32G0C1xx) #define CMSIS_STARTUP_FILE "startup_stm32g0c1xx.s" + #elif defined(STM32G411xB) + #define CMSIS_STARTUP_FILE "startup_stm32g411xb.s" + #elif defined(STM32G411xC) + #define CMSIS_STARTUP_FILE "startup_stm32g411xc.s" + #elif defined(STM32G414xx) + #define CMSIS_STARTUP_FILE "startup_stm32g414xx.s" #elif defined(STM32G431xx) #define CMSIS_STARTUP_FILE "startup_stm32g431xx.s" #elif defined(STM32G441xx) @@ -426,6 +434,12 @@ #define CMSIS_STARTUP_FILE "startup_stm32mp157cxx_cm4.s" #elif defined(STM32MP15xx) #define CMSIS_STARTUP_FILE "startup_stm32mp15xx.s" + #elif defined(STM32U031xx) + #define CMSIS_STARTUP_FILE "startup_stm32u031xx.s" + #elif defined(STM32U073xx) + #define CMSIS_STARTUP_FILE "startup_stm32u073xx.s" + #elif defined(STM32U083xx) + #define CMSIS_STARTUP_FILE "startup_stm32u083xx.s" #elif defined(STM32U535xx) #define CMSIS_STARTUP_FILE "startup_stm32u535xx.s" #elif defined(STM32U545xx) diff --git a/debugger/select_swd.cfg b/debugger/select_swd.cfg new file mode 100644 index 0000000000..d9ec623c2b --- /dev/null +++ b/debugger/select_swd.cfg @@ -0,0 +1,9 @@ +transport select swd + +set ENABLE_LOW_POWER 1 +set STOP_WATCHDOG 1 +set CLOCK_FREQ 4000 + +reset_config none separate + +set CONNECT_UNDER_RESET 1 \ No newline at end of file diff --git a/keywords.txt b/keywords.txt index da0171d435..a4a284e59a 100644 --- a/keywords.txt +++ b/keywords.txt @@ -862,8 +862,7 @@ GPIO_PIN_14 LITERAL1 GPIO_PIN_15 LITERAL1 # HardwareTimer -TIMER_DISABLED LITERAL1 -TIMER_OUTPUT_COMPARE LITERAL1 +TIMER_OUTPUT_DISABLED LITERAL1 TIMER_OUTPUT_COMPARE_ACTIVE LITERAL1 TIMER_OUTPUT_COMPARE_INACTIVE LITERAL1 TIMER_OUTPUT_COMPARE_TOGGLE LITERAL1 diff --git a/libraries/SPI/README.md b/libraries/SPI/README.md index 7a0595c1cc..9a874d7984 100644 --- a/libraries/SPI/README.md +++ b/libraries/SPI/README.md @@ -1,7 +1,7 @@ ## SPI STM32 SPI library has been modified with the possibility to manage hardware CS pin linked to the SPI peripheral. -_We do not describe here the [SPI Arduino API](https://www.arduino.cc/en/Reference/SPI) but the functionalities added._ +_We do not describe here the [SPI Arduino API](https://docs.arduino.cc/language-reference/en/functions/communication/SPI/) but the functionalities added._ User have 2 possibilities about the management of the CS pin: * the CS pin is managed directly by the user code before to transfer the data (like the Arduino SPI library) diff --git a/libraries/SPI/src/SPI.cpp b/libraries/SPI/src/SPI.cpp index 2c6e798b33..f77b48c59b 100644 --- a/libraries/SPI/src/SPI.cpp +++ b/libraries/SPI/src/SPI.cpp @@ -14,26 +14,18 @@ SPIClass SPI; /** - * @brief Default constructor. Uses pin configuration of variant.h. - */ -SPIClass::SPIClass() -{ - _spi.pin_miso = digitalPinToPinName(MISO); - _spi.pin_mosi = digitalPinToPinName(MOSI); - _spi.pin_sclk = digitalPinToPinName(SCK); - _spi.pin_ssel = NC; -} - -/** - * @brief Constructor to create another SPI instance attached to another SPI - * peripheral different of the default SPI. All pins must be attached to - * the same SPI peripheral. See datasheet of the microcontroller. + * @brief Default Constructor. Uses pin configuration of default SPI + * defined in the variant*.h. + * To create another SPI instance attached to another SPI + * peripheral gave the pins as parameters to the constructor. + * @note All pins must be attached to the same SPI peripheral. + * See datasheet of the microcontroller. * @param mosi: SPI mosi pin. Accepted format: number or Arduino format (Dx) - * or ST format (Pxy). + * or ST format (Pxy). Default is MOSI pin of the default SPI peripheral. * @param miso: SPI miso pin. Accepted format: number or Arduino format (Dx) - * or ST format (Pxy). + * or ST format (Pxy). Default is MISO pin of the default SPI peripheral. * @param sclk: SPI clock pin. Accepted format: number or Arduino format (Dx) - * or ST format (Pxy). + * or ST format (Pxy). Default is SCK pin of the default SPI peripheral. * @param ssel: SPI ssel pin (optional). Accepted format: number or * Arduino format (Dx) or ST format (Pxy). By default is set to NC. * This pin must correspond to a hardware CS pin which can be managed @@ -45,6 +37,7 @@ SPIClass::SPIClass() */ SPIClass::SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel) { + memset((void *)&_spi, 0, sizeof(_spi)); _spi.pin_miso = digitalPinToPinName(miso); _spi.pin_mosi = digitalPinToPinName(mosi); _spi.pin_sclk = digitalPinToPinName(sclk); diff --git a/libraries/SPI/src/SPI.h b/libraries/SPI/src/SPI.h index 1105991dc7..a558f5f05c 100644 --- a/libraries/SPI/src/SPI.h +++ b/libraries/SPI/src/SPI.h @@ -84,8 +84,7 @@ class SPISettings { class SPIClass { public: - SPIClass(); - SPIClass(uint32_t mosi, uint32_t miso, uint32_t sclk, uint32_t ssel = PNUM_NOT_DEFINED); + SPIClass(uint32_t mosi = MOSI, uint32_t miso = MISO, uint32_t sclk = SCK, uint32_t ssel = PNUM_NOT_DEFINED); // setMISO/MOSI/SCLK/SSEL have to be called before begin() void setMISO(uint32_t miso) diff --git a/libraries/SPI/src/utility/spi_com.c b/libraries/SPI/src/utility/spi_com.c index 4adeb9d488..6bfd683a53 100644 --- a/libraries/SPI/src/utility/spi_com.c +++ b/libraries/SPI/src/utility/spi_com.c @@ -30,7 +30,8 @@ uint32_t spi_getClkFreqInst(SPI_TypeDef *spi_inst) { uint32_t spi_freq = SystemCoreClock; if (spi_inst != NP) { -#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || \ + defined(STM32U0xx) /* SPIx source CLK is PCKL1 */ spi_freq = HAL_RCC_GetPCLK1Freq(); #else diff --git a/libraries/SrcWrapper/CMakeLists.txt b/libraries/SrcWrapper/CMakeLists.txt index 888647feb7..5377f535a2 100644 --- a/libraries/SrcWrapper/CMakeLists.txt +++ b/libraries/SrcWrapper/CMakeLists.txt @@ -114,6 +114,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL src/HAL/stm32yyxx_hal_sd.c src/HAL/stm32yyxx_hal_sd_ex.c src/HAL/stm32yyxx_hal_sdadc.c + src/HAL/stm32yyxx_hal_sdio.c src/HAL/stm32yyxx_hal_sdram.c src/HAL/stm32yyxx_hal_smartcard.c src/HAL/stm32yyxx_hal_smartcard_ex.c diff --git a/libraries/SrcWrapper/inc/HardwareTimer.h b/libraries/SrcWrapper/inc/HardwareTimer.h index 158e8dbd38..2a5daa3953 100644 --- a/libraries/SrcWrapper/inc/HardwareTimer.h +++ b/libraries/SrcWrapper/inc/HardwareTimer.h @@ -36,9 +36,8 @@ #define TIMER_CHANNELS 4 // channel5 and channel 6 are not considered here has they don't have gpio output and they don't have interrupt typedef enum { - TIMER_DISABLED, // == TIM_OCMODE_TIMING no output, useful for only-interrupt + TIMER_OUTPUT_DISABLED, // == TIM_OCMODE_TIMING no output, useful for only-interrupt // Output Compare - TIMER_OUTPUT_COMPARE, // == Obsolete, use TIMER_DISABLED instead. Kept for compatibility reason TIMER_OUTPUT_COMPARE_ACTIVE, // == TIM_OCMODE_ACTIVE pin is set high when counter == channel compare TIMER_OUTPUT_COMPARE_INACTIVE, // == TIM_OCMODE_INACTIVE pin is set low when counter == channel compare TIMER_OUTPUT_COMPARE_TOGGLE, // == TIM_OCMODE_TOGGLE pin toggles when counter == channel compare @@ -60,6 +59,10 @@ typedef enum { TIMER_NOT_USED = 0xFFFF // This must be the last item of this enum } TimerModes_t; +// Backward compatibility +#define TIMER_DISABLED TIMER_OUTPUT_DISABLED +#define TIMER_OUTPUT_COMPARE TIMER_OUTPUT_DISABLED + typedef enum { TICK_FORMAT, // default MICROSEC_FORMAT, @@ -177,10 +180,10 @@ class HardwareTimer { // The following function(s) are available for more advanced timer options TIM_HandleTypeDef *getHandle(); // return the handle address for HAL related configuration - int getChannel(uint32_t channel); - int getLLChannel(uint32_t channel); - int getIT(uint32_t channel); - int getAssociatedChannel(uint32_t channel); + uint32_t getChannel(uint32_t channel); + uint32_t getLLChannel(uint32_t channel); + uint32_t getIT(uint32_t channel); + uint32_t getAssociatedChannel(uint32_t channel); private: // Store for each channel if regular, complementary or both are used diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h index 7469a19545..abb008e769 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_adc.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_adc.h" #elif STM32MP1xx #include "stm32mp1xx_ll_adc.h" +#elif STM32U0xx + #include "stm32u0xx_ll_adc.h" #elif STM32U5xx #include "stm32u5xx_ll_adc.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h index e27fd52729..00cb84cc6e 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_bus.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_bus.h" #elif STM32MP1xx #include "stm32mp1xx_ll_bus.h" +#elif STM32U0xx + #include "stm32u0xx_ll_bus.h" #elif STM32U5xx #include "stm32u5xx_ll_bus.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h index fb3c8d2b74..d18704b081 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_comp.h @@ -28,6 +28,8 @@ #include "stm32l4xx_ll_comp.h" #elif STM32L5xx #include "stm32l5xx_ll_comp.h" +#elif STM32U0xx + #include "stm32u0xx_ll_comp.h" #elif STM32U5xx #include "stm32u5xx_ll_comp.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h index 8ece363f26..ea5f41b376 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_cortex.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_cortex.h" #elif STM32MP1xx #include "stm32mp1xx_ll_cortex.h" +#elif STM32U0xx + #include "stm32u0xx_ll_cortex.h" #elif STM32U5xx #include "stm32u5xx_ll_cortex.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h index 5a8c391488..ab85bd9324 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crc.h @@ -38,6 +38,8 @@ #include "stm32l4xx_ll_crc.h" #elif STM32L5xx #include "stm32l5xx_ll_crc.h" +#elif STM32U0xx + #include "stm32u0xx_ll_crc.h" #elif STM32U5xx #include "stm32u5xx_ll_crc.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h index 8bd8236bcf..b2e75d6d9f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_crs.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F0xx +#ifdef STM32C0xx + #include "stm32c0xx_ll_crs.h" +#elif STM32F0xx #include "stm32f0xx_ll_crs.h" #elif STM32G0xx #include "stm32g0xx_ll_crs.h" @@ -24,6 +26,8 @@ #include "stm32l4xx_ll_crs.h" #elif STM32L5xx #include "stm32l5xx_ll_crs.h" +#elif STM32U0xx + #include "stm32u0xx_ll_crs.h" #elif STM32U5xx #include "stm32u5xx_ll_crs.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h index e121981cf7..99c545e85f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dac.h @@ -36,6 +36,8 @@ #include "stm32l4xx_ll_dac.h" #elif STM32L5xx #include "stm32l5xx_ll_dac.h" +#elif STM32U0xx + #include "stm32u0xx_ll_dac.h" #elif STM32U5xx #include "stm32u5xx_ll_dac.h" #elif STM32WLxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h index ec71d34c54..ae62053dc3 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dma.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_dma.h" #elif STM32MP1xx #include "stm32mp1xx_ll_dma.h" +#elif STM32U0xx + #include "stm32u0xx_ll_dma.h" #elif STM32U5xx #include "stm32u5xx_ll_dma.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h index 2ea932be4f..85bbdda541 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_dmamux.h @@ -22,6 +22,8 @@ #include "stm32l5xx_ll_dmamux.h" #elif STM32MP1xx #include "stm32mp1xx_ll_dmamux.h" +#elif STM32U0xx + #include "stm32u0xx_ll_dmamux.h" #elif STM32WBxx #include "stm32wbxx_ll_dmamux.h" #elif STM32WLxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h index 826b8eb513..ec683e0b57 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_exti.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_exti.h" #elif STM32MP1xx #include "stm32mp1xx_ll_exti.h" +#elif STM32U0xx + #include "stm32u0xx_ll_exti.h" #elif STM32U5xx #include "stm32u5xx_ll_exti.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h index 7e5d262e4a..d5ca0a4cfa 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_gpio.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_gpio.h" #elif STM32MP1xx #include "stm32mp1xx_ll_gpio.h" +#elif STM32U0xx + #include "stm32u0xx_ll_gpio.h" #elif STM32U5xx #include "stm32u5xx_ll_gpio.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h index 298956a73f..1adf3c3645 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_i2c.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_i2c.h" #elif STM32MP1xx #include "stm32mp1xx_ll_i2c.h" +#elif STM32U0xx + #include "stm32u0xx_ll_i2c.h" #elif STM32U5xx #include "stm32u5xx_ll_i2c.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h index 9c2a009386..1fab9bc430 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_iwdg.h @@ -38,6 +38,8 @@ #include "stm32l4xx_ll_iwdg.h" #elif STM32L5xx #include "stm32l5xx_ll_iwdg.h" +#elif STM32U0xx + #include "stm32u0xx_ll_iwdg.h" #elif STM32U5xx #include "stm32u5xx_ll_iwdg.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h index fb86d8bf52..90b3225e65 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lptim.h @@ -28,6 +28,8 @@ #include "stm32l5xx_ll_lptim.h" #elif STM32MP1xx #include "stm32mp1xx_ll_lptim.h" +#elif STM32U0xx + #include "stm32u0xx_ll_lptim.h" #elif STM32U5xx #include "stm32u5xx_ll_lptim.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h index 3b3d880de9..277a2c88be 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_lpuart.h @@ -22,6 +22,8 @@ #include "stm32l4xx_ll_lpuart.h" #elif STM32L5xx #include "stm32l5xx_ll_lpuart.h" +#elif STM32U0xx + #include "stm32u0xx_ll_lpuart.h" #elif STM32U5xx #include "stm32u5xx_ll_lpuart.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h index c13b074b6c..92988a241c 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_opamp.h @@ -22,6 +22,8 @@ #include "stm32l4xx_ll_opamp.h" #elif STM32L5xx #include "stm32l5xx_ll_opamp.h" +#elif STM32U0xx + #include "stm32u0xx_ll_opamp.h" #elif STM32U5xx #include "stm32u5xx_ll_opamp.h" #endif diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h index df1367df3e..788f8198a0 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_pwr.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_pwr.h" #elif STM32MP1xx #include "stm32mp1xx_ll_pwr.h" +#elif STM32U0xx + #include "stm32u0xx_ll_pwr.h" #elif STM32U5xx #include "stm32u5xx_ll_pwr.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h index bd613a4ba7..ec55e1057b 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rcc.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_rcc.h" #elif STM32MP1xx #include "stm32mp1xx_ll_rcc.h" +#elif STM32U0xx + #include "stm32u0xx_ll_rcc.h" #elif STM32U5xx #include "stm32u5xx_ll_rcc.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h index 34a6f8747c..4598966112 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rng.h @@ -28,6 +28,8 @@ #include "stm32l4xx_ll_rng.h" #elif STM32L5xx #include "stm32l5xx_ll_rng.h" +#elif STM32U0xx + #include "stm32u0xx_ll_rng.h" #elif STM32U5xx #include "stm32u5xx_ll_rng.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h index 0ee36f5a27..0576f29536 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_rtc.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_rtc.h" #elif STM32MP1xx #include "stm32mp1xx_ll_rtc.h" +#elif STM32U0xx + #include "stm32u0xx_ll_rtc.h" #elif STM32U5xx #include "stm32u5xx_ll_rtc.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h index 53e172a32b..d502f09639 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_spi.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_spi.h" #elif STM32MP1xx #include "stm32mp1xx_ll_spi.h" +#elif STM32U0xx + #include "stm32u0xx_ll_spi.h" #elif STM32U5xx #include "stm32u5xx_ll_spi.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h index 4b2eea4b10..1822b2d8a8 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_system.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_system.h" #elif STM32MP1xx #include "stm32mp1xx_ll_system.h" +#elif STM32U0xx + #include "stm32u0xx_ll_system.h" #elif STM32U5xx #include "stm32u5xx_ll_system.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h index 7f8aa0a1ee..e2acfff906 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_tim.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_tim.h" #elif STM32MP1xx #include "stm32mp1xx_ll_tim.h" +#elif STM32U0xx + #include "stm32u0xx_ll_tim.h" #elif STM32U5xx #include "stm32u5xx_ll_tim.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h index 3e2686ee9f..d43d454b8a 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usart.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_usart.h" #elif STM32MP1xx #include "stm32mp1xx_ll_usart.h" +#elif STM32U0xx + #include "stm32u0xx_ll_usart.h" #elif STM32U5xx #include "stm32u5xx_ll_usart.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usb.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usb.h index 43f41d3724..2b44476b8f 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usb.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_usb.h @@ -8,7 +8,9 @@ #pragma GCC diagnostic ignored "-Wregister" #endif -#ifdef STM32F0xx +#ifdef STM32C0xx + #include "stm32c0xx_ll_usb.h" +#elif STM32F0xx #include "stm32f0xx_ll_usb.h" #elif STM32F1xx #include "stm32f1xx_ll_usb.h" @@ -36,6 +38,8 @@ #include "stm32l4xx_ll_usb.h" #elif STM32L5xx #include "stm32l5xx_ll_usb.h" +#elif STM32U0xx + #include "stm32u0xx_ll_usb.h" #elif STM32U5xx #include "stm32u5xx_ll_usb.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h index c290596002..e5b2f03b99 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_utils.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_utils.h" #elif STM32MP1xx #include "stm32mp1xx_ll_utils.h" +#elif STM32U0xx + #include "stm32u0xx_ll_utils.h" #elif STM32U5xx #include "stm32u5xx_ll_utils.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h index c674adf268..28bc30252a 100644 --- a/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h +++ b/libraries/SrcWrapper/inc/LL/stm32yyxx_ll_wwdg.h @@ -40,6 +40,8 @@ #include "stm32l5xx_ll_wwdg.h" #elif STM32MP1xx #include "stm32mp1xx_ll_wwdg.h" +#elif STM32U0xx + #include "stm32u0xx_ll_wwdg.h" #elif STM32U5xx #include "stm32u5xx_ll_wwdg.h" #elif STM32WBxx diff --git a/libraries/SrcWrapper/inc/stm32_def.h b/libraries/SrcWrapper/inc/stm32_def.h index a307d748aa..9d073f3b06 100644 --- a/libraries/SrcWrapper/inc/stm32_def.h +++ b/libraries/SrcWrapper/inc/stm32_def.h @@ -6,8 +6,8 @@ * @brief STM32 core version number */ #define STM32_CORE_VERSION_MAJOR (0x02U) /*!< [31:24] major version */ -#define STM32_CORE_VERSION_MINOR (0x08U) /*!< [23:16] minor version */ -#define STM32_CORE_VERSION_PATCH (0x01U) /*!< [15:8] patch version */ +#define STM32_CORE_VERSION_MINOR (0x09U) /*!< [23:16] minor version */ +#define STM32_CORE_VERSION_PATCH (0x00U) /*!< [15:8] patch version */ /* * Extra label for development: * 0: official release @@ -52,6 +52,8 @@ #include "stm32l5xx.h" #elif defined(STM32MP1xx) #include "stm32mp1xx.h" +#elif defined(STM32U0xx) + #include "stm32u0xx.h" #elif defined(STM32U5xx) #include "stm32u5xx.h" #elif defined(STM32WBxx) @@ -88,11 +90,103 @@ #endif #endif -/* STM32G0xx and some STM32U5xx defined USB_DRD_FS */ +#if defined(STM32U0xx) +#define RCC_CR_HSIDY_Pos RCC_CR_HSIRDY_Pos +#include "stm32yyxx_ll_rtc.h" +#if !defined(LL_RTC_BINARY_NONE) + #define LL_RTC_BINARY_NONE RTC_BINARY_NONE +#endif +#if !defined(LL_RTC_BINARY_ONLY) + #define LL_RTC_BINARY_ONLY RTC_BINARY_ONLY +#endif +#if !defined(LL_RTC_BINARY_MIX) + #define LL_RTC_BINARY_MIX RTC_BINARY_MIX +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_0) + #define LL_RTC_BINARY_MIX_BCDU_0 RTC_BINARY_MIX_BCDU_0 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_1) + #define LL_RTC_BINARY_MIX_BCDU_1 RTC_BINARY_MIX_BCDU_1 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_2) + #define LL_RTC_BINARY_MIX_BCDU_2 RTC_BINARY_MIX_BCDU_2 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_3) + #define LL_RTC_BINARY_MIX_BCDU_3 RTC_BINARY_MIX_BCDU_3 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_4) + #define LL_RTC_BINARY_MIX_BCDU_4 RTC_BINARY_MIX_BCDU_4 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_5) + #define LL_RTC_BINARY_MIX_BCDU_5 RTC_BINARY_MIX_BCDU_5 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_6) + #define LL_RTC_BINARY_MIX_BCDU_6 RTC_BINARY_MIX_BCDU_6 +#endif +#if !defined(LL_RTC_BINARY_MIX_BCDU_7) + #define LL_RTC_BINARY_MIX_BCDU_7 RTC_BINARY_MIX_BCDU_7 +#endif + +/** + * @brief Get Binary mode (Sub Second Register) + * @rmtoll RTC_ICSR BIN LL_RTC_GetBinaryMode + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN)); +} + +/** + * @brief Set Binary mode (Sub Second Register) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BIN LL_RTC_SetBinaryMode + * @param RTCx RTC Instance + * @param BinaryMode can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode); +} + +/** + * @brief Set Binary Mix mode BCDU + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BCDU LL_RTC_SetBinMixBCDU + * @param RTCx RTC Instance + * @param BinMixBcdU can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU); +} +#endif // STM32U0xx + +/* STM32G0xx, STM32U0xx and some STM32U5xx defined USB_DRD_FS */ #if !defined(USB) && defined(USB_DRD_FS) #define USB USB_DRD_FS #define PinMap_USB PinMap_USB_DRD_FS - #if defined(STM32H5xx) || defined(STM32U5xx) + #if defined(STM32H5xx) || defined(STM32U0xx) || defined(STM32U5xx) #define USB_BASE USB_DRD_BASE #if !defined(__HAL_RCC_USB_CLK_ENABLE) #define __HAL_RCC_USB_CLK_ENABLE __HAL_RCC_USB_FS_CLK_ENABLE diff --git a/libraries/SrcWrapper/inc/timer.h b/libraries/SrcWrapper/inc/timer.h index 7ce0941ff8..f0b52b01b1 100644 --- a/libraries/SrcWrapper/inc/timer.h +++ b/libraries/SrcWrapper/inc/timer.h @@ -37,7 +37,8 @@ extern "C" { #endif #if defined(TIM1_BASE) && !defined(TIM1_IRQn) -#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) ||\ + defined(STM32U0xx) #define TIM1_IRQn TIM1_BRK_UP_TRG_COM_IRQn #define TIM1_IRQHandler TIM1_BRK_UP_TRG_COM_IRQHandler #elif defined(STM32F1xx) ||defined(STM32G4xx) @@ -82,7 +83,7 @@ extern "C" { #if defined(TIM6_BASE) && !defined(TIM6_IRQn) #if defined(DAC_BASE) || defined(DAC1_BASE) -#if defined(STM32G0xx) +#if defined(STM32G0xx) || defined(STM32U0xx) #define TIM6_IRQn TIM6_DAC_LPTIM1_IRQn #define TIM6_IRQHandler TIM6_DAC_LPTIM1_IRQHandler #elif !defined(STM32F1xx) && !defined(STM32H5xx) && !defined(STM32L1xx) &&\ @@ -94,7 +95,7 @@ extern "C" { #endif #if defined(TIM7_BASE) && !defined(TIM7_IRQn) -#if defined(STM32G0xx) && defined(LPTIM2_BASE) +#if (defined(STM32G0xx) || defined(STM32U0xx)) && defined(LPTIM2_BASE) #define TIM7_IRQn TIM7_LPTIM2_IRQn #define TIM7_IRQHandler TIM7_LPTIM2_IRQHandler #elif defined(STM32G4xx) @@ -159,6 +160,10 @@ extern "C" { #define TIM15_IRQn TIM1_BRK_TIM15_IRQn #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler #endif +#if defined(STM32U0xx) && defined(LPTIM3_BASE) +#define TIM15_IRQn TIM15_LPTIM3_IRQn +#define TIM15_IRQHandler TIM15_LPTIM3_IRQHandler +#endif #endif #if defined(TIM16_BASE) && !defined(TIM16_IRQn) #if defined(STM32F1xx) || defined(STM32F3xx) || defined(STM32G4xx) || defined(STM32L4xx) || \ diff --git a/libraries/SrcWrapper/inc/uart.h b/libraries/SrcWrapper/inc/uart.h index 2a8537f45c..a6c41390e7 100644 --- a/libraries/SrcWrapper/inc/uart.h +++ b/libraries/SrcWrapper/inc/uart.h @@ -100,7 +100,7 @@ struct serial_s { #endif #if defined(USART2_BASE) && !defined(USART2_IRQn) -#if defined(STM32G0xx) +#if defined(STM32G0xx) || defined(STM32U0xx) #if defined(LPUART2_BASE) #define USART2_IRQn USART2_LPUART2_IRQn #define USART2_IRQHandler USART2_LPUART2_IRQHandler @@ -134,6 +134,9 @@ struct serial_s { #define USART3_IRQn USART3_4_IRQn #define USART3_IRQHandler USART3_4_IRQHandler #endif +#elif defined(STM32U0xx) +#define USART3_IRQn USART3_LPUART1_IRQn +#define USART3_IRQHandler USART3_LPUART1_IRQHandler #endif /* STM32F0xx */ #endif @@ -159,6 +162,11 @@ struct serial_s { #else #define USART4_IRQn USART3_4_IRQn #endif +#elif defined(STM32U0xx) +#if defined(LPUART3_BASE) +#define USART4_IRQn USART4_LPUART3_IRQn +#define USART4_IRQHandler USART4_LPUART3_IRQHandler +#endif /* LPUART3_BASE */ #endif /* STM32G0xx */ #endif @@ -222,6 +230,9 @@ struct serial_s { #define LPUART1_IRQn USART3_4_LPUART1_IRQn #endif #endif /* STM32G0xx */ +#if defined(STM32U0xx) +#define LPUART1_IRQn USART3_LPUART1_IRQn +#endif /* STM32U0xx */ #endif #if defined(LPUART2_BASE) && !defined(LPUART2_IRQn) @@ -230,6 +241,15 @@ struct serial_s { #define LPUART2_IRQn USART2_LPUART2_IRQn #endif #endif /* STM32G0xx */ +#if defined(STM32U0xx) +#define LPUART2_IRQn USART2_LPUART2_IRQn +#endif /* STM32U0xx */ +#endif + +#if defined(LPUART3_BASE) && !defined(LPUART3_IRQn) +#if defined(STM32U0xx) +#define LPUART3_IRQn USART4_LPUART3_IRQn +#endif /* STM32U0xx */ #endif /* Exported macro ------------------------------------------------------------*/ diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c index eea39cec0a..937fbd342c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c @@ -36,6 +36,8 @@ #include "stm32l5xx_hal.c" #elif STM32MP1xx #include "stm32mp1xx_hal.c" +#elif STM32U0xx + #include "stm32u0xx_hal.c" #elif STM32U5xx #include "stm32u5xx_hal.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c index 8e8a9218e1..8849ea895d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_adc.c" #elif STM32MP1xx #include "stm32mp1xx_hal_adc.c" +#elif STM32U0xx + #include "stm32u0xx_hal_adc.c" #elif STM32U5xx #include "stm32u5xx_hal_adc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c index bb702d7ec6..0589032f8f 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_adc_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_adc_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_adc_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_adc_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c index 6e08e521ff..36f108b32e 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c @@ -22,6 +22,8 @@ #include "stm32l4xx_hal_comp.c" #elif STM32L5xx #include "stm32l5xx_hal_comp.c" +#elif STM32U0xx + #include "stm32u0xx_hal_comp.c" #elif STM32U5xx #include "stm32u5xx_hal_comp.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c index 9ab250a266..f59e003459 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_cortex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_cortex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_cortex.c" #elif STM32U5xx #include "stm32u5xx_hal_cortex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c index 0f89a23176..8b98859a25 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_crc.c" #elif STM32MP1xx #include "stm32mp1xx_hal_crc.c" +#elif STM32U0xx + #include "stm32u0xx_hal_crc.c" #elif STM32U5xx #include "stm32u5xx_hal_crc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c index 9879d990a6..dfb2fe71b2 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c @@ -26,6 +26,8 @@ #include "stm32l5xx_hal_crc_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_crc_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_crc_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_crc_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c index 3093fa8f64..06463a7e76 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c @@ -26,6 +26,8 @@ #include "stm32l5xx_hal_cryp.c" #elif STM32MP1xx #include "stm32mp1xx_hal_cryp.c" +#elif STM32U0xx + #include "stm32u0xx_hal_cryp.c" #elif STM32U5xx #include "stm32u5xx_hal_cryp.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c index a6c18f4a04..cfc90950ee 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c @@ -24,6 +24,8 @@ #include "stm32l5xx_hal_cryp_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_cryp_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_cryp_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_cryp_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c index c4d0bfc134..ccfdf05c09 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac.c @@ -32,6 +32,8 @@ #include "stm32l5xx_hal_dac.c" #elif STM32MP1xx #include "stm32mp1xx_hal_dac.c" +#elif STM32U0xx + #include "stm32u0xx_hal_dac.c" #elif STM32U5xx #include "stm32u5xx_hal_dac.c" #elif STM32WLxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c index 822ed08daa..b173fed36a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dac_ex.c @@ -32,6 +32,8 @@ #include "stm32l5xx_hal_dac_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_dac_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_dac_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_dac_ex.c" #elif STM32WLxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c index c30a0752a3..7ca4083d86 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_dma.c" #elif STM32MP1xx #include "stm32mp1xx_hal_dma.c" +#elif STM32U0xx + #include "stm32u0xx_hal_dma.c" #elif STM32U5xx #include "stm32u5xx_hal_dma.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c index b0a512159f..5ef36e7cfe 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c @@ -24,6 +24,8 @@ #include "stm32l5xx_hal_dma_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_dma_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_dma_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_dma_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c index bd73d21953..f3ed583cde 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_exti.c" #elif STM32MP1xx #include "stm32mp1xx_hal_exti.c" +#elif STM32U0xx + #include "stm32u0xx_hal_exti.c" #elif STM32U5xx #include "stm32u5xx_hal_exti.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c index dcc93f730d..92e0c3429b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c @@ -32,6 +32,8 @@ #include "stm32l4xx_hal_flash.c" #elif STM32L5xx #include "stm32l5xx_hal_flash.c" +#elif STM32U0xx + #include "stm32u0xx_hal_flash.c" #elif STM32U5xx #include "stm32u5xx_hal_flash.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c index 45a01e02b7..ed3f26fc30 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c @@ -32,6 +32,8 @@ #include "stm32l4xx_hal_flash_ex.c" #elif STM32L5xx #include "stm32l5xx_hal_flash_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_flash_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_flash_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c index db30784153..036b6ad515 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_gpio.c" #elif STM32MP1xx #include "stm32mp1xx_hal_gpio.c" +#elif STM32U0xx + #include "stm32u0xx_hal_gpio.c" #elif STM32U5xx #include "stm32u5xx_hal_gpio.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c index 7a82631a08..5d4135cf85 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hcd.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F1xx +#ifdef STM32C0xx + #include "stm32c0xx_hal_hcd.c" +#elif STM32F1xx #include "stm32f1xx_hal_hcd.c" #elif STM32F2xx #include "stm32f2xx_hal_hcd.c" diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c index 6cccae82a5..6e0ddd1090 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_i2c.c" #elif STM32MP1xx #include "stm32mp1xx_hal_i2c.c" +#elif STM32U0xx + #include "stm32u0xx_hal_i2c.c" #elif STM32U5xx #include "stm32u5xx_hal_i2c.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c index c527eb3ade..3eedd56b97 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c @@ -28,6 +28,8 @@ #include "stm32l5xx_hal_i2c_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_i2c_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_i2c_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_i2c_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c index 1ea4a2399b..17b3fafa03 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c @@ -32,6 +32,8 @@ #include "stm32l4xx_hal_irda.c" #elif STM32L5xx #include "stm32l5xx_hal_irda.c" +#elif STM32U0xx + #include "stm32u0xx_hal_irda.c" #elif STM32U5xx #include "stm32u5xx_hal_irda.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c index be9c3e93f4..15cfa4c63a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c @@ -32,6 +32,8 @@ #include "stm32l4xx_hal_iwdg.c" #elif STM32L5xx #include "stm32l5xx_hal_iwdg.c" +#elif STM32U0xx + #include "stm32u0xx_hal_iwdg.c" #elif STM32U5xx #include "stm32u5xx_hal_iwdg.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c index 7322e81716..2f48bd72d8 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lcd.c @@ -8,6 +8,8 @@ #include "stm32l1xx_hal_lcd.c" #elif STM32L4xx #include "stm32l4xx_hal_lcd.c" +#elif STM32U0xx + #include "stm32u0xx_hal_lcd.c" #elif STM32WBxx #include "stm32wbxx_hal_lcd.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c index c1c7659250..978c5a3fdd 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c @@ -22,6 +22,8 @@ #include "stm32l5xx_hal_lptim.c" #elif STM32MP1xx #include "stm32mp1xx_hal_lptim.c" +#elif STM32U0xx + #include "stm32u0xx_hal_lptim.c" #elif STM32U5xx #include "stm32u5xx_hal_lptim.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c index 361a482037..ddc6eecf8c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp.c @@ -16,6 +16,8 @@ #include "stm32l4xx_hal_opamp.c" #elif STM32L5xx #include "stm32l5xx_hal_opamp.c" +#elif STM32U0xx + #include "stm32u0xx_hal_opamp.c" #elif STM32U5xx #include "stm32u5xx_hal_opamp.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp_ex.c index 57a2422efe..4de228d398 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_opamp_ex.c @@ -16,6 +16,8 @@ #include "stm32l4xx_hal_opamp_ex.c" #elif STM32L5xx #include "stm32l5xx_hal_opamp_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_opamp_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_opamp_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c index 700ef0043b..d6f61c457b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F0xx +#ifdef STM32C0xx + #include "stm32c0xx_hal_pcd.c" +#elif STM32F0xx #include "stm32f0xx_hal_pcd.c" #elif STM32F1xx #include "stm32f1xx_hal_pcd.c" @@ -30,6 +32,8 @@ #include "stm32l4xx_hal_pcd.c" #elif STM32L5xx #include "stm32l5xx_hal_pcd.c" +#elif STM32U0xx + #include "stm32u0xx_hal_pcd.c" #elif STM32U5xx #include "stm32u5xx_hal_pcd.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd_ex.c index bd144c5c8f..7b2568a4f2 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pcd_ex.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F0xx +#ifdef STM32C0xx + #include "stm32c0xx_hal_pcd_ex.c" +#elif STM32F0xx #include "stm32f0xx_hal_pcd_ex.c" #elif STM32F1xx #include "stm32f1xx_hal_pcd_ex.c" @@ -30,6 +32,8 @@ #include "stm32l4xx_hal_pcd_ex.c" #elif STM32L5xx #include "stm32l5xx_hal_pcd_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_pcd_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_pcd_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c index da93008e4a..de5fc46ff5 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_pwr.c" #elif STM32MP1xx #include "stm32mp1xx_hal_pwr.c" +#elif STM32U0xx + #include "stm32u0xx_hal_pwr.c" #elif STM32U5xx #include "stm32u5xx_hal_pwr.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c index 53935ad857..348cb30431 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c @@ -32,6 +32,8 @@ #include "stm32l5xx_hal_pwr_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_pwr_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_pwr_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_pwr_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c index e8b19bb48c..e2946c13c5 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_rcc.c" #elif STM32MP1xx #include "stm32mp1xx_hal_rcc.c" +#elif STM32U0xx + #include "stm32u0xx_hal_rcc.c" #elif STM32U5xx #include "stm32u5xx_hal_rcc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c index b7136950ca..13d0c045f0 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_rcc_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_rcc_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_rcc_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_rcc_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c index 7ff451dd39..22ad0cfac0 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c @@ -24,6 +24,8 @@ #include "stm32l5xx_hal_rng.c" #elif STM32MP1xx #include "stm32mp1xx_hal_rng.c" +#elif STM32U0xx + #include "stm32u0xx_hal_rng.c" #elif STM32U5xx #include "stm32u5xx_hal_rng.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c index d548a5b6b0..c7f4645513 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c @@ -10,6 +10,8 @@ #include "stm32l4xx_hal_rng_ex.c" #elif STM32L5xx #include "stm32l5xx_hal_rng_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_rng_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_rng_ex.c" #elif STM32WBAxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c index 16d2b6bd23..f946b5a666 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_rtc.c" #elif STM32MP1xx #include "stm32mp1xx_hal_rtc.c" +#elif STM32U0xx + #include "stm32u0xx_hal_rtc.c" #elif STM32U5xx #include "stm32u5xx_hal_rtc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c index 0ea69b3906..c1561310f4 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_rtc_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_rtc_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_rtc_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_rtc_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c new file mode 100644 index 0000000000..2a9e696c39 --- /dev/null +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sdio.c @@ -0,0 +1,8 @@ +/* HAL raised several warnings, ignore them */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#ifdef STM32U5xx + #include "stm32u5xx_hal_sdio.c" +#endif +#pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c index a2b3f60d71..04476b5548 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_smartcard.c" #elif STM32MP1xx #include "stm32mp1xx_hal_smartcard.c" +#elif STM32U0xx + #include "stm32u0xx_hal_smartcard.c" #elif STM32U5xx #include "stm32u5xx_hal_smartcard.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c index 4728afa4d1..095114fd11 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c @@ -26,6 +26,8 @@ #include "stm32l5xx_hal_smartcard_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_smartcard_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_smartcard_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_smartcard_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c index d2ad9ce026..51396f9362 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_spi.c" #elif STM32MP1xx #include "stm32mp1xx_hal_spi.c" +#elif STM32U0xx + #include "stm32u0xx_hal_spi.c" #elif STM32U5xx #include "stm32u5xx_hal_spi.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c index 207d51c808..e993dc26a6 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c @@ -24,6 +24,8 @@ #include "stm32l5xx_hal_spi_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_spi_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_spi_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_spi_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c index eebb60a48f..d2806a7301 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_tim.c" #elif STM32MP1xx #include "stm32mp1xx_hal_tim.c" +#elif STM32U0xx + #include "stm32u0xx_hal_tim.c" #elif STM32U5xx #include "stm32u5xx_hal_tim.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c index fcab96885e..cfeb25ff7d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_tim_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_tim_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_tim_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_tim_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c index c964318e61..fc297e83f2 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c @@ -12,6 +12,8 @@ #include "stm32l4xx_hal_tsc.c" #elif STM32L5xx #include "stm32l5xx_hal_tsc.c" +#elif STM32U0xx + #include "stm32u0xx_hal_tsc.c" #elif STM32U5xx #include "stm32u5xx_hal_tsc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c index 50d34509b3..9cbc459c0a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_uart.c" #elif STM32MP1xx #include "stm32mp1xx_hal_uart.c" +#elif STM32U0xx + #include "stm32u0xx_hal_uart.c" #elif STM32U5xx #include "stm32u5xx_hal_uart.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c index 399b417b67..eb056135c3 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c @@ -26,6 +26,8 @@ #include "stm32l5xx_hal_uart_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_uart_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_uart_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_uart_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c index 8ddc53370b..192c34e747 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_usart.c" #elif STM32MP1xx #include "stm32mp1xx_hal_usart.c" +#elif STM32U0xx + #include "stm32u0xx_hal_usart.c" #elif STM32U5xx #include "stm32u5xx_hal_usart.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c index 2643bef3cd..b4c704bb23 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c @@ -22,6 +22,8 @@ #include "stm32l5xx_hal_usart_ex.c" #elif STM32MP1xx #include "stm32mp1xx_hal_usart_ex.c" +#elif STM32U0xx + #include "stm32u0xx_hal_usart_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_usart_ex.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c index 1e0e040f68..b929989ebc 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c @@ -34,6 +34,8 @@ #include "stm32l5xx_hal_wwdg.c" #elif STM32MP1xx #include "stm32mp1xx_hal_wwdg.c" +#elif STM32U0xx + #include "stm32u0xx_hal_wwdg.c" #elif STM32U5xx #include "stm32u5xx_hal_wwdg.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/HardwareTimer.cpp b/libraries/SrcWrapper/src/HardwareTimer.cpp index 2aca499a72..be95bbf5ab 100644 --- a/libraries/SrcWrapper/src/HardwareTimer.cpp +++ b/libraries/SrcWrapper/src/HardwareTimer.cpp @@ -123,7 +123,7 @@ void HardwareTimer::setup(TIM_TypeDef *instance) // Initialize channel mode and complementary for (int i = 0; i < TIMER_CHANNELS; i++) { __ChannelsUsed[i] = 0x00; - _ChannelMode[i] = TIMER_DISABLED; + _ChannelMode[i] = TIMER_OUTPUT_DISABLED; } /* Configure timer with some default values */ @@ -181,9 +181,9 @@ void HardwareTimer::pauseChannel(uint32_t channel) return; } - int timAssociatedInputChannel; - int LLChannel = getLLChannel(channel); - int interrupt = getIT(channel); + uint32_t timAssociatedInputChannel; + uint32_t LLChannel = getLLChannel(channel); + uint32_t interrupt = getIT(channel); // Disable channel and corresponding interrupt __HAL_TIM_DISABLE_IT(&(_timerObj.handle), interrupt); @@ -217,20 +217,23 @@ void HardwareTimer::pauseChannel(uint32_t channel) */ void HardwareTimer::resume(void) { + bool baseStart = true; + for (uint8_t i = 1; i <= TIMER_CHANNELS; i++) { + if (_ChannelMode[i - 1] != TIMER_OUTPUT_DISABLED) { + resumeChannel(i); + baseStart = false; + } + } // Clear flag and enable IT if (callbacks[0]) { __HAL_TIM_CLEAR_FLAG(&(_timerObj.handle), TIM_FLAG_UPDATE); __HAL_TIM_ENABLE_IT(&(_timerObj.handle), TIM_IT_UPDATE); + } - // Start timer in Time base mode. Required when there is no channel used but only update interrupt. + // Start timer in Time base mode. Required when there is no channel used but only update interrupt. + if (baseStart && (!LL_TIM_IsEnabledCounter(_timerObj.handle.Instance))) { HAL_TIM_Base_Start(&(_timerObj.handle)); } - - // Resume all channels - resumeChannel(1); - resumeChannel(2); - resumeChannel(3); - resumeChannel(4); } /** @@ -238,27 +241,27 @@ void HardwareTimer::resume(void) * @param Arduino channel [1..4] * @retval HAL channel. Error handler called if arduino channel is invalid */ -int HardwareTimer::getChannel(uint32_t channel) +uint32_t HardwareTimer::getChannel(uint32_t channel) { - int return_value = -1; + uint32_t timChannel = -1; switch (channel) { case 1: - return_value = TIM_CHANNEL_1; + timChannel = TIM_CHANNEL_1; break; case 2: - return_value = TIM_CHANNEL_2; + timChannel = TIM_CHANNEL_2; break; case 3: - return_value = TIM_CHANNEL_3; + timChannel = TIM_CHANNEL_3; break; case 4: - return_value = TIM_CHANNEL_4; + timChannel = TIM_CHANNEL_4; break; default: Error_Handler(); } - return return_value; + return timChannel; } /** @@ -266,56 +269,57 @@ int HardwareTimer::getChannel(uint32_t channel) * @param Arduino channel [1..4] * @retval LL channel. Error handler called if arduino channel is invalid */ -int HardwareTimer::getLLChannel(uint32_t channel) +uint32_t HardwareTimer::getLLChannel(uint32_t channel) { - int return_value = 0; + bool error = false; + uint32_t ll_channel = 0; #if defined(TIM_CCER_CC1NE) if (__ChannelsUsed[channel - 1] & COMPLEMENTARY_CHAN_MASK) { // Complementary channel switch (channel) { case 1: - return_value = LL_TIM_CHANNEL_CH1N; + ll_channel = LL_TIM_CHANNEL_CH1N; break; case 2: - return_value = LL_TIM_CHANNEL_CH2N; + ll_channel = LL_TIM_CHANNEL_CH2N; break; case 3: - return_value = LL_TIM_CHANNEL_CH3N; + ll_channel = LL_TIM_CHANNEL_CH3N; break; #if defined(LL_TIM_CHANNEL_CH4N) case 4: - return_value = LL_TIM_CHANNEL_CH4N; + ll_channel = LL_TIM_CHANNEL_CH4N; break; #endif default: - return_value = -1; + error = true; } } #endif - if ((return_value != -1) && (__ChannelsUsed[channel - 1] & REGULAR_CHAN_MASK)) { + if ((!error) && (__ChannelsUsed[channel - 1] & REGULAR_CHAN_MASK)) { // Regular channel not complementary switch (channel) { case 1: - return_value |= LL_TIM_CHANNEL_CH1; + ll_channel |= LL_TIM_CHANNEL_CH1; break; case 2: - return_value |= LL_TIM_CHANNEL_CH2; + ll_channel |= LL_TIM_CHANNEL_CH2; break; case 3: - return_value |= LL_TIM_CHANNEL_CH3; + ll_channel |= LL_TIM_CHANNEL_CH3; break; case 4: - return_value |= LL_TIM_CHANNEL_CH4; + ll_channel |= LL_TIM_CHANNEL_CH4; break; default: - return_value = -1; + error = true; } } - if (return_value == -1) { + if (error) { Error_Handler(); } - return return_value; + return ll_channel; } /** @@ -323,38 +327,37 @@ int HardwareTimer::getLLChannel(uint32_t channel) * @param Arduino channel [1..4] * @retval HAL channel. Error handler called if arduino channel is invalid */ -int HardwareTimer::getIT(uint32_t channel) +uint32_t HardwareTimer::getIT(uint32_t channel) { - int return_value = -1; - + uint32_t interrupt = 0; switch (channel) { case 1: - return_value = TIM_IT_CC1; + interrupt = TIM_IT_CC1; break; case 2: - return_value = TIM_IT_CC2; + interrupt = TIM_IT_CC2; break; case 3: - return_value = TIM_IT_CC3; + interrupt = TIM_IT_CC3; break; case 4: - return_value = TIM_IT_CC4; + interrupt = TIM_IT_CC4; break; default: Error_Handler(); } - return return_value; + return interrupt; } /** * @brief Get input associated channel * Channel 1 and 2 are associated; channel 3 and 4 are associated * @param Arduino channel [1..4] - * @retval HAL channel. return -1 if arduino channel is invalid + * @retval HAL channel. Error handler called if arduino channel is invalid */ -int HardwareTimer::getAssociatedChannel(uint32_t channel) +uint32_t HardwareTimer::getAssociatedChannel(uint32_t channel) { - int timAssociatedInputChannel = -1; + uint32_t timAssociatedInputChannel = 0; switch (channel) { case 1: timAssociatedInputChannel = 2; @@ -369,6 +372,7 @@ int HardwareTimer::getAssociatedChannel(uint32_t channel) timAssociatedInputChannel = 3; break; default: + Error_Handler(); break; } return timAssociatedInputChannel; @@ -381,9 +385,9 @@ int HardwareTimer::getAssociatedChannel(uint32_t channel) */ void HardwareTimer::resumeChannel(uint32_t channel) { - int timChannel = getChannel(channel); - int timAssociatedInputChannel; - int interrupt = getIT(channel); + uint32_t timChannel = getChannel(channel); + uint32_t timAssociatedInputChannel; + uint32_t interrupt = getIT(channel); // Clear flag and enable IT if (callbacks[channel]) { @@ -437,8 +441,7 @@ void HardwareTimer::resumeChannel(uint32_t channel) HAL_TIM_IC_Start(&(_timerObj.handle), timChannel); } break; - case TIMER_OUTPUT_COMPARE: - case TIMER_DISABLED: + case TIMER_OUTPUT_DISABLED: if (!LL_TIM_IsEnabledCounter(_timerObj.handle.Instance)) { HAL_TIM_Base_Start(&(_timerObj.handle)); } @@ -631,8 +634,8 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, uint32_t pin, C */ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, ChannelInputFilter_t filter) { - int timChannel = getChannel(channel); - int timAssociatedInputChannel; + uint32_t timChannel = getChannel(channel); + uint32_t timAssociatedInputChannel; TIM_OC_InitTypeDef channelOC; TIM_IC_InitTypeDef channelIC; @@ -656,21 +659,10 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, Ch channelIC.ICFilter = filter; switch (mode) { - case TIMER_DISABLED: + case TIMER_OUTPUT_DISABLED: channelOC.OCMode = TIM_OCMODE_TIMING; HAL_TIM_OC_ConfigChannel(&(_timerObj.handle), &channelOC, timChannel); break; - case TIMER_OUTPUT_COMPARE: - /* In case of TIMER_OUTPUT_COMPARE, there is no output and thus no pin to - * configure, and no channel. So nothing to do. For compatibility reason - * restore TIMER_DISABLED if necessary. - */ - if (_ChannelMode[channel - 1] != TIMER_DISABLED) { - _ChannelMode[channel - 1] = TIMER_DISABLED; - channelOC.OCMode = TIM_OCMODE_TIMING; - HAL_TIM_OC_ConfigChannel(&(_timerObj.handle), &channelOC, timChannel); - } - return; case TIMER_OUTPUT_COMPARE_ACTIVE: channelOC.OCMode = TIM_OCMODE_ACTIVE; HAL_TIM_OC_ConfigChannel(&(_timerObj.handle), &channelOC, timChannel); @@ -737,24 +729,25 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, Ch // Save channel selected mode to object attribute _ChannelMode[channel - 1] = mode; - - if (pin != NC) { - if ((int)getTimerChannel(pin) == timChannel) { - /* Configure PWM GPIO pins */ - pinmap_pinout(pin, PinMap_TIM); + if (mode != TIMER_OUTPUT_DISABLED) { + if (pin != NC) { + if (getTimerChannel(pin) == timChannel) { + /* Configure PWM GPIO pins */ + pinmap_pinout(pin, PinMap_TIM); #if defined(STM32F1xx) - if ((mode == TIMER_INPUT_CAPTURE_RISING) || (mode == TIMER_INPUT_CAPTURE_FALLING) \ - || (mode == TIMER_INPUT_CAPTURE_BOTHEDGE) || (mode == TIMER_INPUT_FREQ_DUTY_MEASUREMENT)) { - // on F1 family, input alternate function must configure GPIO in input mode - pinMode(pinNametoDigitalPin(pin), INPUT); - } + if ((mode == TIMER_INPUT_CAPTURE_RISING) || (mode == TIMER_INPUT_CAPTURE_FALLING) \ + || (mode == TIMER_INPUT_CAPTURE_BOTHEDGE) || (mode == TIMER_INPUT_FREQ_DUTY_MEASUREMENT)) { + // on F1 family, input alternate function must configure GPIO in input mode + pinMode(pinNametoDigitalPin(pin), INPUT); + } #endif - } else { - // Pin doesn't match with timer output channels - Error_Handler(); - } + } else { + // Pin doesn't match with timer output channels + Error_Handler(); + } - __ChannelsUsed[channel - 1] |= (STM_PIN_INVERTED(pinmap_function(pin, PinMap_TIM))) ? COMPLEMENTARY_CHAN_MASK : REGULAR_CHAN_MASK; + __ChannelsUsed[channel - 1] |= (STM_PIN_INVERTED(pinmap_function(pin, PinMap_TIM))) ? COMPLEMENTARY_CHAN_MASK : REGULAR_CHAN_MASK; + } } } @@ -765,11 +758,7 @@ void HardwareTimer::setMode(uint32_t channel, TimerModes_t mode, PinName pin, Ch */ TimerModes_t HardwareTimer::getMode(uint32_t channel) { - if ((1 <= channel) && (channel <= TIMER_CHANNELS)) { - return _ChannelMode[channel - 1]; - } else { - return TIMER_DISABLED; - } + return ((1 <= channel) && (channel <= TIMER_CHANNELS)) ? _ChannelMode[channel - 1] : TIMER_OUTPUT_DISABLED; } /** @@ -807,7 +796,7 @@ void HardwareTimer::setPreloadEnable(bool value) */ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerCompareFormat_t format) { - int timChannel = getChannel(channel); + uint32_t timChannel = getChannel(channel); uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; uint32_t CCR_RegisterValue; @@ -869,7 +858,7 @@ void HardwareTimer::setCaptureCompare(uint32_t channel, uint32_t compare, TimerC */ uint32_t HardwareTimer::getCaptureCompare(uint32_t channel, TimerCompareFormat_t format) { - int timChannel = getChannel(channel); + uint32_t timChannel = getChannel(channel); uint32_t CCR_RegisterValue = __HAL_TIM_GET_COMPARE(&(_timerObj.handle), timChannel); uint32_t Prescalerfactor = LL_TIM_GetPrescaler(_timerObj.handle.Instance) + 1; uint32_t return_value; @@ -936,7 +925,10 @@ void HardwareTimer::setPWM(uint32_t channel, uint32_t pin, uint32_t frequency, u */ void HardwareTimer::setPWM(uint32_t channel, PinName pin, uint32_t frequency, uint32_t dutycycle, callback_function_t PeriodCallback, callback_function_t CompareCallback) { - setMode(channel, TIMER_OUTPUT_COMPARE_PWM1, pin); + TimerModes_t previousMode = getMode(channel); + if (previousMode != TIMER_OUTPUT_COMPARE_PWM1) { + setMode(channel, TIMER_OUTPUT_COMPARE_PWM1, pin); + } setOverflow(frequency, HERTZ_FORMAT); setCaptureCompare(channel, dutycycle, PERCENT_COMPARE_FORMAT); if (PeriodCallback) { @@ -945,7 +937,9 @@ void HardwareTimer::setPWM(uint32_t channel, PinName pin, uint32_t frequency, ui if (CompareCallback) { attachInterrupt(channel, CompareCallback); } - resume(); + if (!isRunning() || !isRunningChannel(channel) || (previousMode != TIMER_OUTPUT_COMPARE_PWM1)) { + resume(); + } } /** @@ -1010,7 +1004,7 @@ void HardwareTimer::detachInterrupt() */ void HardwareTimer::attachInterrupt(uint32_t channel, callback_function_t callback) { - int interrupt = getIT(channel); + uint32_t interrupt = getIT(channel); if ((channel == 0) || (channel > (TIMER_CHANNELS + 1))) { Error_Handler(); // only channel 1..4 have an interrupt @@ -1036,7 +1030,7 @@ void HardwareTimer::attachInterrupt(uint32_t channel, callback_function_t callba */ void HardwareTimer::detachInterrupt(uint32_t channel) { - int interrupt = getIT(channel); + uint32_t interrupt = getIT(channel); if ((channel == 0) || (channel > (TIMER_CHANNELS + 1))) { Error_Handler(); // only channel 1..4 have an interrupt @@ -1169,14 +1163,14 @@ bool HardwareTimer::isRunning() */ bool HardwareTimer::isRunningChannel(uint32_t channel) { - int LLChannel = getLLChannel(channel); - int interrupt = getIT(channel); + uint32_t LLChannel = getLLChannel(channel); + uint32_t interrupt = getIT(channel); bool ret; // channel is running if: timer is running, and either output channel is // enabled or interrupt is set ret = LL_TIM_CC_IsEnabledChannel(_timerObj.handle.Instance, LLChannel) - || (__HAL_TIM_GET_IT_SOURCE(&(_timerObj.handle), (uint32_t)interrupt) == SET); + || (__HAL_TIM_GET_IT_SOURCE(&(_timerObj.handle), interrupt) == SET); return (isRunning() && ret); } @@ -1361,7 +1355,7 @@ uint32_t HardwareTimer::getTimerClkFreq() uwAPBxPrescaler = clkconfig.APB1CLKDivider; uwTimclock = HAL_RCC_GetPCLK1Freq(); break; -#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) +#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32U0xx) case 2: uwAPBxPrescaler = clkconfig.APB2CLKDivider; uwTimclock = HAL_RCC_GetPCLK2Freq(); diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c index 0a9c4cbf0f..2b7ee1e4f9 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_adc.c" #elif STM32MP1xx #include "stm32mp1xx_ll_adc.c" +#elif STM32U0xx + #include "stm32u0xx_ll_adc.c" #elif STM32U5xx #include "stm32u5xx_ll_adc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c index 98c9f713d4..5c087d72fe 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c @@ -22,6 +22,8 @@ #include "stm32l4xx_ll_comp.c" #elif STM32L5xx #include "stm32l5xx_ll_comp.c" +#elif STM32U0xx + #include "stm32u0xx_ll_comp.c" #elif STM32U5xx #include "stm32u5xx_ll_comp.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c index 3d8ffc2b3a..4d16e6f4dd 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c @@ -32,6 +32,8 @@ #include "stm32l4xx_ll_crc.c" #elif STM32L5xx #include "stm32l5xx_ll_crc.c" +#elif STM32U0xx + #include "stm32u0xx_ll_crc.c" #elif STM32U5xx #include "stm32u5xx_ll_crc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crs.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crs.c index 39154154b7..9fbfb76c75 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crs.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crs.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F0xx +#ifdef STM32C0xx + #include "stm32c0xx_ll_crs.c" +#elif STM32F0xx #include "stm32f0xx_ll_crs.c" #elif STM32G0xx #include "stm32g0xx_ll_crs.c" @@ -18,6 +20,8 @@ #include "stm32l4xx_ll_crs.c" #elif STM32L5xx #include "stm32l5xx_ll_crs.c" +#elif STM32U0xx + #include "stm32u0xx_ll_crs.c" #elif STM32U5xx #include "stm32u5xx_ll_crs.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c index 4ac1c51b8a..9772d5e6a7 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dac.c @@ -30,6 +30,8 @@ #include "stm32l4xx_ll_dac.c" #elif STM32L5xx #include "stm32l5xx_ll_dac.c" +#elif STM32U0xx + #include "stm32u0xx_ll_dac.c" #elif STM32U5xx #include "stm32u5xx_ll_dac.c" #elif STM32WLxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c index 7b61d86c39..4876dd76fc 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_dma.c" #elif STM32MP1xx #include "stm32mp1xx_ll_dma.c" +#elif STM32U0xx + #include "stm32u0xx_ll_dma.c" #elif STM32U5xx #include "stm32u5xx_ll_dma.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c index a61f9511c7..0010d9e08d 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_exti.c" #elif STM32MP1xx #include "stm32mp1xx_ll_exti.c" +#elif STM32U0xx + #include "stm32u0xx_ll_exti.c" #elif STM32U5xx #include "stm32u5xx_ll_exti.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c index b436de00ff..895d9aaa73 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_gpio.c" #elif STM32MP1xx #include "stm32mp1xx_ll_gpio.c" +#elif STM32U0xx + #include "stm32u0xx_ll_gpio.c" #elif STM32U5xx #include "stm32u5xx_ll_gpio.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c index a15fe1695e..cf471d53cb 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_i2c.c" #elif STM32MP1xx #include "stm32mp1xx_ll_i2c.c" +#elif STM32U0xx + #include "stm32u0xx_ll_i2c.c" #elif STM32U5xx #include "stm32u5xx_ll_i2c.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c index d80493464a..ec6d93db08 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c @@ -22,6 +22,8 @@ #include "stm32l5xx_ll_lptim.c" #elif STM32MP1xx #include "stm32mp1xx_ll_lptim.c" +#elif STM32U0xx + #include "stm32u0xx_ll_lptim.c" #elif STM32U5xx #include "stm32u5xx_ll_lptim.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c index 6fbf1b6439..2174f737a3 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c @@ -16,6 +16,8 @@ #include "stm32l4xx_ll_lpuart.c" #elif STM32L5xx #include "stm32l5xx_ll_lpuart.c" +#elif STM32U0xx + #include "stm32u0xx_ll_lpuart.c" #elif STM32U5xx #include "stm32u5xx_ll_lpuart.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_opamp.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_opamp.c index 5890833556..2cefbf4847 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_opamp.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_opamp.c @@ -16,6 +16,8 @@ #include "stm32l4xx_ll_opamp.c" #elif STM32L5xx #include "stm32l5xx_ll_opamp.c" +#elif STM32U0xx + #include "stm32u0xx_ll_opamp.c" #elif STM32U5xx #include "stm32u5xx_ll_opamp.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c index 63d6bf7b62..1107a41551 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_pwr.c" #elif STM32MP1xx #include "stm32mp1xx_ll_pwr.c" +#elif STM32U0xx + #include "stm32u0xx_ll_pwr.c" #elif STM32U5xx #include "stm32u5xx_ll_pwr.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c index b68896c489..0434f787f5 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_rcc.c" #elif STM32MP1xx #include "stm32mp1xx_ll_rcc.c" +#elif STM32U0xx + #include "stm32u0xx_ll_rcc.c" #elif STM32U5xx #include "stm32u5xx_ll_rcc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c index 98063b6b8c..818390eb40 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c @@ -22,6 +22,8 @@ #include "stm32l4xx_ll_rng.c" #elif STM32L5xx #include "stm32l5xx_ll_rng.c" +#elif STM32U0xx + #include "stm32u0xx_ll_rng.c" #elif STM32U5xx #include "stm32u5xx_ll_rng.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c index 027e6ce25d..c977a38264 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_rtc.c" #elif STM32MP1xx #include "stm32mp1xx_ll_rtc.c" +#elif STM32U0xx + #include "stm32u0xx_ll_rtc.c" #elif STM32U5xx #include "stm32u5xx_ll_rtc.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c index 6f28b4f9de..1ea1972dcd 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_spi.c" #elif STM32MP1xx #include "stm32mp1xx_ll_spi.c" +#elif STM32U0xx + #include "stm32u0xx_ll_spi.c" #elif STM32U5xx #include "stm32u5xx_ll_spi.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c index 2af56b4a0f..5369d57fea 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_tim.c" #elif STM32MP1xx #include "stm32mp1xx_ll_tim.c" +#elif STM32U0xx + #include "stm32u0xx_ll_tim.c" #elif STM32U5xx #include "stm32u5xx_ll_tim.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c index a77516d52e..3869bbe4d6 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_usart.c" #elif STM32MP1xx #include "stm32mp1xx_ll_usart.c" +#elif STM32U0xx + #include "stm32u0xx_ll_usart.c" #elif STM32U5xx #include "stm32u5xx_ll_usart.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usb.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usb.c index 5672d4d92b..b7c7b70d44 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usb.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usb.c @@ -2,7 +2,9 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" -#ifdef STM32F0xx +#ifdef STM32C0xx + #include "stm32c0xx_ll_usb.c" +#elif STM32F0xx #include "stm32f0xx_ll_usb.c" #elif STM32F1xx #include "stm32f1xx_ll_usb.c" @@ -30,6 +32,8 @@ #include "stm32l4xx_ll_usb.c" #elif STM32L5xx #include "stm32l5xx_ll_usb.c" +#elif STM32U0xx + #include "stm32u0xx_ll_usb.c" #elif STM32U5xx #include "stm32u5xx_ll_usb.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c index 2c85934ad3..dac4dc27b0 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c @@ -34,6 +34,8 @@ #include "stm32l5xx_ll_utils.c" #elif STM32MP1xx #include "stm32mp1xx_ll_utils.c" +#elif STM32U0xx + #include "stm32u0xx_ll_utils.c" #elif STM32U5xx #include "stm32u5xx_ll_utils.c" #elif STM32WBxx diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 58b8f809cc..2e34a88533 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -418,10 +418,28 @@ void dac_write_value(PinName pin, uint32_t value, uint8_t do_init) dacChannelConf.DAC_OutputSwitch = DAC_OUTPUTSWITCH_ENABLE; #endif /*##-2- Configure DAC channel1 #############################################*/ +#if defined(STM32H5xx) && !defined(TIM8) && !defined(HAL_ICACHE_MODULE_DISABLED) + bool icache_enabled = false; + if (HAL_ICACHE_IsEnabled() == 1) { + icache_enabled = true; + /* Disable instruction cache prior to internal cacheable memory update */ + if (HAL_ICACHE_Disable() != HAL_OK) { + Error_Handler(); + } + } +#endif /* STM32H5xx && !defined(TIM8) &&!HAL_ICACHE_MODULE_DISABLED */ if (HAL_DAC_ConfigChannel(&DacHandle, &dacChannelConf, dacChannel) != HAL_OK) { /* Channel configuration Error */ return; } +#if defined(STM32H5xx) && !defined(TIM8) && !defined(HAL_ICACHE_MODULE_DISABLED) + if (icache_enabled) { + /* Re-enable instruction cache */ + if (HAL_ICACHE_Enable() != HAL_OK) { + Error_Handler(); + } + } +#endif /* STM32H5xx && !defined(TIM8) && !HAL_ICACHE_MODULE_DISABLED */ } /*##-3- Set DAC Channel1 DHR register ######################################*/ @@ -891,8 +909,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif AdcHandle.Init.DiscontinuousConvMode = DISABLE; /* Parameter discarded because sequencer is disabled */ #if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ - !defined(STM32L0xx) && !defined(STM32WBAxx) && !defined(STM32WLxx) && \ - !defined(ADC_SUPPORT_2_5_MSPS) + !defined(STM32L0xx) && !defined(STM32U0xx) && !defined(STM32WBAxx) && \ + !defined(STM32WLxx) && !defined(ADC_SUPPORT_2_5_MSPS) AdcHandle.Init.NbrOfDiscConversion = 0; /* Parameter discarded because sequencer is disabled */ #endif AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; /* Software start to trig the 1st conversion manually, without external event */ @@ -916,7 +934,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #if defined(STM32F0xx) AdcHandle.Init.SamplingTimeCommon = samplingTime; #endif -#if defined(STM32C0xx) || defined(STM32G0xx) || defined(STM32U5xx) || \ +#if defined(STM32C0xx) || defined(STM32G0xx) || defined(STM32U0xx) || defined(STM32U5xx) || \ defined(STM32WBAxx) || defined(STM32WLxx) || defined(ADC_SUPPORT_2_5_MSPS) AdcHandle.Init.SamplingTimeCommon1 = samplingTime; /* Set sampling time common to a group of channels. */ AdcHandle.Init.SamplingTimeCommon2 = samplingTime; /* Set sampling time common to a group of channels, second common setting possible.*/ @@ -981,8 +999,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif #if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32F1xx) && \ !defined(STM32F2xx) && !defined(STM32G0xx) && !defined(STM32L0xx) && \ - !defined(STM32L1xx) && !defined(STM32WBAxx) && !defined(STM32WBxx) && \ - !defined(STM32WLxx) && !defined(ADC1_V2_5) + !defined(STM32L1xx) && !defined(STM32U0xx) && !defined(STM32WBAxx) && \ + !defined(STM32WBxx) && !defined(STM32WLxx) && !defined(ADC1_V2_5) AdcChannelConf.Offset = 0; /* Parameter discarded because offset correction is disabled */ #endif #if defined (STM32H7xx) || defined(STM32MP1xx) diff --git a/libraries/SrcWrapper/src/stm32/interrupt.cpp b/libraries/SrcWrapper/src/stm32/interrupt.cpp index 40327e94ec..84621580cf 100644 --- a/libraries/SrcWrapper/src/stm32/interrupt.cpp +++ b/libraries/SrcWrapper/src/stm32/interrupt.cpp @@ -53,7 +53,8 @@ typedef struct { /* Private Variables */ static gpio_irq_conf_str gpio_irq_conf[NB_EXTI] = { -#if defined (STM32C0xx) || defined (STM32F0xx) || defined (STM32G0xx) || defined (STM32L0xx) +#if defined (STM32C0xx) || defined (STM32F0xx) || defined (STM32G0xx) ||\ + defined (STM32L0xx) || defined (STM32U0xx) {.irqnb = EXTI0_1_IRQn, .callback = NULL}, //GPIO_PIN_0 {.irqnb = EXTI0_1_IRQn, .callback = NULL}, //GPIO_PIN_1 {.irqnb = EXTI2_3_IRQn, .callback = NULL}, //GPIO_PIN_2 @@ -252,8 +253,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) } #if defined(STM32C0xx) || defined(STM32G0xx) || defined(STM32H5xx) || \ - defined(STM32MP1xx) || defined(STM32L5xx) || defined(STM32U5xx) || \ - defined(STM32WBAxx) + defined(STM32MP1xx) || defined(STM32L5xx) || defined(STM32U0xx) || \ + defined(STM32U5xx) || defined(STM32WBAxx) /** * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. @@ -275,7 +276,8 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) } #endif -#if defined (STM32C0xx) || (STM32F0xx) || defined (STM32G0xx) || defined (STM32L0xx) +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || \ + defined(STM32L0xx) || defined(STM32U0xx) #ifdef __cplusplus extern "C" { #endif diff --git a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c index 4019fbe230..df0911ca7f 100644 --- a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c +++ b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c @@ -30,6 +30,8 @@ #include "system_stm32l5xx_ns.c" #elif STM32MP1xx #include "system_stm32mp1xx.c" +#elif STM32U0xx + #include "system_stm32u0xx.c" #elif STM32U5xx #include "system_stm32u5xx.c" #elif STM32WBAxx diff --git a/libraries/SrcWrapper/src/stm32/uart.c b/libraries/SrcWrapper/src/stm32/uart.c index 3f90dcfe72..219b42fc65 100644 --- a/libraries/SrcWrapper/src/stm32/uart.c +++ b/libraries/SrcWrapper/src/stm32/uart.c @@ -73,6 +73,9 @@ typedef enum { #endif #if defined(LPUART2_BASE) LPUART2_INDEX, +#endif +#if defined(LPUART3_BASE) + LPUART3_INDEX, #endif UART_NUM } uart_index_t; @@ -253,6 +256,15 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par obj->irq = LPUART2_IRQn; } #endif +#if defined(LPUART3_BASE) + else if (obj->uart == LPUART3) { + __HAL_RCC_LPUART3_FORCE_RESET(); + __HAL_RCC_LPUART3_RELEASE_RESET(); + __HAL_RCC_LPUART3_CLK_ENABLE(); + obj->index = LPUART3_INDEX; + obj->irq = LPUART3_IRQn; + } +#endif #if defined(UART7_BASE) else if (obj->uart == UART7) { __HAL_RCC_UART7_FORCE_RESET(); @@ -362,6 +374,9 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if ((obj->uart == LPUART1) #if defined(LPUART2_BASE) || (obj->uart == LPUART2) +#endif +#if defined(LPUART3_BASE) + || (obj->uart == LPUART3) #endif ) { if (baudrate <= 9600) { @@ -395,6 +410,11 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj->uart == LPUART2) { __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_LSE); } +#endif +#if defined(LPUART3_BASE) + if (obj->uart == LPUART3) { + __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_LSE); + } #endif if (uart_rx == NP) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { @@ -412,6 +432,11 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj->uart == LPUART2) { __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_HSI); } +#endif +#if defined(LPUART3_BASE) + if (obj->uart == LPUART3) { + __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_HSI); + } #endif if (uart_rx == NP) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { @@ -434,6 +459,11 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj->uart == LPUART2) { __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_PCLK1); } +#endif +#if defined(LPUART3_BASE) + if (obj->uart == LPUART3) { + __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_PCLK1); + } #endif if (uart_rx == NP) { if (HAL_HalfDuplex_Init(huart) == HAL_OK) { @@ -451,6 +481,11 @@ void uart_init(serial_t *obj, uint32_t baudrate, uint32_t databits, uint32_t par if (obj->uart == LPUART2) { __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_SYSCLK); } +#endif +#if defined(LPUART3_BASE) + if (obj->uart == LPUART3) { + __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_SYSCLK); + } #endif } #endif @@ -541,6 +576,13 @@ void uart_deinit(serial_t *obj) __HAL_RCC_LPUART2_CLK_DISABLE(); break; #endif +#if defined(LPUART3_BASE) + case LPUART3_INDEX: + __HAL_RCC_LPUART3_FORCE_RESET(); + __HAL_RCC_LPUART3_RELEASE_RESET(); + __HAL_RCC_LPUART3_CLK_DISABLE(); + break; +#endif #if defined(UART7_BASE) case UART7_INDEX: __HAL_RCC_UART7_FORCE_RESET(); @@ -666,6 +708,13 @@ void uart_config_lowpower(serial_t *obj) __HAL_RCC_LPUART2_CONFIG(RCC_LPUART2CLKSOURCE_HSI); } break; +#endif +#if defined(LPUART3_BASE) && defined(__HAL_RCC_LPUART3_CONFIG) + case LPUART3_INDEX: + if (__HAL_RCC_GET_LPUART3_SOURCE() != RCC_LPUART3CLKSOURCE_HSI) { + __HAL_RCC_LPUART3_CONFIG(RCC_LPUART3CLKSOURCE_HSI); + } + break; #endif } #if defined(UART_WAKEUP_EXTI_LINE) @@ -978,7 +1027,7 @@ void USART2_IRQHandler(void) if (uart_handlers[UART2_INDEX] != NULL) { HAL_UART_IRQHandler(uart_handlers[UART2_INDEX]); } -#if defined(STM32G0xx) && defined(LPUART2_BASE) +#if (defined(STM32G0xx) || defined(STM32U0xx)) && defined(LPUART2_BASE) if (uart_handlers[LPUART2_INDEX] != NULL) { HAL_UART_IRQHandler(uart_handlers[LPUART2_INDEX]); } @@ -1018,7 +1067,7 @@ void USART3_IRQHandler(void) if (uart_handlers[UART3_INDEX] != NULL) { HAL_UART_IRQHandler(uart_handlers[UART3_INDEX]); } -#if defined(STM32F0xx) || defined(STM32G0xx) +#if defined(STM32F0xx) || defined(STM32G0xx) || defined(STM32U0xx) /* USART3_4_IRQn */ if (uart_handlers[UART4_INDEX] != NULL) { HAL_UART_IRQHandler(uart_handlers[UART4_INDEX]); @@ -1031,12 +1080,12 @@ void USART3_IRQHandler(void) HAL_UART_IRQHandler(uart_handlers[UART6_INDEX]); } #endif /* STM32F030xC */ -#if defined(STM32G0xx) && defined(LPUART1_BASE) +#if (defined(STM32G0xx) || STM32U0xx) && defined(LPUART1_BASE) if (uart_handlers[LPUART1_INDEX] != NULL) { HAL_UART_IRQHandler(uart_handlers[LPUART1_INDEX]); } -#endif /* STM32G0xx && LPUART1_BASE */ -#endif /* STM32F0xx || STM32G0xx */ +#endif /* (STM32G0xx || STM32U0xx) && LPUART1_BASE */ +#endif /* STM32F0xx || STM32G0xx || STM32U0xx */ #endif /* STM32F091xC || STM32F098xx */ } #endif @@ -1074,6 +1123,28 @@ void USART4_5_IRQHandler(void) #endif #endif +/** + * @brief USART 4 IRQ handler + * @param None + * @retval None + */ +#if defined(STM32U0xx) +#if defined(USART4_BASE) +void USART4_IRQHandler(void) +{ + HAL_NVIC_ClearPendingIRQ(USART4_IRQn); + if (uart_handlers[UART4_INDEX] != NULL) { + HAL_UART_IRQHandler(uart_handlers[UART4_INDEX]); + } +#if defined(LPUART3_BASE) + if (uart_handlers[LPUART3_INDEX] != NULL) { + HAL_UART_IRQHandler(uart_handlers[LPUART3_INDEX]); + } +#endif +} +#endif +#endif + /** * @brief USART 5 IRQ handler * @param None diff --git a/libraries/USBDevice/inc/usbd_conf.h b/libraries/USBDevice/inc/usbd_conf.h index 03578c3c14..205ecc47b5 100644 --- a/libraries/USBDevice/inc/usbd_conf.h +++ b/libraries/USBDevice/inc/usbd_conf.h @@ -74,7 +74,7 @@ extern "C" { #elif defined(STM32G0xx) #define USB_IRQn USB_UCPD1_2_IRQn #define USB_IRQHandler USB_UCPD1_2_IRQHandler -#elif defined(STM32H5xx) +#elif defined(STM32C0xx) || defined(STM32H5xx) || defined(STM32U0xx) #define USB_IRQn USB_DRD_FS_IRQn #define USB_IRQHandler USB_DRD_FS_IRQHandler #elif defined(STM32U5xx) && !defined(USB_DRD_FS) diff --git a/libraries/Wire/src/Wire.cpp b/libraries/Wire/src/Wire.cpp index c25a915a8b..c167aca5ac 100644 --- a/libraries/Wire/src/Wire.cpp +++ b/libraries/Wire/src/Wire.cpp @@ -33,18 +33,6 @@ static const uint8_t MASTER_ADDRESS = 0x01; // Constructors //////////////////////////////////////////////////////////////// -TwoWire::TwoWire() -{ - memset((void *)&_i2c, 0, sizeof(_i2c)); - _i2c.sda = digitalPinToPinName(SDA); - _i2c.scl = digitalPinToPinName(SCL); - - txBuffer = nullptr; - txBufferAllocated = 0; - rxBuffer = nullptr; - rxBufferAllocated = 0; -} - TwoWire::TwoWire(uint32_t sda, uint32_t scl) { memset((void *)&_i2c, 0, sizeof(_i2c)); @@ -104,7 +92,7 @@ void TwoWire::begin(uint8_t address, bool generalCall, bool NoStretchMode) recoverBus(); // in case I2C bus (device) is stuck after a reset for example - i2c_custom_init(&_i2c, 100000, I2C_ADDRESSINGMODE_7BIT, ownAddress); + i2c_init(&_i2c, 100000, ownAddress); if (_i2c.isMaster == 0) { // i2c_attachSlaveTxEvent(&_i2c, reinterpret_cast(&TwoWire::onRequestService)); diff --git a/libraries/Wire/src/Wire.h b/libraries/Wire/src/Wire.h index fafea29dd9..58398cd76c 100644 --- a/libraries/Wire/src/Wire.h +++ b/libraries/Wire/src/Wire.h @@ -76,8 +76,7 @@ class TwoWire : public Stream { void recoverBus(void); public: - TwoWire(); - TwoWire(uint32_t sda, uint32_t scl); + TwoWire(uint32_t sda = SDA, uint32_t scl = SCL); ~TwoWire(); // setSCL/SDA have to be called before begin() void setSCL(uint32_t scl) diff --git a/libraries/Wire/src/utility/twi.c b/libraries/Wire/src/utility/twi.c index 8cdca94c53..f49eb800b2 100644 --- a/libraries/Wire/src/utility/twi.c +++ b/libraries/Wire/src/utility/twi.c @@ -300,7 +300,7 @@ static uint32_t i2c_getClkFreq(I2C_TypeDef *i2c) Error_Handler(); } #else - /* STM32 L0/G0 I2C2 has no independent clock */ + /* STM32 L0/G0/U0 I2C2 has no independent clock */ clkSrcFreq = HAL_RCC_GetPCLK1Freq(); #endif } @@ -406,7 +406,8 @@ static uint32_t i2c_getClkFreq(I2C_TypeDef *i2c) Error_Handler(); } #else - Error_Handler(); + /* STM32 U0 I2C4 has no independent clock */ + clkSrcFreq = HAL_RCC_GetPCLK1Freq(); #endif } } @@ -419,7 +420,49 @@ static uint32_t i2c_getClkFreq(I2C_TypeDef *i2c) #else clkSrcFreq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C35); #endif + if (clkSrcFreq == 0) +#endif + { +#ifdef __HAL_RCC_GET_I2C5_SOURCE + switch (__HAL_RCC_GET_I2C5_SOURCE()) { +#ifdef RCC_I2C5CLKSOURCE_HSI + case RCC_I2C5CLKSOURCE_HSI: + clkSrcFreq = HSI_VALUE; + break; +#endif +#ifdef RCC_I2C5CLKSOURCE_SYSCLK + case RCC_I2C5CLKSOURCE_SYSCLK: + clkSrcFreq = SystemCoreClock; + break; +#endif +#if defined(RCC_I2C5CLKSOURCE_PCLK1) || defined(RCC_I2C5CLKSOURCE_D2PCLK1) +#ifdef RCC_I2C5CLKSOURCE_PCLK1 + case RCC_I2C5CLKSOURCE_PCLK1: +#endif +#ifdef RCC_I2C5CLKSOURCE_D2PCLK1 + case RCC_I2C5CLKSOURCE_D2PCLK1: +#endif + clkSrcFreq = HAL_RCC_GetPCLK1Freq(); + break; +#endif +#ifdef RCC_I2C5CLKSOURCE_CSI + case RCC_I2C5CLKSOURCE_CSI: + clkSrcFreq = CSI_VALUE; + break; +#endif +#ifdef RCC_I2C5CLKSOURCE_PLL3 + case RCC_I2C5CLKSOURCE_PLL3: + HAL_RCCEx_GetPLL3ClockFreq(&PLL3_Clocks); + clkSrcFreq = PLL3_Clocks.PLL3_R_Frequency; + break; #endif + default: + Error_Handler(); + } +#else + Error_Handler(); +#endif + } } #endif // I2C5_BASE #if defined(I2C6_BASE) @@ -430,7 +473,38 @@ static uint32_t i2c_getClkFreq(I2C_TypeDef *i2c) #else clkSrcFreq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C46); #endif + if (clkSrcFreq == 0) +#endif + { +#ifdef __HAL_RCC_GET_I2C6_SOURCE + switch (__HAL_RCC_GET_I2C6_SOURCE()) { +#ifdef RCC_I2C6CLKSOURCE_HSI + case RCC_I2C6CLKSOURCE_HSI: + clkSrcFreq = HSI_VALUE; + break; +#endif +#ifdef RCC_I2C6CLKSOURCE_SYSCLK + case RCC_I2C6CLKSOURCE_SYSCLK: + clkSrcFreq = SystemCoreClock; + break; +#endif +#ifdef RCC_I2C6CLKSOURCE_PCLK1 + case RCC_I2C6CLKSOURCE_PCLK1: + clkSrcFreq = HAL_RCC_GetPCLK1Freq(); + break; +#endif +#ifdef RCC_I2C6CLKSOURCE_MSIK + case RCC_I2C6CLKSOURCE_MSIK: + clkSrcFreq = MSI_VALUE; + break; +#endif + default: + Error_Handler(); + } +#else + Error_Handler(); #endif + } } #endif // I2C6_BASE return clkSrcFreq; @@ -637,25 +711,14 @@ static uint32_t i2c_getTiming(i2c_t *obj, uint32_t frequency) return ret; } -/** - * @brief Default init and setup GPIO and I2C peripheral - * @param obj : pointer to i2c_t structure - * @retval none - */ -void i2c_init(i2c_t *obj) -{ - i2c_custom_init(obj, 100000, I2C_ADDRESSINGMODE_7BIT, 0x33); -} - /** * @brief Initialize and setup GPIO and I2C peripheral * @param obj : pointer to i2c_t structure * @param timing : one of the i2c_timing_e - * @param addressingMode : I2C_ADDRESSINGMODE_7BIT or I2C_ADDRESSINGMODE_10BIT * @param ownAddress : device address * @retval none */ -void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint32_t ownAddress) +void i2c_init(i2c_t *obj, uint32_t timing, uint32_t ownAddress) { if (obj != NULL) { @@ -686,9 +749,10 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 __HAL_RCC_I2C1_RELEASE_RESET(); obj->irq = I2C1_EV_IRQn; -#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ + !defined(STM32L0xx) && !defined(STM32U0xx) obj->irqER = I2C1_ER_IRQn; -#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx */ +#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ i2c_handles[I2C1_INDEX] = handle; } #endif // I2C1_BASE @@ -699,9 +763,10 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 __HAL_RCC_I2C2_FORCE_RESET(); __HAL_RCC_I2C2_RELEASE_RESET(); obj->irq = I2C2_EV_IRQn; -#if !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ + !defined(STM32L0xx) && !defined(STM32U0xx) obj->irqER = I2C2_ER_IRQn; -#endif /* !STM32F0xx && !STM32G0xx && !STM32L0xx */ +#endif /* !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ i2c_handles[I2C2_INDEX] = handle; } #endif // I2C2_BASE @@ -712,9 +777,9 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 __HAL_RCC_I2C3_FORCE_RESET(); __HAL_RCC_I2C3_RELEASE_RESET(); obj->irq = I2C3_EV_IRQn; -#if !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32G0xx) && !defined(STM32L0xx) && !defined(STM32U0xx) obj->irqER = I2C3_ER_IRQn; -#endif /* !STM32G0xx && !STM32L0xx */ +#endif /* !STM32G0xx && !STM32L0xx && !STM32U0xx*/ i2c_handles[I2C3_INDEX] = handle; } #endif // I2C3_BASE @@ -725,7 +790,9 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 __HAL_RCC_I2C4_FORCE_RESET(); __HAL_RCC_I2C4_RELEASE_RESET(); obj->irq = I2C4_EV_IRQn; +#if !defined(STM32U0xx) obj->irqER = I2C4_ER_IRQn; +#endif /* !STM32U0xx */ i2c_handles[I2C4_INDEX] = handle; } #endif // I2C4_BASE @@ -771,7 +838,7 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 #endif handle->Init.OwnAddress1 = ownAddress; handle->Init.OwnAddress2 = 0; - handle->Init.AddressingMode = addressingMode; + handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; handle->Init.GeneralCallMode = (obj->generalCall == 0) ? I2C_GENERALCALL_DISABLE : I2C_GENERALCALL_ENABLE; handle->Init.NoStretchMode = (obj->NoStretchMode == 0) ? I2C_NOSTRETCH_DISABLE : I2C_NOSTRETCH_ENABLE; @@ -780,10 +847,11 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 HAL_NVIC_SetPriority(obj->irq, I2C_IRQ_PRIO, I2C_IRQ_SUBPRIO); HAL_NVIC_EnableIRQ(obj->irq); -#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ + !defined(STM32L0xx) && !defined(STM32U0xx) HAL_NVIC_SetPriority(obj->irqER, I2C_IRQ_PRIO, I2C_IRQ_SUBPRIO); HAL_NVIC_EnableIRQ(obj->irqER); -#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx */ +#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ /* Init the I2C */ if (HAL_I2C_Init(handle) != HAL_OK) { @@ -807,9 +875,10 @@ void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, uint3 void i2c_deinit(i2c_t *obj) { HAL_NVIC_DisableIRQ(obj->irq); -#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ + !defined(STM32L0xx) && !defined(STM32U0xx) HAL_NVIC_DisableIRQ(obj->irqER); -#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx */ +#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ HAL_I2C_DeInit(&(obj->handle)); /* Reset I2C GPIO pins as INPUT_ANALOG */ pin_function(obj->scl, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); @@ -1232,12 +1301,14 @@ void I2C1_EV_IRQHandler(void) { I2C_HandleTypeDef *handle = i2c_handles[I2C1_INDEX]; HAL_I2C_EV_IRQHandler(handle); -#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || defined(STM32L0xx) +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || \ + defined(STM32L0xx) || defined(STM32U0xx) HAL_I2C_ER_IRQHandler(handle); -#endif /* STM32C0xx || STM32F0xx || STM32G0xx || STM32L0xx */ +#endif /* STM32C0xx || STM32F0xx || STM32G0xx || STM32L0xx || STM32U0xx*/ } -#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ + !defined(STM32L0xx) && !defined(STM32U0xx) /** * @brief This function handles I2C1 interrupt. * @param None @@ -1248,7 +1319,7 @@ void I2C1_ER_IRQHandler(void) I2C_HandleTypeDef *handle = i2c_handles[I2C1_INDEX]; HAL_I2C_ER_IRQHandler(handle); } -#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx */ +#endif /* !STM32C0xx && !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ #endif // I2C1_BASE #if defined(I2C2_BASE) @@ -1259,7 +1330,7 @@ void I2C1_ER_IRQHandler(void) */ void I2C2_EV_IRQHandler(void) { -#if defined(I2C3_BASE) && defined(STM32G0xx) +#if defined(I2C3_BASE) && (defined(STM32G0xx) || defined(STM32U0xx)) /* I2C2_3_IRQHandler */ I2C_HandleTypeDef *handle2 = i2c_handles[I2C2_INDEX]; I2C_HandleTypeDef *handle3 = i2c_handles[I2C3_INDEX]; @@ -1271,16 +1342,26 @@ void I2C2_EV_IRQHandler(void) HAL_I2C_EV_IRQHandler(handle3); HAL_I2C_ER_IRQHandler(handle3); } +#if defined(I2C4_BASE) + /* I2C2_3_4_IRQHandler */ + I2C_HandleTypeDef *handle4 = i2c_handles[I2C4_INDEX]; + if (handle4) { + HAL_I2C_EV_IRQHandler(handle4); + HAL_I2C_ER_IRQHandler(handle4); + } +#endif /* I2C4_BASE */ #else I2C_HandleTypeDef *handle = i2c_handles[I2C2_INDEX]; HAL_I2C_EV_IRQHandler(handle); -#if defined(STM32F0xx) || defined(STM32G0xx) || defined(STM32L0xx) +#if defined(STM32F0xx) || defined(STM32G0xx) || defined(STM32L0xx) || \ + defined(STM32U0xx) HAL_I2C_ER_IRQHandler(handle); -#endif /* STM32F0xx || STM32G0xx || STM32L0xx */ +#endif /* STM32F0xx || STM32G0xx || STM32L0xx || STM32U0xx*/ #endif } -#if !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) +#if !defined(STM32F0xx) && !defined(STM32G0xx) && !defined(STM32L0xx) && \ + !defined(STM32U0xx) /** * @brief This function handles I2C2 interrupt. * @param None @@ -1291,10 +1372,10 @@ void I2C2_ER_IRQHandler(void) I2C_HandleTypeDef *handle = i2c_handles[I2C2_INDEX]; HAL_I2C_ER_IRQHandler(handle); } -#endif /* !STM32F0xx && !STM32G0xx && !STM32L0xx */ +#endif /* !STM32F0xx && !STM32G0xx && !STM32L0xx && !STM32U0xx */ #endif // I2C2_BASE -#if defined(I2C3_BASE) && !defined(STM32G0xx) +#if defined(I2C3_BASE) && !defined(STM32G0xx) && !defined(STM32U0xx) /** * @brief This function handles I2C3 interrupt. * @param None @@ -1321,9 +1402,9 @@ void I2C3_ER_IRQHandler(void) HAL_I2C_ER_IRQHandler(handle); } #endif /* !STM32L0xx */ -#endif /* I2C3_BASE && ! STM32G0xx */ +#endif /* I2C3_BASE && ! STM32G0xx && !STM32U0xx */ -#if defined(I2C4_BASE) +#if defined(I2C4_BASE) && !defined(STM32U0xx) /** * @brief This function handles I2C4 interrupt. * @param None @@ -1346,7 +1427,7 @@ void I2C4_ER_IRQHandler(void) I2C_HandleTypeDef *handle = i2c_handles[I2C4_INDEX]; HAL_I2C_ER_IRQHandler(handle); } -#endif // I2C4_BASE +#endif // I2C4_BASE && !STM32U0xx #if defined(I2C5_BASE) /** diff --git a/libraries/Wire/src/utility/twi.h b/libraries/Wire/src/utility/twi.h index 8fb3dc6b81..085a1edeca 100644 --- a/libraries/Wire/src/utility/twi.h +++ b/libraries/Wire/src/utility/twi.h @@ -67,24 +67,34 @@ extern "C" { #error I2C buffer size cannot exceed 255 #endif -/* Redefinition of IRQ for C0/F0/G0/L0 families */ -#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) || defined(STM32L0xx) +/* Redefinition of IRQ for C0/F0/G0/L0/U0 families */ +#if defined(STM32C0xx) || defined(STM32F0xx) || defined(STM32G0xx) ||\ + defined(STM32L0xx) || defined(STM32U0xx) #if defined(I2C1_BASE) #define I2C1_EV_IRQn I2C1_IRQn #define I2C1_EV_IRQHandler I2C1_IRQHandler #endif // defined(I2C1_BASE) #if defined(I2C2_BASE) -#if defined(STM32G0xx) && defined(I2C3_BASE) +#if (defined(STM32G0xx) || defined(STM32U0xx)) && defined(I2C3_BASE) +#if defined(I2C4_BASE) +#define I2C2_EV_IRQn I2C2_3_4_IRQn +#define I2C2_EV_IRQHandler I2C2_3_4_IRQHandler +#else #define I2C2_EV_IRQn I2C2_3_IRQn #define I2C2_EV_IRQHandler I2C2_3_IRQHandler +#endif // defined(I2C4_BASE) #else #define I2C2_EV_IRQn I2C2_IRQn #define I2C2_EV_IRQHandler I2C2_IRQHandler #endif #endif // defined(I2C2_BASE) #if defined(I2C3_BASE) -#if defined(STM32G0xx) +#if defined(STM32G0xx) || defined(STM32U0xx) +#if defined(I2C4_BASE) +#define I2C3_EV_IRQn I2C2_3_4_IRQn +#else #define I2C3_EV_IRQn I2C2_3_IRQn +#endif #else #define I2C3_EV_IRQn I2C3_IRQn #define I2C3_EV_IRQHandler I2C3_IRQHandler @@ -92,10 +102,14 @@ extern "C" { #endif // defined(I2C3_BASE) /* Defined but no one has it */ #if defined(I2C4_BASE) +#if defined(STM32U0xx) +#define I2C4_EV_IRQn I2C2_3_4_IRQn +#else #define I2C4_EV_IRQn I2C4_IRQn #define I2C4_EV_IRQHandler I2C4_IRQHandler +#endif #endif // defined(I2C4_BASE) -#endif /* STM32C0xx || STM32F0xx || STM32G0xx || STM32L0xx */ +#endif /* STM32C0xx || STM32F0xx || STM32G0xx || STM32L0xx || STM32U0xx */ typedef struct i2c_s i2c_t; @@ -137,9 +151,7 @@ typedef enum { } i2c_status_e; /* Exported functions ------------------------------------------------------- */ -void i2c_init(i2c_t *obj); -void i2c_custom_init(i2c_t *obj, uint32_t timing, uint32_t addressingMode, - uint32_t ownAddress); +void i2c_init(i2c_t *obj, uint32_t timing, uint32_t ownAddress); void i2c_deinit(i2c_t *obj); void i2c_setTiming(i2c_t *obj, uint32_t frequency); i2c_status_e i2c_master_write(i2c_t *obj, uint8_t dev_address, uint8_t *data, uint16_t size); diff --git a/platform.txt b/platform.txt index f171d5b19a..edfce65bf1 100644 --- a/platform.txt +++ b/platform.txt @@ -5,7 +5,7 @@ # https://arduino.github.io/arduino-cli/latest/platform-specification/ name=STM32 boards groups (Board to be selected from Tools submenu 'Board part number') -version=2.8.1 +version=2.9.0 # Define variables used multiple times in platform file @@ -17,7 +17,7 @@ busybox= busybox.windows={runtime.tools.STM32Tools.path}/win/busybox.exe toolchain_dir={runtime.tools.xpack-arm-none-eabi-gcc-13.2.1-1.1.path} -openocd_dir={runtime.tools.xpack-openocd-0.12.0-3.path} +openocd_dir={runtime.tools.xpack-openocd-0.12.0-4.path} tools_bin_path.windows={runtime.tools.STM32Tools.path}/win tools_bin_path.macosx={runtime.tools.STM32Tools.path}/macosx @@ -153,7 +153,6 @@ extras.path={build.system.path}/extras # Create {build.opt} if not exists in the output sketch dir and force include of SrcWrapper library recipe.hooks.prebuild.1.pattern="{busybox}" sh "{extras.path}/prebuild.sh" "{build.path}" "{build.source.path}" "{runtime.platform.path}" "usb={build.enable_usb}" "virtio={build.enable_virtio}" -recipe.hooks.postbuild.1.pattern="{busybox}" sh "{extras.path}/postbuild.sh" "{build.path}" "{build.series}" "{runtime.platform.path}" # compile patterns # --------------------- @@ -239,6 +238,14 @@ tools.remoteproc_gen.upload.params.verbose= tools.remoteproc_gen.upload.params.quiet= tools.remoteproc_gen.upload.pattern="{busybox}" sh "{path}/{script}" generate "{build.path}/{build.project_name}.elf" "{build.path}/run_arduino_{build.project_name}.sh" +# OpenOCD sketch upload +tools.openocd_upload.path={openocd_dir} +tools.openocd_upload.cmd=bin/openocd +tools.openocd_upload.cmd.windows=bin/openocd.exe +tools.openocd_upload.upload.params.verbose=-d2 +tools.openocd_upload.upload.params.quiet=-d0 +tools.openocd_upload.upload.pattern="{path}/{cmd}" {upload.verbose} -f interface/{upload.protocol}.cfg -f target/{openocd.target}.cfg -c "program {build.path}/{build.project_name}.elf verify reset exit" + # # Debugger # @@ -252,3 +259,4 @@ debug.server.openocd.scripts_dir={openocd_dir}/openocd/scripts # Common config debug.server.openocd.scripts.0=interface/stlink.cfg debug.server.openocd.scripts.1={runtime.platform.path}/debugger/select_hla.cfg +debug.server.openocd.scripts.2=target/{openocd.target}.cfg diff --git a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h index 3edae74be8..7ce9b55ca2 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32C0xx/Include/stm32c011xx.h @@ -225,7 +225,7 @@ typedef struct __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ - uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ @@ -498,7 +498,14 @@ typedef struct #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ -#define SRAM_SIZE_MAX (0x00001500UL) /*!< maximum SRAM size (up to 6 KBytes) */ +#define SRAM_SIZE_MAX (0x00001800UL) /*!< maximum SRAM size (up to 6 KBytes) */ + +#define FLASH_SIZE_DEFAULT 0x8000U /*!< Flash memory default size */ + +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? FLASH_SIZE_DEFAULT : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? FLASH_SIZE_DEFAULT : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + /*!< Peripheral memory map */ #define APBPERIPH_BASE (PERIPH_BASE) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) @@ -546,6 +553,7 @@ typedef struct #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL) #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL) #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL) #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL) #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL) @@ -606,10 +614,10 @@ typedef struct #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) - #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) @@ -1283,6 +1291,10 @@ typedef struct #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_AWD3CR register ****************/ #define ADC_AWD3CR_AWD3CH_Pos (0U) @@ -1307,6 +1319,10 @@ typedef struct #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD3CH_20 (0x100000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD3CH_21 (0x200000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD3CH_22 (0x400000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00400000 */ /******************** Bit definition for ADC_CALFACT register ***************/ #define ADC_CALFACT_CALFACT_Pos (0U) @@ -1523,18 +1539,6 @@ typedef struct #define DMA_IFCR_CTEIF3_Pos (11U) #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4_Pos (12U) -#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ -#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4_Pos (13U) -#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ -#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4_Pos (14U) -#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ -#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4_Pos (15U) -#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ -#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ #define DMA_CCR_EN_Pos (0U) @@ -1953,7 +1957,6 @@ typedef struct #define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ #define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ - /******************* Bit definition for EXTI_FPR1 register ******************/ #define EXTI_FPR1_FPIF0_Pos (0U) #define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ @@ -2093,8 +2096,8 @@ typedef struct #define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */ #define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ #define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ -#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ -#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ #define EXTI_EXTICR4_EXTI14_Pos (16U) #define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */ #define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ @@ -2157,57 +2160,21 @@ typedef struct #define EXTI_IMR1_IM15_Pos (15U) #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR1_IM16_Pos (16U) -#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ -#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR1_IM17_Pos (17U) -#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ -#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR1_IM18_Pos (18U) -#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ #define EXTI_IMR1_IM19_Pos (19U) #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */ #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */ -#define EXTI_IMR1_IM20_Pos (20U) -#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */ -#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */ -#define EXTI_IMR1_IM21_Pos (21U) -#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */ -#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */ -#define EXTI_IMR1_IM22_Pos (22U) -#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */ -#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */ #define EXTI_IMR1_IM23_Pos (23U) #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */ #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */ -#define EXTI_IMR1_IM24_Pos (24U) -#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */ -#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */ #define EXTI_IMR1_IM25_Pos (25U) #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */ -#define EXTI_IMR1_IM26_Pos (26U) -#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */ -#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */ -#define EXTI_IMR1_IM27_Pos (27U) -#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */ -#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */ -#define EXTI_IMR1_IM28_Pos (28U) -#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ -#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */ -#define EXTI_IMR1_IM29_Pos (29U) -#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */ -#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */ -#define EXTI_IMR1_IM30_Pos (30U) -#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */ -#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */ #define EXTI_IMR1_IM31_Pos (31U) -#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ +#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */ #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */ #define EXTI_IMR1_IM_Pos (0U) -#define EXTI_IMR1_IM_Msk (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFEAFFFFF */ +#define EXTI_IMR1_IM_Msk (0x0288FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x288FFFF */ #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */ /******************* Bit definition for EXTI_EMR1 register ******************/ @@ -2272,34 +2239,17 @@ typedef struct #define EXTI_EMR1_EM19_Pos (19U) #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */ #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */ -#define EXTI_EMR1_EM21_Pos (21U) -#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */ -#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */ #define EXTI_EMR1_EM23_Pos (23U) #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */ #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */ #define EXTI_EMR1_EM25_Pos (25U) #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */ #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */ -#define EXTI_EMR1_EM26_Pos (26U) -#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */ -#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */ -#define EXTI_EMR1_EM27_Pos (27U) -#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */ -#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */ -#define EXTI_EMR1_EM28_Pos (28U) -#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */ -#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */ -#define EXTI_EMR1_EM29_Pos (29U) -#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */ -#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */ -#define EXTI_EMR1_EM30_Pos (30U) -#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */ -#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */ #define EXTI_EMR1_EM31_Pos (31U) #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */ #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */ + /******************************************************************************/ /* */ /* FLASH */ @@ -2384,7 +2334,7 @@ typedef struct #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */ #define FLASH_CR_MER1 FLASH_CR_MER1_Msk #define FLASH_CR_PNB_Pos (3U) -#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_CR_PNB_Msk (0xFUL << FLASH_CR_PNB_Pos) /*!< 0x00000078 */ #define FLASH_CR_PNB FLASH_CR_PNB_Msk #define FLASH_CR_STRT_Pos (16U) #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ @@ -2417,23 +2367,6 @@ typedef struct #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk -/******************* Bits definition for FLASH_ECCR register ****************/ -#define FLASH_ECCR_ADDR_ECC_Pos (0U) -#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */ -#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk -#define FLASH_ECCR_SYSF_ECC_Pos (20U) -#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */ -#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk -#define FLASH_ECCR_ECCCIE_Pos (24U) -#define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */ -#define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk -#define FLASH_ECCR_ECCC_Pos (30U) -#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ -#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk -#define FLASH_ECCR_ECCD_Pos (31U) -#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ -#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk - /******************* Bits definition for FLASH_OPTR register ****************/ #define FLASH_OPTR_RDP_Pos (0U) #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ @@ -2441,16 +2374,16 @@ typedef struct #define FLASH_OPTR_BOR_EN_Pos (8U) #define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */ #define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk -#define FLASH_OPTR_BORF_LEV_Pos (9U) -#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */ -#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk -#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */ -#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */ -#define FLASH_OPTR_BORR_LEV_Pos (11U) -#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORR_LEV_Pos (9U) +#define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000600 */ #define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk -#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */ -#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_BORF_LEV_Pos (11U) +#define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001800 */ +#define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk +#define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000800 */ +#define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00001000 */ #define FLASH_OPTR_nRST_STOP_Pos (13U) #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */ #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk @@ -2475,6 +2408,9 @@ typedef struct #define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U) #define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */ #define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk +#define FLASH_OPTR_SECURE_MUXING_EN_Pos (23U) +#define FLASH_OPTR_SECURE_MUXING_EN_Msk (0x1UL << FLASH_OPTR_SECURE_MUXING_EN_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SECURE_MUXING_EN FLASH_OPTR_SECURE_MUXING_EN_Msk #define FLASH_OPTR_nBOOT_SEL_Pos (24U) #define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */ #define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk @@ -2495,12 +2431,12 @@ typedef struct /****************** Bits definition for FLASH_PCROP1ASR register ************/ #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U) -#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x3FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000003F */ #define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk /****************** Bits definition for FLASH_PCROP1AER register ************/ #define FLASH_PCROP1AER_PCROP1A_END_Pos (0U) -#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1AER_PCROP1A_END_Msk (0x3FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000003F */ #define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk #define FLASH_PCROP1AER_PCROP_RDP_Pos (31U) #define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */ @@ -2508,34 +2444,34 @@ typedef struct /****************** Bits definition for FLASH_WRP1AR register ***************/ #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U) -#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_STRT_Msk (0xFUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000000F */ #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk #define FLASH_WRP1AR_WRP1A_END_Pos (16U) -#define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_END_Msk (0xFUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x000F0000 */ #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk /****************** Bits definition for FLASH_WRP1BR register ***************/ #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U) -#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_STRT_Msk (0xFUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000000F */ #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk #define FLASH_WRP1BR_WRP1B_END_Pos (16U) -#define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_END_Msk (0xFUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x000F0000 */ #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk /****************** Bits definition for FLASH_PCROP1BSR register ************/ #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U) -#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x3FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000003F */ #define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk /****************** Bits definition for FLASH_PCROP1BER register ************/ #define FLASH_PCROP1BER_PCROP1B_END_Pos (0U) -#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */ +#define FLASH_PCROP1BER_PCROP1B_END_Msk (0x3FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000003F */ #define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk /****************** Bits definition for FLASH_SECR register *****************/ #define FLASH_SECR_SEC_SIZE_Pos (0U) -#define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */ +#define FLASH_SECR_SEC_SIZE_Msk (0x1FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000001F */ #define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk #define FLASH_SECR_BOOT_LOCK_Pos (16U) #define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */ @@ -3617,7 +3553,7 @@ typedef struct #define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */ #define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable external WKUP pin 3 */ #define PWR_CR3_EWUP4_Pos (3U) -#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000004 */ +#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */ #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable external WKUP pin 4 */ #define PWR_CR3_EWUP6_Pos (5U) #define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */ @@ -3679,9 +3615,6 @@ typedef struct #define PWR_SR2_FLASH_RDY_Pos (7U) #define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */ #define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */ -#define PWR_SR2_REGLPF_Pos (9U) -#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */ -#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */ /******************** Bit definition for PWR_SCR register ********************/ #define PWR_SCR_CWUF_Pos (0U) @@ -3970,40 +3903,36 @@ typedef struct #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */ /*!< MCO2SEL configuration */ -#define RCC_CFGR_MCO2SEL_Pos (16U) -#define RCC_CFGR_MCO2SEL_Msk (0xFUL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x000F0000 */ -#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [3:0] bits (Clock output selection) */ -#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00010000 */ -#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00020000 */ -#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00040000 */ -#define RCC_CFGR_MCO2SEL_3 (0x8UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CFGR_MCO2SEL_Pos (16U) +#define RCC_CFGR_MCO2SEL_Msk (0x7UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00070000 */ +#define RCC_CFGR_MCO2SEL RCC_CFGR_MCO2SEL_Msk /*!< MCO2SEL [2:0] bits (Clock output selection) */ +#define RCC_CFGR_MCO2SEL_0 (0x1UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00010000 */ +#define RCC_CFGR_MCO2SEL_1 (0x2UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00020000 */ +#define RCC_CFGR_MCO2SEL_2 (0x4UL << RCC_CFGR_MCO2SEL_Pos) /*!< 0x00040000 */ /*!< MCO2 Prescaler configuration */ -#define RCC_CFGR_MCO2PRE_Pos (20U) -#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00F00000 */ -#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO prescaler [3:0] */ -#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00100000 */ -#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00400000 */ -#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00800000 */ +#define RCC_CFGR_MCO2PRE_Pos (20U) +#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00700000 */ +#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< MCO prescaler [2:0] */ +#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00100000 */ +#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00200000 */ +#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x00400000 */ /*!< MCOSEL configuration */ #define RCC_CFGR_MCOSEL_Pos (24U) -#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ -#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */ +#define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */ +#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */ #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ -#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ /*!< MCO Prescaler configuration */ #define RCC_CFGR_MCOPRE_Pos (28U) -#define RCC_CFGR_MCOPRE_Msk (0xFUL << RCC_CFGR_MCOPRE_Pos) /*!< 0xF0000000 */ -#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [3:0] */ +#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */ #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ -#define RCC_CFGR_MCOPRE_3 (0x8UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x80000000 */ /******************** Bit definition for RCC_CIER register ******************/ #define RCC_CIER_LSIRDYIE_Pos (0U) @@ -4089,7 +4018,7 @@ typedef struct #define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk #define RCC_APBRSTR1_USART2RST_Pos (17U) -#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00010000 */ #define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk #define RCC_APBRSTR1_I2C1RST_Pos (21U) #define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */ @@ -4163,7 +4092,7 @@ typedef struct #define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk #define RCC_APBENR1_USART2EN_Pos (17U) -#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00010000 */ #define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk #define RCC_APBENR1_I2C1EN_Pos (21U) #define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */ @@ -4240,7 +4169,7 @@ typedef struct #define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk #define RCC_APBSMENR1_USART2SMEN_Pos (17U) -#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00010000 */ #define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk #define RCC_APBSMENR1_I2C1SMEN_Pos (21U) #define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ @@ -5013,9 +4942,6 @@ typedef struct #define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */ #define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */ #define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */ -#define SYSCFG_CFGR1_BOOSTEN_Pos (8U) -#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */ -#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */ #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U) #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */ #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ @@ -5048,49 +4974,49 @@ typedef struct /****************** Bit definition for SYSCFG_CFGR3 register ****************/ #define SYSCFG_CFGR3_PINMUX0_Pos (0U) -#define SYSCFG_CFGR3_PINMUX0_Msk (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000003 */ +#define SYSCFG_CFGR3_PINMUX0_Msk (0x3UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000003 */ #define SYSCFG_CFGR3_PINMUX0 SYSCFG_CFGR3_PINMUX0_Msk /*!< Pin GPIO multiplexer 0 */ #define SYSCFG_CFGR3_PINMUX0_0 (0x1UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000001 */ #define SYSCFG_CFGR3_PINMUX0_1 (0x2UL << SYSCFG_CFGR3_PINMUX0_Pos) /*!< 0x00000002 */ #define SYSCFG_CFGR3_PINMUX1_Pos (2U) -#define SYSCFG_CFGR3_PINMUX1_Msk (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x0000000C */ +#define SYSCFG_CFGR3_PINMUX1_Msk (0x3UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x0000000C */ #define SYSCFG_CFGR3_PINMUX1 SYSCFG_CFGR3_PINMUX1_Msk /*!< Pin GPIO multiplexer 1 */ #define SYSCFG_CFGR3_PINMUX1_0 (0x1UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x00000004 */ #define SYSCFG_CFGR3_PINMUX1_1 (0x2UL << SYSCFG_CFGR3_PINMUX1_Pos) /*!< 0x00000008 */ #define SYSCFG_CFGR3_PINMUX2_Pos (4U) -#define SYSCFG_CFGR3_PINMUX2_Msk (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000030 */ +#define SYSCFG_CFGR3_PINMUX2_Msk (0x3UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000030 */ #define SYSCFG_CFGR3_PINMUX2 SYSCFG_CFGR3_PINMUX2_Msk /*!< Pin GPIO multiplexer 2 */ #define SYSCFG_CFGR3_PINMUX2_0 (0x1UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000010 */ #define SYSCFG_CFGR3_PINMUX2_1 (0x2UL << SYSCFG_CFGR3_PINMUX2_Pos) /*!< 0x00000020 */ #define SYSCFG_CFGR3_PINMUX3_Pos (6U) -#define SYSCFG_CFGR3_PINMUX3_Msk (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x000000C0 */ +#define SYSCFG_CFGR3_PINMUX3_Msk (0x3UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x000000C0 */ #define SYSCFG_CFGR3_PINMUX3 SYSCFG_CFGR3_PINMUX3_Msk /*!< Pin GPIO multiplexer 3 */ #define SYSCFG_CFGR3_PINMUX3_0 (0x1UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x00000040 */ #define SYSCFG_CFGR3_PINMUX3_1 (0x2UL << SYSCFG_CFGR3_PINMUX3_Pos) /*!< 0x00000080 */ #define SYSCFG_CFGR3_PINMUX4_Pos (8U) -#define SYSCFG_CFGR3_PINMUX4_Msk (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000300 */ +#define SYSCFG_CFGR3_PINMUX4_Msk (0x3UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000300 */ #define SYSCFG_CFGR3_PINMUX4 SYSCFG_CFGR3_PINMUX4_Msk /*!< Pin GPIO multiplexer 4 */ #define SYSCFG_CFGR3_PINMUX4_0 (0x1UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000100 */ #define SYSCFG_CFGR3_PINMUX4_1 (0x2UL << SYSCFG_CFGR3_PINMUX4_Pos) /*!< 0x00000200 */ #define SYSCFG_CFGR3_PINMUX5_Pos (10U) -#define SYSCFG_CFGR3_PINMUX5_Msk (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000C00 */ +#define SYSCFG_CFGR3_PINMUX5_Msk (0x3UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000C00 */ #define SYSCFG_CFGR3_PINMUX5 SYSCFG_CFGR3_PINMUX5_Msk /*!< Pin GPIO multiplexer 5 */ #define SYSCFG_CFGR3_PINMUX5_0 (0x1UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000400 */ #define SYSCFG_CFGR3_PINMUX5_1 (0x2UL << SYSCFG_CFGR3_PINMUX5_Pos) /*!< 0x00000800 */ /***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/ -#define SYSCFG_ITLINE0_SR_EWDG_Pos (0U) -#define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */ +#define SYSCFG_ITLINE0_SR_WWDG_Pos (0U) +#define SYSCFG_ITLINE0_SR_WWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_WWDG_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE0_SR_WWDG SYSCFG_ITLINE0_SR_WWDG_Msk /*!< EWDG interrupt */ #define SYSCFG_ITLINE2_SR_RTC_Pos (1U) #define SYSCFG_ITLINE2_SR_RTC_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE2_SR_RTC SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC interrupt */ #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U) #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */ -#define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U) -#define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */ +#define SYSCFG_ITLINE4_SR_RCC_Pos (0U) +#define SYSCFG_ITLINE4_SR_RCC_Msk (0x1UL << SYSCFG_ITLINE4_SR_RCC_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE4_SR_RCC SYSCFG_ITLINE4_SR_RCC_Msk /*!< RCC interrupt */ #define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U) #define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */ @@ -5148,9 +5074,9 @@ typedef struct #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U) #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */ #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA1 Channel 3 Interrupt */ -#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) -#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ -#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ +#define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U) +#define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */ #define SYSCFG_ITLINE12_SR_ADC_Pos (0U) #define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */ #define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */ @@ -5751,27 +5677,27 @@ typedef struct /******************* Bit definition for TIM_CCR1 register *******************/ #define TIM_CCR1_CCR1_Pos (0U) -#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ +#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */ #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/* Legacy registers naming */ +#define TR1 AWD1TR +#define TR2 AWD2TR +#define TR3 AWD3TR + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ + __IO uint32_t CR; /*!< CRS control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBG_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief DMA Multiplexer + */ +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x30 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x34 */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x38 */ + uint32_t RESERVED3[11]; /*!< Reserved 3, 0x3C -- 0x5F */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18 */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */ + __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */ + __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */ + uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */ + __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x40 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */ + uint32_t RESERVED7[8]; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t BKP0R; /*!< Backup register 0, Address offset: 0x70 */ + __IO uint32_t BKP1R; /*!< Backup register 1, Address offset: 0x74 */ + __IO uint32_t BKP2R; /*!< Backup register 2, Address offset: 0x78 */ + __IO uint32_t BKP3R; /*!< Backup register 3, Address offset: 0x7C */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x0C -- 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Configuration Register, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */ + __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */ + __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */ + __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t CCIPR2; /*!< RCC Peripherals Independent Clocks Configuration Register2, Address offset: 0x58 */ + __IO uint32_t CSR1; /*!< RCC Control and status Register 1, Address offset: 0x5C */ + __IO uint32_t CSR2; /*!< RCC Control and status Register 2, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x1C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */ +} RTC_TypeDef; + + /** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + uint32_t RESERVED1[8]; /*!< Reserved 0x1C --0x38 */ + __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x3C */ + uint32_t RESERVED2[16]; /*!< Reserved 0x40 --0x7C */ + __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** +  * @brief Universal Serial Bus Full Speed Dual Role Device +  */ + +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register,   Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** +  * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table +  */ +typedef struct +{ + __IO uint32_t TXBD; /*! */ +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */ +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */ + +/******************** Bits definition for RTC_WPR register ******************/ +#define RTC_WPR_KEY_Pos (0U) +#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ +#define RTC_WPR_KEY RTC_WPR_KEY_Msk + +/******************** Bits definition for RTC_CALR register *****************/ +#define RTC_CALR_CALP_Pos (15U) +#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ +#define RTC_CALR_CALP RTC_CALR_CALP_Msk +#define RTC_CALR_CALW8_Pos (14U) +#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ +#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk +#define RTC_CALR_CALW16_Pos (13U) +#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ +#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk +#define RTC_CALR_CALM_Pos (0U) +#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ +#define RTC_CALR_CALM RTC_CALR_CALM_Msk +#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ +#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ +#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ +#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ +#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ +#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ +#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ +#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ +#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ + +/******************** Bits definition for RTC_SHIFTR register ***************/ +#define RTC_SHIFTR_ADD1S_Pos (31U) +#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ +#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk +#define RTC_SHIFTR_SUBFS_Pos (0U) +#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ +#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk +/******************** Bits definition for RTC_TSTR register *****************/ +#define RTC_TSTR_PM_Pos (22U) +#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */ +#define RTC_TSTR_HT_Pos (20U) +#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TSTR_HT RTC_TSTR_HT_Msk +#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TSTR_HU_Pos (16U) +#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TSTR_HU RTC_TSTR_HU_Msk +#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TSTR_MNT_Pos (12U) +#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk +#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TSTR_MNU_Pos (8U) +#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk +#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TSTR_ST_Pos (4U) +#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TSTR_ST RTC_TSTR_ST_Msk +#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TSTR_SU_Pos (0U) +#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TSTR_SU RTC_TSTR_SU_Msk +#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSDR register *****************/ +#define RTC_TSDR_WDU_Pos (13U) +#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */ +#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_TSDR_MT_Pos (12U) +#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ +#define RTC_TSDR_MT RTC_TSDR_MT_Msk +#define RTC_TSDR_MU_Pos (8U) +#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_TSDR_MU RTC_TSDR_MU_Msk +#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ +#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ +#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ +#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ +#define RTC_TSDR_DT_Pos (4U) +#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ +#define RTC_TSDR_DT RTC_TSDR_DT_Msk +#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ +#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ +#define RTC_TSDR_DU_Pos (0U) +#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ +#define RTC_TSDR_DU RTC_TSDR_DU_Msk +#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ +#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ +#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ +#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_TSSSR register ****************/ +#define RTC_TSSSR_SS_Pos (0U) +#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ +#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */ +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */ +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */ +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ + +#define SPI_I2S_SUPPORT /*!< I2S support */ + +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_CPHA_Pos (0U) +#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ +#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*! exti[22]*/ +#define SYSCFG_ITLINE25_SR_SPI1_Pos (0U) +#define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */ +#define SYSCFG_ITLINE26_SR_SPI2_Pos (0U) +#define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */ +#define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U) +#define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt */ +#define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U) +#define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */ +#define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! + -
@@ -33,27 +36,94 @@

Release Notes for  STM32C0xx CMSIS

Copyright © 2022 STMicroelectronics

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-
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Update History

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+

Update History

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Main Changes

-

Align flash register address with STM32C0 reference manual

+
    +
  • First official release of STM32C0xx CMSIS drivers to support +STM32C071xx devices
    • +
  • General updates to fix known defects and enhance implementation
    • +
  • Align version of bit and registers definition with the STM32C0 +reference manual
    • +
+

Contents

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  • Support of STM32C071xx devices: +
      +
    • Add “stm32c071xx.h” file
      • +
    • Add startup files “startup_stm32c071xx.s” for EWARM, STM32CubeIDE +and MDK-ARM toolchains
      • +
    • Add STM32C071xx devices linker files for EWARM and STM32CubeIDE +toolchains
      • +
    • +
  • Registers and bit field definitions updates : +
      +
    • Add DMAMUX1_RequestGenerator3_BASE and DMAMUX1_RequestGenerator3 +definitions
      • +
    • Remove DMA_IFCR_CGIF4, DMA_IFCR_CTCIF4, DMA_IFCR_CHTIF4 and +DMA_IFCR_CTEIF4 definitions
      • +
    • Add ADC_AWD2CR_AWD2CH_19, ADC_AWD2CR_AWD2CH_20, ADC_AWD2CR_AWD2CH_21 +and ADC_AWD2CR_AWD2CH_22 bits definitions
      • +
    • Add ADC_AWD3CR_AWD3CH_19, ADC_AWD3CR_AWD3CH_20, +ADC_AWD3CR_AWD3CH_21, ADC_AWD3CR_AWD3CH_22 bits definitions
      • +
    • Add FLASH_OPTR_SECURE_MUXING_EN bit definition
      • +
    • Correct Flash page number section mask (FLASH_CR_PNB_Msk)
      • +
    • Remove extra FLASH_ECCR register bits definitions
      • +
    • Correct masks values of FLASH_PCROP1ASR, FLASH_WRP1AR, FLASH_WRP1BR, +FLASH_WRP1BR, FLASH_PCROP1BER registers
      • +
    • Add FLASH_SIZE macro to compute Flash size value
      • +
    • Fix correct FLASH_OPTR_BORF_LEV and FLASH_OPTR_BORR_LEV +positions
      • +
    • Remove SYSCFG_CFGR1_BOOSTEN bit definition
      • +
    • Correct SYSCFG_CFGR3 register bits masks values
      • +
    • Change SYSCFG_ITLINE0_SR_EWDG bit definition naming by +SYSCFG_ITLINE0_SR_WWDG to be aligned with the reference manual
      • +
    • Change SYSCFG_ITLINE4_SR_CLK_CTRL bit definition naming by +SYSCFG_ITLINE4_SR_RCC to be aligned with the reference manual
      • +
    • Update IS_TIM_REMAP_INSTANCE and IS_TIM_ETRSEL_INSTANCE macros
      • +
    • Update TIM Capture/Compare masks values
      • +
    • Remove extra EXTI interrupts and events Masks
      • +
    • Remove extra PWR_SR2_REGLPF bits definition
      • +
    • Update some RCC_CFGR bit definitions +
        +
      • Remove RCC_CFGR_MCO2PRE_3 and RCC_CFGR_MCOPRE_3 bits definitions as +reserved
        • +
      • Update RCC_CFGR_MCO2PRE_Msk and RCC_CFGR_MCOPRE_Msk masks +values
        • +
      • +
    • +
+

Supported Devices

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  • STM32C011xx, STM32C031xx and STM32C071xx devices
    • +
- -
+ +

Main Changes

-

First official release version of bits and registers definition aligned with STM32C0 reference manual

-
+

Align flash register address with STM32C0 reference manual

+
+ + +

Main Changes

+

First official release version of bits and registers definition +aligned with STM32C0 reference manual

- +