From 520b9be2974aa2bdf5a778869e972f4ad24f7e94 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 4 Jul 2024 15:20:34 +0200 Subject: [PATCH 001/129] system(G4) update STM32G4xx HAL Drivers to v1.2.4 Included in STM32CubeG4 FW v1.6.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 499 +++++++++++++++++- .../STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h | 2 + .../Inc/stm32g4xx_hal_adc.h | 2 +- .../Inc/stm32g4xx_hal_adc_ex.h | 14 +- .../Inc/stm32g4xx_hal_comp.h | 322 +++++------ .../Inc/stm32g4xx_hal_cordic.h | 21 +- .../Inc/stm32g4xx_hal_cortex.h | 2 + .../Inc/stm32g4xx_hal_dac.h | 4 +- .../Inc/stm32g4xx_hal_dac_ex.h | 8 +- .../Inc/stm32g4xx_hal_fdcan.h | 4 +- .../Inc/stm32g4xx_hal_fmac.h | 12 +- .../Inc/stm32g4xx_hal_i2c_ex.h | 15 + .../Inc/stm32g4xx_hal_irda_ex.h | 221 +++++++- .../Inc/stm32g4xx_hal_lptim.h | 4 +- .../Inc/stm32g4xx_hal_opamp.h | 6 +- .../Inc/stm32g4xx_hal_opamp_ex.h | 6 +- .../Inc/stm32g4xx_hal_pcd.h | 17 +- .../Inc/stm32g4xx_hal_pcd_ex.h | 1 - .../Inc/stm32g4xx_hal_rcc_ex.h | 30 +- .../Inc/stm32g4xx_hal_sai.h | 4 + .../Inc/stm32g4xx_hal_sai_ex.h | 4 + .../Inc/stm32g4xx_hal_smartcard.h | 52 ++ .../Inc/stm32g4xx_hal_smbus_ex.h | 4 + .../Inc/stm32g4xx_hal_uart.h | 5 +- .../Inc/stm32g4xx_hal_uart_ex.h | 284 +++++++++- .../Inc/stm32g4xx_hal_usart.h | 55 +- .../Inc/stm32g4xx_ll_adc.h | 2 +- .../Inc/stm32g4xx_ll_bus.h | 2 +- .../Inc/stm32g4xx_ll_cordic.h | 28 +- .../Inc/stm32g4xx_ll_fmac.h | 6 - .../Inc/stm32g4xx_ll_lpuart.h | 15 + .../Inc/stm32g4xx_ll_pwr.h | 2 + .../Inc/stm32g4xx_ll_rcc.h | 10 + .../Inc/stm32g4xx_ll_rng.h | 2 +- .../Inc/stm32g4xx_ll_system.h | 9 +- .../Inc/stm32g4xx_ll_ucpd.h | 12 +- .../Inc/stm32g4xx_ll_utils.h | 7 +- .../STM32G4xx_HAL_Driver/Release_Notes.html | 314 +++++++---- .../STM32G4xx_HAL_Driver/Src/stm32g4xx_hal.c | 11 +- .../Src/stm32g4xx_hal_comp.c | 2 +- .../Src/stm32g4xx_hal_cordic.c | 2 +- .../Src/stm32g4xx_hal_cortex.c | 82 ++- .../Src/stm32g4xx_hal_cryp.c | 12 +- .../Src/stm32g4xx_hal_dac_ex.c | 15 +- .../Src/stm32g4xx_hal_dma.c | 2 +- .../Src/stm32g4xx_hal_flash_ex.c | 4 +- .../Src/stm32g4xx_hal_fmac.c | 7 +- .../Src/stm32g4xx_hal_gpio.c | 2 +- .../Src/stm32g4xx_hal_i2c.c | 40 +- .../Src/stm32g4xx_hal_opamp.c | 7 +- .../Src/stm32g4xx_hal_opamp_ex.c | 2 + .../Src/stm32g4xx_hal_pcd.c | 6 +- .../Src/stm32g4xx_hal_pcd_ex.c | 2 - .../Src/stm32g4xx_hal_pwr_ex.c | 8 +- .../Src/stm32g4xx_hal_qspi.c | 12 + .../Src/stm32g4xx_hal_rcc_ex.c | 45 +- .../Src/stm32g4xx_hal_sai.c | 10 +- .../Src/stm32g4xx_hal_sai_ex.c | 5 +- .../Src/stm32g4xx_hal_smartcard.c | 2 +- .../Src/stm32g4xx_hal_smbus_ex.c | 2 + .../Src/stm32g4xx_hal_uart.c | 24 + .../Src/stm32g4xx_hal_uart_ex.c | 2 +- .../Src/stm32g4xx_hal_usart.c | 17 +- .../Src/stm32g4xx_hal_usart_ex.c | 2 +- .../Src/stm32g4xx_ll_adc.c | 4 +- .../Src/stm32g4xx_ll_comp.c | 292 +++++----- .../Src/stm32g4xx_ll_dac.c | 12 +- .../Src/stm32g4xx_ll_fmac.c | 2 - .../Src/stm32g4xx_ll_i2c.c | 2 + .../Src/stm32g4xx_ll_rcc.c | 30 +- .../Src/stm32g4xx_ll_rng.c | 2 +- .../Src/stm32g4xx_ll_ucpd.c | 2 +- .../Src/stm32g4xx_ll_usart.c | 4 + .../STM32G4xx_HAL_Driver/_htmresc/favicon.png | Bin 4126 -> 0 bytes .../{mini-st_2020.css => mini-st.css} | 357 +++++++------ .../STM32G4xx_HAL_Driver/_htmresc/st_logo.png | Bin 0 -> 18616 bytes .../_htmresc/st_logo_2020.png | Bin 7520 -> 0 bytes .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 78 files changed, 2201 insertions(+), 840 deletions(-) delete mode 100644 system/Drivers/STM32G4xx_HAL_Driver/_htmresc/favicon.png rename system/Drivers/STM32G4xx_HAL_Driver/_htmresc/{mini-st_2020.css => mini-st.css} (78%) create mode 100644 system/Drivers/STM32G4xx_HAL_Driver/_htmresc/st_logo.png delete mode 100644 system/Drivers/STM32G4xx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 3caddb5298..22770e91a4 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -103,7 +103,15 @@ extern "C" { #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ - +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -207,6 +215,9 @@ extern "C" { #endif +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif /** * @} @@ -216,6 +227,11 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ /** * @} */ @@ -223,10 +239,13 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ +#if defined(STM32H5) || defined(STM32C0) +#else #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif /** * @} */ @@ -256,12 +275,22 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ defined(STM32F4) || defined(STM32G4) @@ -408,6 +437,9 @@ extern "C" { #endif /* STM32H7 */ +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -487,7 +519,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -504,6 +536,28 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ /** * @} @@ -547,6 +601,104 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ /** @@ -624,12 +776,13 @@ extern "C" { #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB */ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -646,6 +799,28 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -653,6 +828,27 @@ extern "C" { /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose * @{ */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -900,6 +1096,11 @@ extern "C" { * @} */ +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ /** * @} */ @@ -967,7 +1168,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1063,8 +1264,25 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - - +#if defined(STM32H5) || defined(STM32H7RS) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1248,6 +1466,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1398,7 +1620,7 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ -#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ /** * @} @@ -1448,7 +1670,9 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ @@ -1458,7 +1682,7 @@ extern "C" { * @} */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -1482,6 +1706,10 @@ extern "C" { * @{ */ +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ /** * @} @@ -1604,7 +1832,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1692,6 +1920,92 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif /** * @} @@ -1700,6 +2014,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS */ /** * @} @@ -2014,8 +2334,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2048,8 +2368,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2106,8 +2426,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2124,7 +2444,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2426,6 +2746,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3349,8 +3675,12 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3452,8 +3782,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3462,7 +3794,124 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ /** * @} @@ -3480,7 +3929,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3540,6 +3991,10 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h index 5786f8a428..e67a2033bf 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h @@ -601,7 +601,9 @@ void HAL_SYSCFG_DisableIOSwitchBooster(void); void HAL_SYSCFG_EnableIOSwitchVDD(void); void HAL_SYSCFG_DisableIOSwitchVDD(void); +#if defined(CCMSRAM_BASE) void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page); +#endif /* CCMSRAM_BASE */ /** * @} diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h index 97bc1bbce0..81622aae4f 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h @@ -1305,7 +1305,7 @@ out-of-window sample to raise flag or interrupt */ ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \ ((__REGTRIG__) == ADC_SOFTWARE_START) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h index 7acf6e663c..d893d33b6d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h @@ -631,7 +631,7 @@ typedef struct : \ RESET \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ @@ -790,7 +790,7 @@ typedef struct : \ ((__HANDLE_SLAVE__)->Instance = NULL) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) /** * @brief Set handle instance of the ADC slave associated to the ADC master. * @param __HANDLE_MASTER__ ADC master handle. @@ -816,7 +816,7 @@ typedef struct #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \ ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) #endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ @@ -828,7 +828,7 @@ typedef struct #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \ ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4)) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) @@ -947,7 +947,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_0) || \ ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ @@ -1069,7 +1069,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_13))) || \ ((((__HANDLE__)->Instance) == ADC3) && \ ((__CHANNEL__) == ADC_CHANNEL_15))) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \ ((__CHANNEL__) == ADC_CHANNEL_2) || \ ((__CHANNEL__) == ADC_CHANNEL_3) || \ @@ -1239,7 +1239,7 @@ typedef struct ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \ ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h index f575d605e3..2aecfde90d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h @@ -369,16 +369,16 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ } while(0) @@ -453,17 +453,17 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ } while(0) @@ -537,19 +537,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP3 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) +#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + } while(0) /** * @brief Disable the COMP3 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \ - } while(0) +#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3);\ + } while(0) /** * @brief Enable the COMP3 EXTI line in interrupt mode. @@ -621,19 +621,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP4 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - } while(0) +#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + } while(0) /** * @brief Disable the COMP4 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \ - } while(0) +#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4);\ + } while(0) /** * @brief Enable the COMP4 EXTI line in interrupt mode. @@ -677,7 +677,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4) -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) /** * @brief Enable the COMP5 EXTI line rising edge trigger. * @retval None @@ -706,19 +706,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP5 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - } while(0) +#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + } while(0) /** * @brief Disable the COMP5 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \ - } while(0) +#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5);\ + } while(0) /** * @brief Enable the COMP5 EXTI line in interrupt mode. @@ -762,8 +762,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5) -#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/ +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) /** * @brief Enable the COMP6 EXTI line rising edge trigger. * @retval None @@ -792,19 +792,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP6 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - } while(0) +#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ + LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ + } while(0) /** * @brief Disable the COMP6 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \ - } while(0) +#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6);\ + LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6);\ + } while(0) /** * @brief Enable the COMP6 EXTI line in interrupt mode. @@ -848,8 +848,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6) -#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/ +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) /** * @brief Enable the COMP7 EXTI line rising edge trigger. * @retval None @@ -878,19 +878,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP7 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - } while(0) +#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ + LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ + } while(0) /** * @brief Disable the COMP7 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \ - } while(0) +#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7);\ + LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7);\ + } while(0) /** * @brief Enable the COMP7 EXTI line in interrupt mode. @@ -934,7 +934,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer */ #define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7) -#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ /** * @} */ @@ -957,11 +957,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30) /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */ #define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */ -#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ /** * @} */ @@ -994,7 +994,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __INSTANCE__ specifies the COMP instance. * @retval value of @ref COMP_ExtiLine */ -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \ @@ -1007,7 +1007,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \ :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \ : COMP_EXTI_LINE_COMP4) -#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ /** * @} */ @@ -1018,63 +1018,63 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \ ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)) -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ (((__COMP_INSTANCE__) == COMP1) && \ (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP2) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP3) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP4) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP5) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP6) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP7) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \ )) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) -#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) ||\ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \ (((__COMP_INSTANCE__) == COMP1) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP2) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ ) || \ (((__COMP_INSTANCE__) == COMP3) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \ ) || \ (((__COMP_INSTANCE__) == COMP4) && \ - (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) ||\ - ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ + (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \ )) #endif @@ -1098,159 +1098,159 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Better use IS_COMP_BLANKINGSRC_INSTANCE instead */ /* Macro kept for compatibility with other STM32 series */ #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ + || \ + (((__INSTANCE__) == COMP2) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ + || \ + (((__INSTANCE__) == COMP3) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ + || \ + (((__INSTANCE__) == COMP4) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || \ - (((__INSTANCE__) == COMP5) && \ + || \ + (((__INSTANCE__) == COMP5) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \ - || \ - (((__INSTANCE__) == COMP6) && \ + || \ + (((__INSTANCE__) == COMP6) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \ - || \ - (((__INSTANCE__) == COMP7) && \ + || \ + (((__INSTANCE__) == COMP7) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ + || \ + (((__INSTANCE__) == COMP2) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ + || \ + (((__INSTANCE__) == COMP3) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ + || \ + (((__INSTANCE__) == COMP4) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - ((((__INSTANCE__) == COMP1) && \ + ((((__INSTANCE__) == COMP1) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \ - || \ - (((__INSTANCE__) == COMP2) && \ + || \ + (((__INSTANCE__) == COMP2) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \ - || \ - (((__INSTANCE__) == COMP3) && \ + || \ + (((__INSTANCE__) == COMP3) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \ - || \ - (((__INSTANCE__) == COMP4) && \ + || \ + (((__INSTANCE__) == COMP4) && \ (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \ ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ - || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \ + || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \ ) -#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */ #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h index 2f06845385..ddb7a7b0a3 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h index 0fd9deec34..c1fbd86574 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h @@ -295,6 +295,8 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h index a331446b98..d196be0f09 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h @@ -499,7 +499,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) -#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((DACX) == DAC2) ? \ ((CHANNEL) == DAC_CHANNEL_1) \ @@ -510,7 +510,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #define IS_DAC_CHANNEL(DACX, CHANNEL) \ (((CHANNEL) == DAC_CHANNEL_1) || \ ((CHANNEL) == DAC_CHANNEL_2)) -#endif /* STM32G474xx || STM32G484xx || STM32G473xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx */ #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ ((ALIGN) == DAC_ALIGN_12B_L) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h index d042af1a6f..bbc7f573a0 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h @@ -103,7 +103,7 @@ extern "C" { /** @defgroup DACEx_Private_Macros DACEx Private Macros * @{ */ -#if defined(STM32G474xx) || defined(STM32G484xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ @@ -153,9 +153,9 @@ extern "C" { : ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) -#endif /* STM32G474xx || STM32G484xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx */ -#if defined(STM32G474xx) || defined(STM32G484xx) +#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) #define IS_DAC_TRIGGER2(DACX, TRIGGER) \ (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \ @@ -201,7 +201,7 @@ extern "C" { :((TRIGGER) == DAC_TRIGGER_T8_TRGO) \ ) \ ) -#endif /* STM32G474xx || STM32G484xx */ +#endif /* STM32G414xx || STM32G474xx || STM32G484xx */ #define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \ ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h index e956f7f693..4e9bb25ad0 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h index ca8926986d..48a94b6127 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h @@ -243,10 +243,7 @@ typedef struct * @} */ - /* Exported constants --------------------------------------------------------*/ - - /** @defgroup FMAC_Exported_Constants FMAC Exported Constants * @{ */ @@ -357,7 +354,6 @@ typedef struct * @} */ - /* Exported variables --------------------------------------------------------*/ /** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ @@ -499,7 +495,7 @@ typedef struct * @} */ -/* Private Macros-----------------------------------------------------------*/ +/* Private Macros-------------------------------------------------------------*/ /** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -578,9 +574,9 @@ typedef struct * @param __FUNCTION__ ID of the filter function. * @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid) */ -#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ - (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ - (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h index 840beeaed8..3042f9eb1f 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h @@ -60,7 +60,11 @@ extern "C" { #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ #define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#if defined(SYSCFG_CFGR1_I2C3_FMP) #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /* SYSCFG_CFGR1_I2C3_FMP */ #if defined(SYSCFG_CFGR1_I2C4_FMP) #define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ #else @@ -138,6 +142,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) +#if defined (I2C3) #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ @@ -147,6 +152,16 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) +#else +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) +#endif /* I2C3 */ /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h index 24df2ebd4e..c1f87f4f7d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h @@ -69,7 +69,99 @@ extern "C" { * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ -#if defined(UART5) +#if defined(UART5) && !defined(USART3) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(UART5) && defined(USART3) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -182,7 +274,78 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#elif defined(UART4) +#elif defined(UART4) && !defined(USART3) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(UART4) && defined(USART3) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -274,7 +437,7 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#else +#elif defined(USART3) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -345,7 +508,57 @@ extern "C" { (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif /* UART5 */ +#else +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* UART5 && !USART3 */ /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h index 6ceca1a251..82176c33dd 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h @@ -766,7 +766,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) -#if defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx) +#if defined(STM32G414xx) || defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx) #define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ @@ -793,7 +793,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); ((__TRIG__) == LPTIM_TRIGSOURCE_7) || \ ((__TRIG__) == LPTIM_TRIGSOURCE_8) || \ ((__TRIG__) == LPTIM_TRIGSOURCE_9)) -#endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */ +#endif /* STM32G414xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */ #define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h index a8849057a0..e00b8280af 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h @@ -31,6 +31,8 @@ extern "C" { * @{ */ +#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6) + /** @addtogroup OPAMP * @{ */ @@ -560,14 +562,14 @@ OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, * @} */ +#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */ + /** * @} */ - #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_OPAMP_H */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h index 4ec3601183..72d48cf907 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h @@ -31,6 +31,8 @@ extern "C" { * @{ */ +#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6) + /** @addtogroup OPAMPEx OPAMPEx * @{ */ @@ -71,15 +73,15 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA * @} */ +#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */ + /** * @} */ - #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_OPAMP_EX_H */ - diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h index 1aee8202d1..52e06a94b8 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h @@ -806,20 +806,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); \ *(pdwReg) &= 0x3FFU; \ \ - if ((wCount) > 62U) \ + if ((wCount) == 0U) \ { \ - PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if ((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ } \ else \ { \ - if ((wCount) == 0U) \ - { \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else \ - { \ - PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h index afb606d6f6..3d85758a3a 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h index 6cebf27795..10206ee17d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h @@ -53,9 +53,10 @@ typedef struct uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - +#if defined(USART3) uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ +#endif /* UART3 */ #if defined(UART4) uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. @@ -353,6 +354,7 @@ typedef struct * @} */ +#if defined(SPI_I2S_SUPPORT) /** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source * @{ */ @@ -363,6 +365,8 @@ typedef struct /** * @} */ +#endif /* SPI_I2S_SUPPORT */ + #if defined(FDCAN1) /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source * @{ @@ -827,6 +831,8 @@ typedef struct * * @retval None */ + +#if defined(SAI1) #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__)) @@ -839,7 +845,9 @@ typedef struct * */ #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)) +#endif /* SAI1 */ +#if defined(SPI_I2S_SUPPORT) /** * @brief Macro to configure the I2S clock source. * @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived @@ -864,6 +872,7 @@ typedef struct * */ #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL))) +#endif /* SPI_I2S_SUPPORT */ #if defined(FDCAN1) /** @@ -1404,7 +1413,6 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32G431xx) || defined(STM32G441xx) - #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ @@ -1423,6 +1431,22 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32G414xx) +#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) #elif defined(STM32GBK1CB) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ @@ -1514,11 +1538,13 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) +#if defined(SAI1) #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) +#endif /* SAI1 */ #define IS_RCC_I2SCLKSOURCE(__SOURCE__) \ (((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h index 771d4d6232..d8311b2ad1 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h @@ -31,6 +31,8 @@ extern "C" { * @{ */ +#if defined(SAI1) + /** @addtogroup SAI * @{ */ @@ -943,6 +945,8 @@ uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); * @} */ +#endif /* SAI1 */ + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h index 05771bea8b..86a9625637 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h @@ -31,6 +31,8 @@ extern "C" { * @{ */ +#if defined(SAI1) + /** @addtogroup SAIEx * @{ */ @@ -92,6 +94,8 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, * @} */ +#endif /* SAI1 */ + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h index a2f700dd11..d765c0f4f2 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h @@ -859,6 +859,7 @@ typedef enum * @param __CLOCKSOURCE__ output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART3) #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -929,6 +930,57 @@ typedef enum (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#else +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART3 */ /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on G4 (150 MHz) diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus_ex.h index 5043329ea6..7ddf7706b1 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus_ex.h @@ -51,7 +51,11 @@ extern "C" { #define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ #define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ #define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#if defined(SYSCFG_CFGR1_I2C3_FMP) #define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define SMBUS_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /* SYSCFG_CFGR1_I2C3_FMP */ #if defined(SYSCFG_CFGR1_I2C4_FMP) #define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ #else diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h index bb06ee89f0..2f308b3330 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h @@ -1230,7 +1230,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1245,8 +1245,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h index 34c17155ef..0c56e2790d 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h @@ -199,7 +199,7 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#if defined(UART5) +#if defined(UART5) && defined(USART3) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -333,7 +333,120 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#elif defined(UART4) +#elif defined(UART5) && !defined(USART3) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(UART4) && defined(USART3) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -446,7 +559,99 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#else +#elif defined(UART4) && !defined(USART3) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#elif defined(USART3) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -538,7 +743,78 @@ HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef * (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) -#endif /* UART5 */ +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* UART5 && !USART3 */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h index 8e012b8567..7c305b8760 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h @@ -704,8 +704,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. @@ -722,6 +721,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ +#if defined(USART3) #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -792,6 +792,57 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0) +#endif /* USART3 */ /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h index dc64ef1a41..5621f09d32 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h @@ -2873,7 +2873,7 @@ Refer to device datasheet for ADC5 & OPAMP5 availability */ ) \ ) \ ) -#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) +#elif defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ ((((__ADC_INSTANCE__) == ADC1) \ &&( \ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h index a336346960..ffd3b7be63 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h @@ -93,7 +93,7 @@ extern "C" { #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN -#define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN +#define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSRAMSMEN #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN #define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN #if defined(ADC345_COMMON) diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h index 8adb69beb8..5abc53203b 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h index 102cac0ff5..63fac203ef 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h index e3f996ac17..0c9a894980 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h @@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h index e3c1bef8f6..4a5a0c9c6e 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h @@ -783,6 +783,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) return ((temp == (PWR_CR3_APC))?1U:0U); } +#if defined(SRAM2_BASE) /** * @brief Enable SRAM2 content retention in Standby mode * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention @@ -816,6 +817,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) return ((temp == (PWR_CR3_RRS))?1U:0U); } +#endif /* SRAM2_BASE */ /** * @brief Enable the WakeUp PINx functionality * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h index 9fef6c1432..eb9d9f40e9 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h @@ -319,10 +319,12 @@ typedef struct #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#if defined(RCC_CCIPR_USART3SEL) #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#endif /* RCC_CCIPR_USART3SEL */ /** * @} */ @@ -472,7 +474,9 @@ typedef struct */ #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */ #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */ +#if defined(RCC_CCIPR_USART3SEL) #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */ +#endif /* RCC_CCIPR_USART3SEL */ /** * @} */ @@ -503,7 +507,9 @@ typedef struct */ #define LL_RCC_I2C1_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ #define LL_RCC_I2C2_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ +#if defined(RCC_CCIPR_I2C3SEL) #define LL_RCC_I2C3_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR << 24U) | ((uint32_t)RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ +#endif /* RCC_CCIPR_I2C3SEL */ #if defined(RCC_CCIPR2_I2C4SEL) #define LL_RCC_I2C4_CLKSOURCE (((uint32_t)RCC_OFFSET_CCIPR2 << 24U) | ((uint32_t)RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ #endif /* RCC_CCIPR2_I2C4SEL */ @@ -1602,6 +1608,7 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource); } +#if defined(SAI1) /** * @brief Configure SAIx clock source * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource @@ -1618,7 +1625,9 @@ __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource); } +#endif /* SAI1 */ +#if defined(SPI_I2S_SUPPORT) /** * @brief Configure I2S clock source * @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource @@ -1633,6 +1642,7 @@ __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) { MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource); } +#endif /* SPI_I2S_SUPPORT */ #if defined(FDCAN1) /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h index dce1306618..90d95e545e 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h @@ -369,7 +369,7 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h index e90aebbacb..58aedfca82 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h @@ -187,6 +187,7 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP * @{ */ +#if defined(CCMSRAM_BASE) #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */ @@ -197,6 +198,7 @@ extern "C" { #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */ +#endif /* CCMSRAM_BASE */ #if defined(SYSCFG_SWPR_PAGE10) #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */ #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */ @@ -261,7 +263,9 @@ extern "C" { #if defined(I2C2) #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ #endif /* I2C2 */ +#if defined(I2C3) #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/ +#endif /* I2C3 */ #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ /** * @} @@ -754,6 +758,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU)); } +#if defined (CCMSRAM_BASE) /** * @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is * automatically cleared at the end of the CCMSRAM erase operation.) @@ -779,6 +784,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void) return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL); } +#endif /* CCMSRAM_BASE */ /** * @brief Set connections to TIM1/8/15/16/17 Break inputs * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n @@ -834,6 +840,7 @@ __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void) SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF); } +#if defined(CCMSRAM_BASE) /** * @brief Enable CCMSRAM page write protection * @note Write protection is cleared only by a system reset @@ -902,7 +909,7 @@ __STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void) WRITE_REG(SYSCFG->SKR, 0xCA); WRITE_REG(SYSCFG->SKR, 0x53); } - +#endif /* CCMSRAM_BASE */ /** * @} */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h index 2cafeaa4cc..0e90d7edc8 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h @@ -847,7 +847,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1012,7 +1012,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1177,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1350,7 +1350,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1501,7 +1501,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset interrupt * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1833,7 +1833,7 @@ __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) */ ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); +ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, const LL_UCPD_InitTypeDef *UCPD_InitStruct); void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); /** diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h index 60510db505..e8c955f107 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h +++ b/system/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h @@ -160,14 +160,13 @@ typedef struct */ #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ #define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */ -#if defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32G471xx) || \ - defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || \ - defined (STM32G484xx) +#if defined (STM32G431xx) || defined (STM32G414xx) || defined (STM32G441xx) || defined (STM32G471xx) || \ + defined (STM32G473xx) || defined (STM32G483xx) || defined (STM32G474xx) || defined (STM32G484xx) #define LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 0x00000002U /*!< LQFP100 \ LQFP80 package type */ #define LL_UTILS_PACKAGETYPE_LQFP100 LL_UTILS_PACKAGETYPE_LQFP100_LQFP80 /*!< For backward compatibility */ #else #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#endif /* STM32G431xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx ||STM32G474xx || STM32G484xx */ +#endif /* STM32G431xx || STM32G414xx || STM32G441xx || STM32G471xx || STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */ #define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */ #define LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 0x00000007U /*!< LQFP128 \ UFBGA121 package type */ #define LL_UTILS_PACKAGETYPE_LQFP128 LL_UTILS_PACKAGETYPE_LQFP128_UFBGA121 /*!< For backward compatibility */ diff --git a/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html index c38e0b033e..0799e962f4 100644 --- a/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32G4xx_HAL_Driver/Release_Notes.html @@ -5,13 +5,16 @@ Release Notes for STM32G4xx HAL Drivers - - + @@ -24,7 +27,7 @@

Release Notes for STM32G4xx HAL Drivers

Copyright © 2019 STMicroelectronics

- +

Purpose

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

@@ -37,14 +40,103 @@

Purpose

  • Full features coverage of the all the supported peripherals.
    • -
    -

    Update History

    +
    +

    Update History

    - +

    Main Changes

    Maintenance Release

      +

    • Add support of STM32G414xx devices.

      • +

    • General updates to fix known defects and enhancements implementation.

      • +

    • HAL DAC update

      +
        +
      • Update HAL_DACEx_SelfCalibrate() API to manage case of calibration factor equal to range maximum value.
        • +
      • +

    • HAL CORTEX update

      +
        +
      • Update HAL_MPU_ConfigRegion() API to allow the configuration of the MPU registers independently of the value of Enable/Disable field.
        • +
      • Add new HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion() APIs.
        • +
      • +

    • HAL QSPI update

      +
        +
      • Clear AR register after CCR to avoid new transfer when address is not needed.
        • +
      • +

    • HAL I2C update

      +
        +
      • Code quality enhancement MISRA-C 2012 Rule-13.5 within the HAL_I2C_Master_Abort_IT() API: +
          +
        • Add a temporary variable to get the value to check before comparison.
          • +
        • +
      • Add abort memory management to HAL_I2C_Master_Abort_IT() API.
        • +
      • Move the prefetch process in HAL_I2C_Slave_Transmit() API.
        • +
      • +

    • HAL SPI update

      +
        +
      • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers..
        • +
      • +

    • HAL/LL TIM update

      +
        +
      • Fixed typo in PWM asymmetric mode related constants.
        • +
      • +

    • HAL UART update

      +
        +
      • Add HAL_UART_RXEVENT_IDLE event notification to user in case of HAL_UARTEx_ReceiveToIdle_DMA() use with Circular DMA, even if occurring just after TC event.
        • +
      • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with RM.
        • +
      • Correct wrong comment in HAL_UARTEx_DisableFifoMode() API.
        • +
      • Ensure UART Rx buffer is not written beyond boundaries in case of RX FIFO reception in Interrupt mode.
        • +
      • +

    • HAL USART update

      +
        +
      • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with RM.
        • +
      • Correct wrong comment in HAL_USARTEx_DisableFifoMode() API.
        • +
      • Improve the visibility of the SPI mode support in HAL USART description.
        • +
      • +

    • HAL CRYP update

      +
        +
      • Code quality enhancement MISRA-C 2012 Rule-10.4 within HAL_CRYP_IRQHandler() API.
        • +
      • +

    • HAL FDCAN update

      +
        +
      • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
        • +
      • +

    • LL BUS update

      +
        +
      • Update macro definition LL_AHB2_GRP1_PERIPH_CCM.
        • +
      • +

    • LL LPUART update

      +
        +
      • Add LL_LPUART_RequestTxDataFlush() API allowing TX FIFO flush request.
        • +
      • +

    • LL UCPD update

      +
        +
      • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
        • +
      • Fix typo in Doxygen sections.
        • +
      • +
    +

    Development Toolchains and Compilers

    +
      +
    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9 + ST-LINKV2
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38 + ST-LINKV2
      • +
    • STM32CubeIDE toolchain (gcc9_2020_q2_update) V1.14.0
      • +
    +

    Supported Devices

    +
      +
    • STM32G431xx/41xx
      • +
    • STM32G471xx
      • +
    • STM32G414/73/83xx
      • +
    • STM32G474/84xx
      • +
    • STM32G491/A1xx
      • +
    +
    +
    +
    + +
    +

    Main Changes

    +

    Maintenance Release

    +
    • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
    • HAL Generic update
        @@ -247,13 +339,13 @@

        Maintenance Release

      • Fix a note about Ticks parameter.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.9 + ST-LINKV2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.38 + ST-LINKV2
    • STM32CubeIDE toolchain (gcc9_2020_q2_update) V1.14.0
    -

    Supported Devices

    +

    Supported Devices

    • STM32G431/41xx
    • STM32G471xx
      • @@ -266,29 +358,29 @@

      Supported Devices

      -

      Main Changes

      -

      Maintenance Release

      +

      Main Changes

      +

      Maintenance Release

      • General updates to fix known defects and enhancements implementation.

        • -
      • HAL/LL ADC update +

      • HAL/LL ADC update

        • Update HAL_ADC_Start_DMA() API to avoid return error when using Independent instance with multimode activated.
        • Update of the TEMPSENSOR_CAL2_TEMP value in the ll_adc.h file.
        • Update LL_ADC_SetChannelSingleDiff() API to be compliant with ARM CLang compiler v6.16.
        • -
      • HAL/LL RCC update +

      • HAL/LL RCC update

        • Add missing API IsEnabled for PLL "domain" output.
        • Enhance RCC_MCOx in order to support both MCO number (PA8 and PG10) and AF mapping.
        • -
      • HAL/LL USART update +

      • HAL/LL USART update

        • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
        • Add const qualifier for read only pointers.
        • Improve header description of USART_WaitOnFlagUntilTimeout() function
        • Add a check on the USART parity before enabling the parity error interrupt.
        • -
      • HAL/LL UART update +

      • HAL/LL UART update

        • Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA().
        • Correction on UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback
          • @@ -298,51 +390,51 @@

          Maintenance Release

        • Add const qualifier for read only pointers.
        • Fix wrong cast when computing the USARTDIV value in UART_SetConfig().
        • -
      • LL LPTIM update +

      • LL LPTIM update

        • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable().
        • -
      • LL TIM update +

      • LL TIM update

        • Update LL_TIM_OC_SetPulseWidth implementation to properly align the PulseWidth input value with the TIM_ECR register.
        • Fix wrong compile switch used in TIM_LL_EC_DMABURST_BASEADDR constant definitions.
        • -
      • LL LPUART update +

      • LL LPUART update

        • Remove useless TXFECF reference from LL LPUART driver.
        • -
      • HAL IRDA update +

      • HAL IRDA update

        • Improve header description of IRDA_WaitOnFlagUntilTimeout() function
        • Add a check on the IRDA parity before enabling the parity error interrupt.
        • Add const qualifier for read only pointers.
        • Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig().
        • -
      • HAL SMARTCARD update +

      • HAL SMARTCARD update

        • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function.
        • Add const qualifier for read only pointers.
        • Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig().
        • -
      • HAL/LL SPI update +

      • HAL/LL SPI update

        • Updated to fix MISRA-C 2012 Rule-13.2.
        • Update LL_SPI_TransmitData8() API to avoid casting the result to 8 bits.
        • -
      • HAL RTC update +

      • HAL RTC update

        • Update __HAL_RTC_…(HANDLE, …) macros to access registers through (HANDLE)->Instance pointer and avoid “unused variable†warnings.
        • -
      • HAL CRYP update +

      • HAL CRYP update

        • CRYP_AESCCM_Process_IT() update to manage header lengths in bytes or words when header length is less than 16 bytes.
        • -
      • HAL HRTIM update +

      • HAL HRTIM update

        • Fix compilation ARMCLANG -Wparenteses-equality warnings.
        • Fix missing initial update when Resynchronized update is used.
        • -
      • HAL FLASH update +

      • HAL FLASH update

        • Update to support STM32G4 part numbers with 256K flash
        • Disable ICache while Flash programming. @@ -350,27 +442,27 @@

          Maintenance Release

        • Update HAL_FLASHEx_Erase() to remove __HAL_FLASH_INSTRUCTION_CACHE_DISABLE().
      -
    • HAL USB update +

    • HAL USB update

      • HAL PCD: add fix transfer complete for IN Interrupt transaction in single buffer mode
      • -
    • HAL GPIO update +

    • HAL GPIO update

      • Reorder EXTI configuration sequence in order to avoid unexpected level detection.
      • Optimize assertion control for GPIO Pull mode in HAL_GPIO_Init() API.
      • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected.
      • -
    • HAL EXTI update +

    • HAL EXTI update

      • Update HAL_EXTI_GetConfigLine() API to set default configuration value of Trigger and GPIOSel before checking each corresponding registers.
      • -
    • HAL USART update +

    • HAL USART update

      • Improve header description of USART_WaitOnFlagUntilTimeout() function
      • Add a check on the USART parity before enabling the parity error interrupt.
      • Fix compilation warnings generated with ARMV6 compiler.
      • -
    • HAL I2C update +

    • HAL I2C update

      • Update I2C_IsAcknowledgeFailed() API to avoid I2C in busy state if NACK received after transmitting register address.
      • Update to handle errors in polling mode. @@ -380,7 +472,7 @@

        Maintenance Release

      • Update to fix issue detected due to low system frequency execution (HSI).
      • Declare an internal macro link to DMA macro to check remaining data: I2C_GET_DMA_REMAIN_DATA.
      • -
    • HAL SMBUS update +

    • HAL SMBUS update

      • Add the support of wake up capability.
          @@ -395,26 +487,26 @@

          Maintenance Release

        • Add flush on TX register.
      • -
    • HAL IWDG update +

    • HAL IWDG update

      • Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).
      • -
    • HAL RNG update +

    • HAL RNG update

      • Update timeout mechanism to avoid false timeout detection in case of preemption.
      • -
    • HAL NAND update +

    • HAL NAND update

      • Update implementation of “HAL_NAND_Write_Page_16b†and “HAL_NAND_Read_Page_16b†APIs implementation to fix an issue with the page calculation of 8 bits memories.
    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-LINKV2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINKV2
    • STM32CubeIDE toolchain (gcc9_2020_q2_update) V1.7.0
    -

    Supported Devices

    +

    Supported Devices

    • STM32G431/41xx
    • STM32G471xx
      • @@ -427,31 +519,31 @@

      Supported Devices

      -

      Main Changes

      -

      Maintenance Release

      +

      Main Changes

      +

      Maintenance Release

      • General updates to fix known defects and enhancements implementation

        • -
      • HAL
        • -
      • General updates to fix known defects and enhancements implementation.
        • -
      • Support for new ARM compiler Keil V6.
        • -
      • Added new defines for ARM compiler V6: +

      • HAL

        • +

      • General updates to fix known defects and enhancements implementation.

        • +

      • Support for new ARM compiler Keil V6.

        • +

      • Added new defines for ARM compiler V6:

        • __weak
        • __packed
        • __NOINLINE
        • -
      • LL RCC update +

      • LL RCC update

        • Private functions made static.
        • -
      • HAL CRYP update +

      • HAL CRYP update

        • Correction made for the Official NIST CCM test pattern ciphering failing when header length is null.
        • GCM/GMAC/CCM data header is now fed using DMA instead of polling.
        • Fixed CRYP HAL driver to manage GCM header lengths not multiple of 4 bytes in 8-bit, 16-bit and 32-bit data types.
        • Fixed handling of AUD with size not multiple of 4 bytes in CRYP_AESGCM_Process_IT for GCM.
        • -
      • HAL RTC Update +

      • HAL RTC Update

        • New APIs to subtract or add one hour to the calendar in one single operation without going through the initialization procedure (Daylight Saving):
            @@ -465,37 +557,37 @@

            Maintenance Release

          • Updated HAL_RTC_SetTimeStamp() API to call __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT before configuring the TimeStamp.
        • -
      • HAL/LL TIM update +

      • HAL/LL TIM update

        • Updated HAL_TIMEx_OnePulseN_Start() and HAL_TIMEx_OnePulseN_Stop() APIs (pooling and IT mode) to take into consideration all OutputChannel parameters.
        • Corrected reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode.
        • Updated LL_TIM_GetCounterMode() API to return the correct counter mode.
        • -
      • HAL/LL LPTIM update +

      • HAL/LL LPTIM update

        • Updated HAL_LPTIM_Init() API implementation to configure digital filter for external clock when LPTIM is configured with internal clock source.
        • -
      • HAL/LL HRTIM update +

      • HAL/LL HRTIM update

        • IRQ handlers optimized by reducing the multiple read-accesses to ISR and IER registers to one read-access per register.
        • LL_HRTIM_FLT_SetSrc() API updated to avoid overwriting the content of FLTINR2 register on successive calls.
        • -
      • HAL EXTI update +

      • HAL EXTI update

        • __EXTI__LINE is now used instead of LINE which is a standard C macro.
        • -
      • HAL OPAMP update +

      • HAL OPAMP update

        • Corrected OPAMPs outputs for the STM32G4 device table to be coherent with reference manual.
        • -
      • HAL/LL ADC Update +

      • HAL/LL ADC Update

        • Update HAL_ADC_DeInit() to avoid ADC hardware resource deinitialization when other ADC instances sharing the same common ADC instance are disable.
        • Update temperature sensor stabilization time management.
        • Update timeout mechanism to avoid false timeout detection in case of preemption.
        • Align the defined value of internal regulator stabilization time (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US) with product documentation (20us instead of 10us).
        • -
      • HAL DAC update +

      • HAL DAC update

        • Updated HAL_DAC_Stop_DMA() API to not return HAL_ERROR when DAC is already disabled.
        • Updated HAL_DAC_ConfigChannel to return the right timeout error for channel 2.
          • @@ -505,7 +597,7 @@

          Maintenance Release

        • (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)) instead of DAC_CR_TEN2
      -
    • HAL NOR Update +

    • HAL NOR Update

      • Corrected how p_endaddress is computed and how p_currentaddress is used in the HAL_NOR_ProgramBuffer() API.
      • NOR command sets can now be selected by manufacturer code, as specified in JEDEC JEP137B 2004-05, using NOR_HandleTypeDef field CommandSet. the following APIs have been updated: @@ -534,27 +626,27 @@

        Maintenance Release

    • Updated multiple APIs to treat separately the different memory types.
    -
  • LL FMC Update +

  • LL FMC Update

    • Updated FMC_NORSRAM_Extended_Timing_Init() API to manage the “bus turn around duration†parameter availability.
    • Updated FMC_NORSRAM_Init() API to resolve compilation issue with Microsoft Visual Studio 2017.
    • -
  • HAL NAND update +

  • HAL NAND update

    • Updated HAL_NAND_Read_SpareArea_16b() and HAL_NAND_Write_SpareArea_16b() APIs to fix the column address calculation.
    • -
  • HAL/LL SMARTCARD update +

  • HAL/LL SMARTCARD update

    • Fixed invalid initialization of SMARTCARD configuration by removing the FIFO mode configuration.
    • Fixed typos in SMARTCARD State definition description.
    • Optimized stack usage for multiple APIs.
    • -
  • HAL/LL IRDA update +

  • HAL/LL IRDA update

    • Fixed typos in IRDA State definition description.
    • Optimized stack usage for multiple APIs.
    • -
  • HAL/LL UART update +

  • HAL/LL UART update

    • Enhanced reception for idle services (ReceptionToIdle):
        @@ -572,7 +664,7 @@

        Maintenance Release

      • Fixed typos in UART State definition description.
      • Optimized stack usage for multiple APIs.
      • -
    • HAL/LL USART update +

    • HAL/LL USART update

      • Removed IS_USART_OVERSAMPLING() as it is unused.
      • LL_USART_ClockInit now supports clock phase and clock polarity configuration for SPI_Slave mode.
        • @@ -580,35 +672,35 @@

        Maintenance Release

      • Optimized stack usage for multiple APIs.
      • Removed useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro.
      • -
    • HAL SMBUS update +

    • HAL SMBUS update

      • Support for Fast Mode Plus to be SMBUS rev 3 compliant.
        • Added HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+.
      • -
    • LL SPI update +

    • LL SPI update

      • Updated to set the FRXTH bit for 8bit data for LL_SPI_Init() API.
      • -
    • HAL WWDG update +

    • HAL WWDG update

      • Updated HAL driver description.
      • -
    • HAL/LL USB update +

    • HAL/LL USB update

      • Fixed USB ISO IN double buffer mode Transfer.
      • Fixed PMA rx count descriptor

    • Added few instructions before reading the RX count register.

    -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.50.4 + ST-LINKV2
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31 + ST-LINKV2
    • STM32CubeIDE toolchain V1.6.0
    -

    Supported Devices

    +

    Supported Devices

    • STM32G431/41xx
    • STM32G471xx
      • @@ -621,17 +713,17 @@

      Supported Devices

      -

      Main Changes

      -

      Maintenance Release

      +

      Main Changes

      +

      Maintenance Release

        -
      • Add support for STM32G491xx and STM32G4A1 part numbers
        • +

      • Add support for STM32G491xx and STM32G4A1 part numbers

      • General updates to fix known defects and enhancements implementation

        • -
      • HAL/LL GPIO update +

      • HAL/LL GPIO update

        • Enhancement GPIO_TogglePin API to allow the toggling of many pins
        • Update GPIO initialization sequence to avoid unwanted pulse on GPIO Pin’s
        • -
      • HAL/LL HRTIM update +

      • HAL/LL HRTIM update

        • Constants renaming:
            @@ -645,7 +737,7 @@

            Maintenance Release

          • Remove unused LL constant LL_HRTIM_RESETTRIG_OTHER5_CMP4 as the definition it corresponds to (HRTIM_RSTR_TIMFCMP4) exists neither in the CMSIS nor in the reference manual.
        • -
      • HAL/LL I2S update +

      • HAL/LL I2S update

        • Update HAL_I2S_DMAStop() API to be more safe
            @@ -657,7 +749,7 @@

            Maintenance Release

          • Add new ErrorCode define: HAL_I2S_ERROR_BUSY_LINE_RX
        • -
      • HAL/LL SPI update +

      • HAL/LL SPI update

        • Update HAL_SPI_Init() API
            @@ -677,11 +769,11 @@

            Maintenance Release

          • Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled
        • -
      • HAL SAI update +

      • HAL SAI update

        • Update HAL_SAI_Init() API to correct the formula in case of SPDIF is wrong
        • -
      • HAL/LL ADC update +

      • HAL/LL ADC update

        • Update Channel & external trigger to support STM32G491/STM32G4A1 embedded with 3 ADC:
            @@ -690,23 +782,23 @@

            Maintenance Release

        • Update note in ll_adc.h & hal_adc.h to highlight that the ADC with transfers DMA and ADC mode auto delay can work simultaneously.
        • -
      • HAL COMP update +

      • HAL COMP update

        • Update Blanking sources to support STM32G491/STM32G4A1 embedded with 4 COMP:
          • IS_COMP_BLANKINGSRC_INSTANCE
        • -
      • HAL OPAMP update +

      • HAL OPAMP update

        • Update hal_opamp_ex.c to support STM32G491/STM32G4A1 embedded with 4 OPAMP (OPAMP1/OPAMP2/OPAMP3/OPAMP6):
        • -
      • HAL FLASH update +

      • HAL FLASH update

        • Update FLASH Latency comment param to list all supported flash latency values.
        • Update FLASH_PAGE_NB to return the right page number(256 pages for devices embedded with 512KB flash size and 64 for devices embedded with 128KB flash size)
        • -
      • HAL/LL RCC update +

      • HAL/LL RCC update

        • Update Table 1. HCLK clock frequency for STM32G4xx devices to be aligned with reference manual RM0440
        • Update peripheral clock to support STM32G491/STM32G4A1 devices: @@ -715,7 +807,7 @@

          Maintenance Release

        • IS_RCC_PERIPHCLOCK
      -
    • HAL/LL TIM driver +

    • HAL/LL TIM driver

      • Align HAL/LL TIM driver with latest updates and enhancements
      • Add new macros to enable and disable the fast mode when using the one pulse mode to output a waveform with a minimum delay @@ -731,7 +823,7 @@

        Maintenance Release

      • Add new API HAL_TIM_DMABurst_MultiWriteStart() allowing to configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
      • Add new API HAL_TIM_DMABurst_MultiReadStart() allowing to configure the DMA Burst to transfer Data from the TIM peripheral to the memory
      • -
    • HAL/LL UART driver +

    • HAL/LL UART driver

      • Update UART polling processes to handle efficiently the Lock mechanism
          @@ -740,11 +832,11 @@

          Maintenance Release

        • Update UART BRR calculation for ROM size gain
        • Remove ‘register’ storage class specifier from LL UART driver.
        • -
      • HAL/LL USART driver +

      • HAL/LL USART driver

        • Remove ‘register’ storage class specifier from LL USART driver.
        • -
      • HAL/LL USB driver +

      • HAL/LL USB driver

        • Fix USB Bulk transfer double buffer mode
        • Remove register keyword from USB defined macros as no more supported by c++ compiler
          • @@ -752,13 +844,13 @@

          Maintenance Release

        • Correct some word spelling issues
      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.40.1
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.29
      • STM32CubeIDE toolchain V1.4.0
      -

      Supported Devices

      +

      Supported Devices

      • STM32G431/41xx
      • STM32G471xx
        • @@ -771,11 +863,11 @@

        Supported Devices

        -

        Main Changes

        -

        Maintenance Release

        +

        Main Changes

        +

        Maintenance Release

        • General updates to fix known defects and enhancements implementation

          • -
        • HAL/LL CRYP update +

        • HAL/LL CRYP update

          • Correct MISRA C:2012 warnings reported by rules 2.2_c, 10.1_R6, 10.3, 10.4_a, 10.6, 12.1, 13.5 15.7
          • Perform a new check mechanism on the cryp buffer size in Encryption et Decryption API @@ -809,11 +901,11 @@

            Maintenance Release

          • Update CRYP_GCMCCM_SetPayloadPhase_IT() API
        -
      • HAL/LL FMAC update +

      • HAL/LL FMAC update

        • General updates to comply to internal coding rules.
        • -
      • HAL GPIO update +

      • HAL GPIO update

        • Update the GPIO initialization sequence in HAL_GPIO_Init() API to avoid unwanted glitches on GPIO pins.
        • Add missing GPIO Alternate Function definitions: @@ -821,7 +913,7 @@

          Maintenance Release

        • GPIO_AF2_TIM16, GPIO_AF9_TIM8, GPIO_AF11_TIM8, GPIO_AF12_TIM1.
      • -
    • HAL HRTIM update +

    • HAL HRTIM update

      • Update HAL_HRTIM_WaveformCompareConfig() to clear HRTIM_TIMxCR.DELCMP bitfield when the auto-delayed protection mode is disabled.
      • Correct some “HRTIM_OUTPUTSET_TIMxx†constant names which are not compliant with Timer Events Mapping specified in the reference manual @@ -836,7 +928,7 @@

        Maintenance Release

      • Remove UPDGAT bits reset from the HRTIM_TimingUnitWaveform_Control() API
      • Add a lock and unlock handle process in the HAL_HRTIM_SimpleOCChannelConfig() API
      • -
    • HAL I2C update +

    • HAL I2C update

      • Update I2C_DMAAbort() APIs to fix hardfault issue when hdmatx and hdmarx parameters in i2c handle aren’t initialized (NULL pointer).
          @@ -847,7 +939,7 @@

          Maintenance Release

        • Update I2C_Slave_ISR_IT() and I2C_Slave_ISR_DMA() APIs to check on STOP condition and handle it before clearing the ADDR flag
      • -
    • HAL LPTIM update +

    • HAL LPTIM update

      • Add a polling mechanism to check on LPTIM_FLAG_XXOK flags in different API
          @@ -866,16 +958,16 @@

          Maintenance Release

    • -
  • HAL/LL RTC update +

  • HAL/LL RTC update

    • Update API HAL_RTC_SetAlarm_IT() to allow changing alarm time “on the fly†simply by calling the API again.
    • Update API LL_RTC_BKP_SetRegister() and API LL_RTC_BKP_GetRegister() to comply to rules 2.2 and 13.2 of MISRAC-2012.
    • -
  • HAL SPI update +

  • HAL SPI update

    • Update the “Rx DMA transfer complete callbackâ€Â to disable the Tx DMA request only in case of full-duplex mode and not it in half-duplex mode.
    • -
  • HAL TIM update +

  • HAL TIM update

    • Update Encoder interface mode to keep TIM_CCER_CCxNP bits low
        @@ -937,7 +1029,7 @@

        Maintenance Release

      • Add a new element in the TIM_HandleTypeDef structure : ChannelNState to manage TIM complementary channel operation state
    • -
  • HAL/LL USART update +

  • HAL/LL USART update

    • Add support to the Receiver Timeout Interrupt in the HAL_USART_IRQHandler
    • Fix wrong value for SlaveMode field in USART handle after HAL_USARTEx_DisableSlaveMode() call @@ -945,23 +1037,23 @@

      Maintenance Release

    • Set USART_SLAVEMODE_DISABLE instead of USART_SLAVEMODE_ENABLE
    • -
  • HAL USB update +

  • HAL USB update

    • Improve USB endpoint out re-enabling with double-buffer mode.
    • -
  • LL UTILS update +

  • LL UTILS update

    • API UTILS_SetFlashLatency() renamed LL_SetFlashLatency() and set exportable.
    • API LL_PLL_ConfigSystemClock_HSI() and API LL_PLL_ConfigSystemClock_HSE() updated to set back the AHB prescaler to 1 after it has been temporarily set to 2 to avoid undershoot when configuring PLL at high frequencies.
    • -

    Development Toolchains and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • STM32CubeIDE toolchain v1.3.0
    -

    Supported Devices

    +

    Supported Devices

    • STM32G431/41xx
    • STM32G471xx
      • @@ -973,8 +1065,8 @@

      Supported Devices

      -

      Main Changes

      -

      Maintenance Release

      +

      Main Changes

      +

      Maintenance Release

      Maintenance release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.

      Contents

      @@ -1057,13 +1149,13 @@

      Contents

      -

      Development Toolchains and Compilers

      +

      Development Toolchains and Compilers

      • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
      • System Workbench STM32 (SW4STM32) toolchain V2.7.2
      -

      Supported Devices

      +

      Supported Devices

      • STM32G431/41xx
      • STM32G471xx
        • @@ -1075,16 +1167,16 @@

        Supported Devices

        -

        Main Changes

        +

        Main Changes

        First release

        First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32G431/41xx, STM32G471xx, STM32G473/83xx and STM32G474/84xx.

        -

        Development Toolchains and Compilers

        +

        Development Toolchains and Compilers

        • IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25
        • System Workbench STM32 (SW4STM32) toolchain V2.7.2
        -

        Supported Devices

        +

        Supported Devices

        • STM32G431/41xx
        • STM32G471xx
          • @@ -1093,7 +1185,7 @@

          Supported Devices

        -
      +