From 0dda106ede926e8d7919d1335e722023734396b4 Mon Sep 17 00:00:00 2001
From: alextrical <35117191+alextrical@users.noreply.github.com>
Date: Thu, 11 Aug 2022 10:23:56 +0100
Subject: [PATCH 1/5] Added F410T(8-B)Y board
---
README.md | 1 +
boards.txt | 16 ++
.../F410T(8-B)Y/STM32F410T8YX_ldscript.ld | 185 ++++++++++++++++++
.../STM32F4xx/F410T(8-B)Y/generic_clock.c | 41 +++-
4 files changed, 241 insertions(+), 2 deletions(-)
create mode 100644 variants/STM32F4xx/F410T(8-B)Y/STM32F410T8YX_ldscript.ld
diff --git a/README.md b/README.md
index f1e08f9540..69da74caf8 100644
--- a/README.md
+++ b/README.md
@@ -252,6 +252,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F407ZE
STM32F407ZG | Generic Board | **2.0.0** | |
| :green_heart: | STM32F410C8
STM32F410CB | Generic Board | *1.9.0* | |
| :green_heart: | STM32F410R8
STM32F410RB | Generic Board | *1.9.0* | |
+| :yellow_heart: | STM32F410T8
STM32F410TB | Generic Board | **2.3.0** | |
| :green_heart: | STM32F411CC
STM32F411CE | Generic Board | *1.9.0* | |
| :green_heart: | STM32F411RC
STM32F411RE | Generic Board | *1.9.0* | |
| :green_heart: | STM32F412CE
STM32F412CG | Generic Board | *1.9.0* | |
diff --git a/boards.txt b/boards.txt
index 0ab159124c..b2f58f0d7f 100644
--- a/boards.txt
+++ b/boards.txt
@@ -2559,6 +2559,22 @@ GenF4.menu.pnum.GENERIC_F410RBTX.build.board=GENERIC_F410RBTX
GenF4.menu.pnum.GENERIC_F410RBTX.build.product_line=STM32F410Rx
GenF4.menu.pnum.GENERIC_F410RBTX.build.variant=STM32F4xx/F410R(8-B)(I-T)
+# Generic F410T8Yx
+GenF4.menu.pnum.GENERIC_F410T8YX=Generic F410T8Yx
+GenF4.menu.pnum.GENERIC_F410T8YX.upload.maximum_size=65536
+GenF4.menu.pnum.GENERIC_F410T8YX.upload.maximum_data_size=32768
+GenF4.menu.pnum.GENERIC_F410T8YX.build.board=GENERIC_F410T8YX
+GenF4.menu.pnum.GENERIC_F410T8YX.build.product_line=STM32F410Tx
+GenF4.menu.pnum.GENERIC_F410T8YX.build.variant=STM32F4xx/F410T(8-B)Y
+
+# Generic F410TBYx
+GenF4.menu.pnum.GENERIC_F410TBYX=Generic F410TBYx
+GenF4.menu.pnum.GENERIC_F410TBYX.upload.maximum_size=131072
+GenF4.menu.pnum.GENERIC_F410TBYX.upload.maximum_data_size=32768
+GenF4.menu.pnum.GENERIC_F410TBYX.build.board=GENERIC_F410TBYX
+GenF4.menu.pnum.GENERIC_F410TBYX.build.product_line=STM32F410Tx
+GenF4.menu.pnum.GENERIC_F410TBYX.build.variant=STM32F4xx/F410T(8-B)Y
+
# Generic F411CCUx
GenF4.menu.pnum.GENERIC_F411CCUX=Generic F411CCUx
GenF4.menu.pnum.GENERIC_F411CCUX.upload.maximum_size=262144
diff --git a/variants/STM32F4xx/F410T(8-B)Y/STM32F410T8YX_ldscript.ld b/variants/STM32F4xx/F410T(8-B)Y/STM32F410T8YX_ldscript.ld
new file mode 100644
index 0000000000..c61e43420c
--- /dev/null
+++ b/variants/STM32F4xx/F410T(8-B)Y/STM32F410T8YX_ldscript.ld
@@ -0,0 +1,185 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32F410T8Yx Device from STM32F4 series
+** 64Kbytes FLASH
+** 32Kbytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2022 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+
+_Min_Heap_Size = 0x200 ; /* required amount of heap */
+_Min_Stack_Size = 0x400 ; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM xrw : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH rx : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM : {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array :
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c b/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c
index 6a45968543..54c55d9434 100644
--- a/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c
+++ b/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c
@@ -20,8 +20,45 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 8;
+ RCC_OscInitStruct.PLL.PLLN = 100;
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
+ {
+ Error_Handler();
+ }
}
#endif /* ARDUINO_GENERIC_* */
From 0dcf2dbcf1b9627b2d1d9c1386827f969f01f45e Mon Sep 17 00:00:00 2001
From: alextrical <35117191+alextrical@users.noreply.github.com>
Date: Thu, 11 Aug 2022 10:51:36 +0100
Subject: [PATCH 2/5] Update README.md
Co-authored-by: Frederic Pillon
---
README.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/README.md b/README.md
index 69da74caf8..8c1dd16a14 100644
--- a/README.md
+++ b/README.md
@@ -252,7 +252,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F407ZE
STM32F407ZG | Generic Board | **2.0.0** | |
| :green_heart: | STM32F410C8
STM32F410CB | Generic Board | *1.9.0* | |
| :green_heart: | STM32F410R8
STM32F410RB | Generic Board | *1.9.0* | |
-| :yellow_heart: | STM32F410T8
STM32F410TB | Generic Board | **2.3.0** | |
+| :yellow_heart: | STM32F410T8
STM32F410TB | Generic Board | **2.4.0** | |
| :green_heart: | STM32F411CC
STM32F411CE | Generic Board | *1.9.0* | |
| :green_heart: | STM32F411RC
STM32F411RE | Generic Board | *1.9.0* | |
| :green_heart: | STM32F412CE
STM32F412CG | Generic Board | *1.9.0* | |
From 06efa159f0e004299579364036e25cacebc7e084 Mon Sep 17 00:00:00 2001
From: alextrical <35117191+alextrical@users.noreply.github.com>
Date: Thu, 11 Aug 2022 10:53:26 +0100
Subject: [PATCH 3/5] Style corrections
---
variants/STM32F4xx/F410T(8-B)Y/generic_clock.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c b/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c
index 54c55d9434..027c62858c 100644
--- a/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c
+++ b/variants/STM32F4xx/F410T(8-B)Y/generic_clock.c
@@ -41,22 +41,20 @@ WEAK void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
- {
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
Error_Handler();
}
}
From 2adb54bf7250f3ff6316ce77820245ceb8634a9a Mon Sep 17 00:00:00 2001
From: alextrical <35117191+alextrical@users.noreply.github.com>
Date: Thu, 11 Aug 2022 13:57:51 +0100
Subject: [PATCH 4/5] Corrected ldscript.ld names
---
.../F410T(8-B)Y/{STM32F410T8YX_ldscript.ld => ldscript.ld} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename variants/STM32F4xx/F410T(8-B)Y/{STM32F410T8YX_ldscript.ld => ldscript.ld} (100%)
diff --git a/variants/STM32F4xx/F410T(8-B)Y/STM32F410T8YX_ldscript.ld b/variants/STM32F4xx/F410T(8-B)Y/ldscript.ld
similarity index 100%
rename from variants/STM32F4xx/F410T(8-B)Y/STM32F410T8YX_ldscript.ld
rename to variants/STM32F4xx/F410T(8-B)Y/ldscript.ld
From 710354e894004e6b3250b4068f22bc9c7a89136a Mon Sep 17 00:00:00 2001
From: alextrical <35117191+alextrical@users.noreply.github.com>
Date: Thu, 11 Aug 2022 17:22:34 +0100
Subject: [PATCH 5/5] Fixed issue caused by incorrect RegEx query, removing
parenthesis
---
variants/STM32F4xx/F410T(8-B)Y/ldscript.ld | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/variants/STM32F4xx/F410T(8-B)Y/ldscript.ld b/variants/STM32F4xx/F410T(8-B)Y/ldscript.ld
index c61e43420c..b87aa0331a 100644
--- a/variants/STM32F4xx/F410T(8-B)Y/ldscript.ld
+++ b/variants/STM32F4xx/F410T(8-B)Y/ldscript.ld
@@ -44,8 +44,8 @@ _Min_Stack_Size = 0x400 ; /* required amount of stack */
/* Memories definition */
MEMORY
{
- RAM xrw : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
- FLASH rx : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
}
/* Sections */