From 792cc6086835a6fadb03709aabb774a16081a3f3 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 8 Dec 2022 11:45:38 +0100 Subject: [PATCH 1/2] system(H7) update STM32H7xx HAL Drivers to v1.11.1 Included in STM32CubeH7 FW v1.11.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 200 +- .../STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h | 53 +- .../Inc/stm32h7xx_hal_adc.h | 25 +- .../Inc/stm32h7xx_hal_adc_ex.h | 4 +- .../Inc/stm32h7xx_hal_cec.h | 136 +- .../Inc/stm32h7xx_hal_conf_template.h | 4 +- .../Inc/stm32h7xx_hal_cordic.h | 16 +- .../Inc/stm32h7xx_hal_cryp.h | 40 +- .../Inc/stm32h7xx_hal_dcmi.h | 7 + .../Inc/stm32h7xx_hal_dfsdm.h | 24 +- .../Inc/stm32h7xx_hal_dfsdm_ex.h | 2 +- .../Inc/stm32h7xx_hal_dma.h | 8 + .../Inc/stm32h7xx_hal_dts.h | 59 +- .../Inc/stm32h7xx_hal_eth.h | 394 +-- .../Inc/stm32h7xx_hal_eth_ex.h | 26 +- .../Inc/stm32h7xx_hal_flash_ex.h | 13 +- .../Inc/stm32h7xx_hal_fmac.h | 111 +- .../Inc/stm32h7xx_hal_hcd.h | 10 +- .../Inc/stm32h7xx_hal_hrtim.h | 56 +- .../Inc/stm32h7xx_hal_i2c.h | 4 + .../Inc/stm32h7xx_hal_i2s.h | 27 +- .../Inc/stm32h7xx_hal_irda.h | 4 +- .../Inc/stm32h7xx_hal_lptim.h | 6 +- .../Inc/stm32h7xx_hal_mmc.h | 11 +- .../Inc/stm32h7xx_hal_opamp.h | 8 +- .../Inc/stm32h7xx_hal_pcd.h | 6 +- .../Inc/stm32h7xx_hal_pssi.h | 62 +- .../Inc/stm32h7xx_hal_ramecc.h | 19 +- .../Inc/stm32h7xx_hal_rcc.h | 21 +- .../Inc/stm32h7xx_hal_rcc_ex.h | 209 +- .../Inc/stm32h7xx_hal_rtc.h | 222 +- .../Inc/stm32h7xx_hal_rtc_ex.h | 481 +-- .../Inc/stm32h7xx_hal_sai.h | 4 +- .../Inc/stm32h7xx_hal_sai_ex.h | 3 +- .../Inc/stm32h7xx_hal_sd.h | 10 +- .../Inc/stm32h7xx_hal_smartcard.h | 4 +- .../Inc/stm32h7xx_hal_spi.h | 78 +- .../Inc/stm32h7xx_hal_spi_ex.h | 2 +- .../Inc/stm32h7xx_hal_tim.h | 59 +- .../Inc/stm32h7xx_hal_tim_ex.h | 226 +- .../Inc/stm32h7xx_hal_uart.h | 31 +- .../Inc/stm32h7xx_hal_uart_ex.h | 2 + .../Inc/stm32h7xx_hal_usart.h | 4 +- .../Inc/stm32h7xx_ll_adc.h | 173 +- .../Inc/stm32h7xx_ll_bdma.h | 18 +- .../Inc/stm32h7xx_ll_bus.h | 162 +- .../Inc/stm32h7xx_ll_comp.h | 6 + .../Inc/stm32h7xx_ll_cordic.h | 28 +- .../Inc/stm32h7xx_ll_cortex.h | 4 +- .../Inc/stm32h7xx_ll_delayblock.h | 9 +- .../Inc/stm32h7xx_ll_dma.h | 13 +- .../Inc/stm32h7xx_ll_fmac.h | 48 +- .../Inc/stm32h7xx_ll_hrtim.h | 274 +- .../Inc/stm32h7xx_ll_lptim.h | 92 +- .../Inc/stm32h7xx_ll_lpuart.h | 165 +- .../Inc/stm32h7xx_ll_rcc.h | 263 +- .../Inc/stm32h7xx_ll_rng.h | 15 + .../Inc/stm32h7xx_ll_rtc.h | 303 +- .../Inc/stm32h7xx_ll_sdmmc.h | 12 +- .../Inc/stm32h7xx_ll_spi.h | 36 +- .../Inc/stm32h7xx_ll_system.h | 4 +- .../Inc/stm32h7xx_ll_tim.h | 326 +- .../Inc/stm32h7xx_ll_usart.h | 241 +- .../Inc/stm32h7xx_ll_usb.h | 136 +- system/Drivers/STM32H7xx_HAL_Driver/README.md | 14 +- .../STM32H7xx_HAL_Driver/Release_Notes.html | 186 +- .../STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c | 22 +- .../Src/stm32h7xx_hal_cec.c | 57 +- .../Src/stm32h7xx_hal_cordic.c | 28 +- .../Src/stm32h7xx_hal_crc_ex.c | 79 +- .../Src/stm32h7xx_hal_cryp.c | 1296 +++---- .../Src/stm32h7xx_hal_cryp_ex.c | 16 +- .../Src/stm32h7xx_hal_dac.c | 28 +- .../Src/stm32h7xx_hal_dcmi.c | 16 +- .../Src/stm32h7xx_hal_dfsdm.c | 24 +- .../Src/stm32h7xx_hal_dfsdm_ex.c | 2 +- .../Src/stm32h7xx_hal_dma.c | 6 + .../Src/stm32h7xx_hal_dsi.c | 359 +- .../Src/stm32h7xx_hal_dts.c | 223 +- .../Src/stm32h7xx_hal_eth.c | 50 +- .../Src/stm32h7xx_hal_exti.c | 2 +- .../Src/stm32h7xx_hal_flash.c | 6 + .../Src/stm32h7xx_hal_fmac.c | 11 +- .../Src/stm32h7xx_hal_hash.c | 2 +- .../Src/stm32h7xx_hal_hcd.c | 435 +-- .../Src/stm32h7xx_hal_hrtim.c | 144 +- .../Src/stm32h7xx_hal_i2c.c | 749 +++-- .../Src/stm32h7xx_hal_i2s.c | 123 +- .../Src/stm32h7xx_hal_irda.c | 25 +- .../Src/stm32h7xx_hal_lptim.c | 18 +- .../Src/stm32h7xx_hal_ltdc.c | 6 + .../Src/stm32h7xx_hal_mdios.c | 21 +- .../Src/stm32h7xx_hal_mmc.c | 143 +- .../Src/stm32h7xx_hal_opamp.c | 85 +- .../Src/stm32h7xx_hal_pcd.c | 43 +- .../Src/stm32h7xx_hal_pcd_ex.c | 6 +- .../Src/stm32h7xx_hal_pssi.c | 209 +- .../Src/stm32h7xx_hal_ramecc.c | 15 +- .../Src/stm32h7xx_hal_rcc.c | 671 ++-- .../Src/stm32h7xx_hal_rcc_ex.c | 2996 +++++++++-------- .../Src/stm32h7xx_hal_rng.c | 11 +- .../Src/stm32h7xx_hal_rng_ex.c | 2 +- .../Src/stm32h7xx_hal_rtc.c | 337 +- .../Src/stm32h7xx_hal_rtc_ex.c | 435 +-- .../Src/stm32h7xx_hal_sai.c | 10 +- .../Src/stm32h7xx_hal_sai_ex.c | 3 +- .../Src/stm32h7xx_hal_sd.c | 227 +- .../Src/stm32h7xx_hal_sdram.c | 12 + .../Src/stm32h7xx_hal_smartcard.c | 21 +- .../Src/stm32h7xx_hal_smbus.c | 25 +- .../Src/stm32h7xx_hal_spi.c | 411 +-- .../Src/stm32h7xx_hal_spi_ex.c | 2 +- .../Src/stm32h7xx_hal_sram.c | 14 + .../Src/stm32h7xx_hal_tim.c | 105 +- .../Src/stm32h7xx_hal_tim_ex.c | 25 +- .../Src/stm32h7xx_hal_uart.c | 194 +- .../Src/stm32h7xx_hal_uart_ex.c | 42 +- .../Src/stm32h7xx_hal_usart.c | 22 +- .../Src/stm32h7xx_ll_adc.c | 25 + .../Src/stm32h7xx_ll_cordic.c | 2 +- .../Src/stm32h7xx_ll_delayblock.c | 6 + .../Src/stm32h7xx_ll_lptim.c | 5 +- .../Src/stm32h7xx_ll_lpuart.c | 9 +- .../Src/stm32h7xx_ll_rcc.c | 93 +- .../Src/stm32h7xx_ll_rtc.c | 21 +- .../Src/stm32h7xx_ll_spi.c | 5 +- .../Src/stm32h7xx_ll_tim.c | 70 +- .../Src/stm32h7xx_ll_usart.c | 22 +- .../Src/stm32h7xx_ll_usb.c | 202 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 130 files changed, 8461 insertions(+), 7034 deletions(-) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 844bb943af..73380827d7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,14 +37,16 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF #endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ /** * @} */ @@ -110,6 +112,7 @@ extern "C" { #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ + /** * @} */ @@ -211,6 +214,11 @@ extern "C" { #endif #endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + /** * @} */ @@ -231,7 +239,7 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32H5) || defined(STM32C0) +#if defined(STM32C0) #else #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ @@ -265,7 +273,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -277,11 +285,6 @@ extern "C" { #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif -#if defined(STM32H5) -#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 -#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 -#endif - #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID @@ -532,6 +535,9 @@ extern "C" { #define OB_USER_nBOOT0 OB_USER_NBOOT0 #define OB_nBOOT0_RESET OB_NBOOT0_RESET #define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ /** @@ -576,106 +582,6 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ -#if defined(STM32H5) -#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC -#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC -#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC -#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC -#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC -#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC - -#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC -#define SYSCFG_BREAK_PVD SBS_BREAK_PVD -#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC -#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP - -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 -#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 -#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 - -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE - -#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 -#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 -#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 -#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 - -#define SYSCFG_ETH_MII SBS_ETH_MII -#define SYSCFG_ETH_RMII SBS_ETH_RMII -#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG - -#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE -#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR -#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG - -#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG - -#define SYSCFG_MPU_NSEC SBS_MPU_NSEC -#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SYSCFG_SAU SBS_SAU -#define SYSCFG_MPU_SEC SBS_MPU_SEC -#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC -#define SYSCFG_LOCK_ALL SBS_LOCK_ALL -#else -#define SYSCFG_LOCK_ALL SBS_LOCK_ALL -#endif /* __ARM_FEATURE_CMSE */ - -#define SYSCFG_CLK SBS_CLK -#define SYSCFG_CLASSB SBS_CLASSB -#define SYSCFG_FPU SBS_FPU -#define SYSCFG_ALL SBS_ALL - -#define SYSCFG_SEC SBS_SEC -#define SYSCFG_NSEC SBS_NSEC - -#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE -#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE - -#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK -#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK -#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK - -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE - -#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS -#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS - -#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT -#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG -#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE -#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE -#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING -#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS -#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES -#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES -#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS - -#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig -#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig -#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig -#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF -#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster -#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect - -#define HAL_SYSCFG_Lock HAL_SBS_Lock -#define HAL_SYSCFG_GetLock HAL_SBS_GetLock - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes -#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes -#endif /* __ARM_FEATURE_CMSE */ - -#endif /* STM32H5 */ - - /** * @} */ @@ -774,6 +680,8 @@ extern "C" { #if defined(STM32U5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ /** * @} @@ -784,7 +692,9 @@ extern "C" { */ #if defined(STM32U5) #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB #endif /* STM32U5 */ + /** * @} */ @@ -1103,7 +1013,7 @@ extern "C" { #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif @@ -1187,8 +1097,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1199,15 +1109,22 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ /** * @} @@ -3050,6 +2967,11 @@ extern "C" { #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 #endif #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE @@ -3514,10 +3436,7 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32GK) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_DISABLE -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_DISABLE -#elif defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32V7) || defined(STM32N6) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3630,8 +3549,8 @@ extern "C" { #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 #if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE @@ -3647,15 +3566,20 @@ extern "C" { #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE -#endif +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ /** * @} @@ -3673,7 +3597,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32GK) || defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3726,10 +3652,6 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE -#if defined (STM32H5) -#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE -#endif /* STM32H5 */ - /** * @} */ @@ -3741,7 +3663,7 @@ extern "C" { #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1) +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE @@ -4078,6 +4000,16 @@ extern "C" { * @} */ +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h index 3a5e9948de..c3760b1735 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h @@ -8,7 +8,7 @@ * @attention * * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. + * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. @@ -52,7 +52,9 @@ typedef enum */ /* Exported constants --------------------------------------------------------*/ - +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ /** @defgroup REV_ID device revision ID * @{ */ @@ -65,6 +67,10 @@ typedef enum * @} */ +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale * @{ */ @@ -230,7 +236,9 @@ typedef enum * @} */ - +/** + * @} + */ /** @defgroup EXTI_Event_Input_Config Event Input Config @@ -696,9 +704,14 @@ typedef enum /** * @} */ - +/** + * @} + */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ #if defined(DUAL_CORE) /** @defgroup ART_Exported_Macros ART Exported Macros * @{ @@ -835,6 +848,10 @@ typedef enum * @} */ +/** @defgroup DBG_Exported_Macros DBG Exported Macros + * @{ + */ + /** @brief Freeze/Unfreeze Peripherals in Debug mode */ #define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1)) @@ -1002,6 +1019,12 @@ typedef enum #define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1)) #endif /*DUAL_CORE*/ +/** + * @} + */ +/** + * @} + */ /** @defgroup HAL_Private_Macros HAL Private Macros * @{ @@ -1026,15 +1049,27 @@ extern HAL_TickFreqTypeDef uwTickFreq; */ /* Exported functions --------------------------------------------------------*/ - +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ /* Initialization and de-initialization functions ******************************/ +/** @defgroup HAL_Group1 Initialization and de-initialization Functions + * @{ + */ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +/** + * @} + */ + /* Peripheral Control functions ************************************************/ +/** @defgroup HAL_Group2 HAL Control functions + * + */ void HAL_IncTick(void); void HAL_Delay(uint32_t Delay); uint32_t HAL_GetTick(void); @@ -1125,6 +1160,14 @@ void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0); void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ +/** + * @} + */ + +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h index 3a0451cf54..861324a382 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h @@ -256,8 +256,8 @@ typedef struct uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, - 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. + Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024). Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ @@ -755,14 +755,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration * @{ */ -#define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ -#define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_2SAMPLES ((ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_3SAMPLES ((ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_4SAMPLES ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_5SAMPLES ((ADC3_TR1_AWDFILT_2)) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_6SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_7SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1)) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ +#define ADC3_AWD_FILTERING_8SAMPLES ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */ /** * @} */ @@ -910,7 +910,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ - +#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC LDO output voltage ready bit */ /** * @} */ @@ -1372,7 +1372,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag + * @arg @ref ADC_FLAG_LDORDY ADC LDO output voltage ready bit. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h index 8c623933a8..1f7a2a35d3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h @@ -112,8 +112,8 @@ typedef struct uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number - between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. + Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used). + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024). Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h index 7547acb116..15e187ca2d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cec.h @@ -48,61 +48,70 @@ extern "C" { typedef struct { uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. - It can be one of @ref CEC_Signal_Free_Time + It can be one of CEC_Signal_Free_Time and belongs to the set {0,...,7} where 0x0 is the default configuration else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, - it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE - or CEC_EXTENDED_TOLERANCE */ + it can be a value of CEC_Tolerance : + it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ - uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. + uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising + Error stops the reception. CEC_NO_RX_STOP_ON_BRE: reception is not stopped. CEC_RX_STOP_ON_BRE: reception is stopped. */ - uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the + uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an + Error-Bit is generated on the CEC line upon Bit Rising Error detection. CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ - uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the + uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an + Error-Bit is generated on the CEC line upon Long Bit Period Error detection. CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ - uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line + uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an + Error-Bit generation on the CEC line upon an error detected on a broadcast message. - It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values: + It supersedes BREGEN and LBPEGEN bits for a broadcast message error + handling. It can take two values: 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. - a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE - and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. + a) BRE detection: error-bit generation on the CEC line if + BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. b) LBPE detection: error-bit generation on the CEC line if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. - no error-bit generation in case neither a) nor b) are satisfied. Additionally, - there is no error-bit generation in case of Short Bit Period Error detection in - a broadcast message while LSTN bit is set. */ + no error-bit generation in case neither a) nor b) are satisfied. + Additionally, there is no error-bit generation in case of Short Bit + Period Error detection in a broadcast message while LSTN bit is set. */ - uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts. + uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. - CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */ + CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end + of message transmission/reception. */ - uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values: + uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. + It can take two values: - CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its - own address (OAR). Messages addressed to different destination are ignored. + CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed + to its own address (OAR). Messages addressed to different destination + are ignored. Broadcast messages are always received. - CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own - address (OAR) with positive acknowledge. Messages addressed to different destination - are received, but without interfering with the CEC bus: no acknowledge sent. */ + CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its + own address (OAR) with positive acknowledge. Messages addressed to + different destination are received, but without interfering with the + CEC bus: no acknowledge sent. */ - uint16_t OwnAddress; /*!< Own addresses configuration - This parameter can be a value of @ref CEC_OWN_ADDRESS */ + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of CEC_OWN_ADDRESS */ uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ @@ -111,7 +120,8 @@ typedef struct /** * @brief HAL CEC State definition - * @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition). + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState + (see CEC_State_Definition). * - gState contains CEC state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -159,37 +169,37 @@ typedef struct __CEC_HandleTypeDef typedef struct #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ { - CEC_TypeDef *Instance; /*!< CEC registers base address */ + CEC_TypeDef *Instance; /*!< CEC registers base address */ - CEC_InitTypeDef Init; /*!< CEC communication parameters */ + CEC_InitTypeDef Init; /*!< CEC communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ - uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ + uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ + uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - HAL_LockTypeDef Lock; /*!< Locking object */ + HAL_LockTypeDef Lock; /*!< Locking object */ HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management and also related to Tx operations. - This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + This parameter can be a value of HAL_CEC_StateTypeDef */ HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. - This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + This parameter can be a value of HAL_CEC_StateTypeDef */ uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register - in case error is reported */ + in case error is reported */ #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) void (* TxCpltCallback)(struct __CEC_HandleTypeDef - *hcec); /*!< CEC Tx Transfer completed callback */ + *hcec); /*!< CEC Tx Transfer completed callback */ void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ - void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ + uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ + void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ - void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ - void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ + void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ + void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ } CEC_HandleTypeDef; @@ -202,7 +212,7 @@ typedef enum { HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ - HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ + HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ } HAL_CEC_CallbackIDTypeDef; @@ -212,7 +222,8 @@ typedef enum */ typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ + uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed + callback function */ #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ /** * @} @@ -358,16 +369,16 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_OWN_ADDRESS CEC Own Address * @{ */ -#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ -#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ -#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ -#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ -#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ -#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ -#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ -#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ -#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ -#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ +#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ +#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ +#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ +#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ +#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ +#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ +#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ +#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ +#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ #define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ #define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ #define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ @@ -421,8 +432,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags * @{ */ -#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ - CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) +#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ + CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) /** * @} */ @@ -430,7 +441,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag * @{ */ -#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) +#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) /** * @} */ @@ -438,7 +449,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag * @{ */ -#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) +#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) /** * @} */ @@ -622,7 +633,8 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) * @retval none */ -#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) +#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ + (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) /** * @} @@ -660,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); */ /* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size); -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); + const uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); @@ -675,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); * @{ */ /* Peripheral State functions ************************************************/ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); /** * @} */ @@ -731,8 +743,9 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) -#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ - ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) +#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ + (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ + ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) #define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) @@ -789,4 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #endif #endif /* STM32H7xxHAL_CEC_H */ - diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h index afca3b122d..90e89d1ab5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h @@ -218,8 +218,8 @@ #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ /* ########################### Ethernet Configuration ######################### */ -#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */ -#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */ +#define ETH_TX_DESC_CNT 4U /* number of Ethernet Tx DMA descriptors */ +#define ETH_RX_DESC_CNT 4U /* number of Ethernet Rx DMA descriptors */ #define ETH_MAC_ADDR0 (0x02UL) #define ETH_MAC_ADDR1 (0x00UL) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h index 7f8d5d9d41..0aa08c4316 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cordic.h @@ -64,7 +64,7 @@ typedef struct { CORDIC_TypeDef *Instance; /*!< Register base address */ - int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ + const int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */ int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */ @@ -546,14 +546,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig); +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc); -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection); /** * @} @@ -582,8 +582,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); * @{ */ /* Peripheral State functions *************************************************/ -HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic); -uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic); +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h index 769254776c..a6802ed6ba 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h @@ -47,8 +47,8 @@ extern "C" { typedef struct { - uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. - This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t DataType; /*!< no swap(32-bit data), halfword swap(16-bit data), byte swap(8-bit data) + or bit swap(1-bit data).this parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. This parameter can be a value of @ref CRYP_Key_Size */ uint32_t *pKey; /*!< The key used for encryption/decryption */ @@ -60,9 +60,9 @@ typedef struct uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ - uint32_t HeaderSize; /*!< The size of header buffer */ - uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ - uint32_t DataWidthUnit; /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t HeaderSize; /*!< The size of header buffer */ + uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ + uint32_t DataWidthUnit; /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to configure Key and Initialization Vector only once and to skip configuration for consecutive processing. @@ -210,7 +210,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point */ #define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ -#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */ +#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< Size unit is byte, but all input will be loaded in HW CRYPT IP by block of 4 words */ /** * @} @@ -221,7 +221,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point */ #define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ -#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< Size unit is byte, but all input will be loaded in HW CRYPT IP by block of 4 words */ /** * @} @@ -261,10 +261,10 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @{ */ -#define CRYP_DATATYPE_32B 0x00000000U -#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0 -#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1 -#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE +#define CRYP_NO_SWAP 0x00000000U +#define CRYP_HALFWORD_SWAP CRYP_CR_DATATYPE_0 +#define CRYP_BYTE_SWAP CRYP_CR_DATATYPE_1 +#define CRYP_BIT_SWAP CRYP_CR_DATATYPE /** * @} @@ -358,8 +358,11 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point */ #define CRYP_FLAG_MASK 0x0000001FU -#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ - ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) +#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)\ + ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) &\ + ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ + ((((__HANDLE__)->Instance->RISR) &\ + ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) /** @brief Check whether the specified CRYP interrupt is set or not. * @param __HANDLE__: specifies the CRYP handle. @@ -370,7 +373,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @retval The state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Enable the CRYP interrupt. @@ -487,10 +491,10 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((KEYSIZE) == CRYP_KEYSIZE_192B) || \ ((KEYSIZE) == CRYP_KEYSIZE_256B)) -#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \ - ((DATATYPE) == CRYP_DATATYPE_16B) || \ - ((DATATYPE) == CRYP_DATATYPE_8B) || \ - ((DATATYPE) == CRYP_DATATYPE_1B)) +#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_NO_SWAP) || \ + ((DATATYPE) == CRYP_HALFWORD_SWAP) || \ + ((DATATYPE) == CRYP_BYTE_SWAP) || \ + ((DATATYPE) == CRYP_BIT_SWAP)) #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h index e844fbba85..a21afc09d5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h @@ -580,6 +580,13 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup DCMI_Private_Defines DCMI Private Defines + * @{ + */ +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Constants DCMI Private Constants diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h index 73b226b89d..b4fd219a0f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h @@ -599,11 +599,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); @@ -615,7 +615,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); * @{ */ /* Channel state function *****************************************************/ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /** * @} */ @@ -676,16 +676,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef *awdParam); + const DFSDM_Filter_AwdParamTypeDef *awdParam); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); @@ -706,8 +706,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); * @{ */ /* Filter state functions *****************************************************/ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h index 6252debaa2..8a872602c4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h @@ -51,7 +51,7 @@ extern "C" { */ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue); -HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue); +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h index 1c299d58b0..82f6f215e5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h @@ -1228,6 +1228,14 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @} */ +/* Private types -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Types DMA Private Types + * @{ + */ +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros * @brief DMA private macros diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h index f30de77426..f9bff1703e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h @@ -24,14 +24,15 @@ extern "C" { #endif -#if defined(DTS) + /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" + /** @addtogroup STM32H7xx_HAL_Driver * @{ */ - +#if defined(DTS) /** @addtogroup DTS * @{ */ @@ -95,15 +96,37 @@ typedef struct #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp Init Callback */ void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts); /*!< DTS Base Msp DeInit Callback */ - void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */ - void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */ - void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */ - void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */ - void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */ - void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */ + void (* EndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< End measure Callback */ + void (* LowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< low threshold Callback */ + void (* HighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< high threshold Callback */ + void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous end of measure Callback */ + void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous low threshold Callback */ + void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts); /*!< Asynchronous high threshold Callback */ #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ } DTS_HandleTypeDef; +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) +/** + * @brief DTS callback ID enumeration definition + */ +typedef enum +{ + HAL_DTS_MEAS_COMPLETE_CB_ID = 0x00U, /*!< Measure complete callback ID */ + HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID = 0x01U, /*!< Asynchronous measure complete callback ID */ + HAL_DTS_LOW_THRESHOLD_CB_ID = 0x02U, /*!< Low threshold detection callback ID */ + HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID = 0x03U, /*!< Asynchronous low threshold detection callback ID */ + HAL_DTS_HIGH_THRESHOLD_CB_ID = 0x04U, /*!< High threshold detection callback ID */ + HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U, /*!< Asynchronous high threshold detection callback ID */ + HAL_DTS_MSPINIT_CB_ID = 0x06U, /*!< MSP init callback ID */ + HAL_DTS_MSPDEINIT_CB_ID = 0x07U /*!< MSP de-init callback ID */ +} HAL_DTS_CallbackIDTypeDef; + +/** + * @brief DTS callback pointers definition + */ +typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + /** * @} */ @@ -212,7 +235,15 @@ typedef struct * @param __HANDLE__ DTS handle. * @retval None */ +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) +#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DTS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else /* USE_HAL_DTS_REGISTER_CALLBACKS */ #define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DTS_STATE_RESET) +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ /** * @brief Enable the specified DTS sensor @@ -371,6 +402,13 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts); HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts); void HAL_DTS_MspInit(DTS_HandleTypeDef *hdts); void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts); +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID, + pDTS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ /** * @} */ @@ -396,6 +434,9 @@ void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts); /** * @} */ +/** + * @} + */ /* Private types -------------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -435,7 +476,7 @@ void HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts); #define IS_DTS_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= 0xFFFFUL) -#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL))) +#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL) #define IS_DTS_SAMPLINGTIME(__CYCLE__) (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE) || \ ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE) || \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h index e73cd9c176..5e4f1804c7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h @@ -48,15 +48,15 @@ extern "C" { #endif /* ETH_RX_DESC_CNT */ #ifndef ETH_SWRESET_TIMEOUT -#define ETH_SWRESET_TIMEOUT ((uint32_t)500U) +#define ETH_SWRESET_TIMEOUT 500U #endif /* ETH_SWRESET_TIMEOUT */ #ifndef ETH_MDIO_BUS_TIMEOUT -#define ETH_MDIO_BUS_TIMEOUT ((uint32_t)1000U) +#define ETH_MDIO_BUS_TIMEOUT 1000U #endif /* ETH_MDIO_BUS_TIMEOUT */ #ifndef ETH_MAC_US_TICK -#define ETH_MAC_US_TICK ((uint32_t)1000000U) +#define ETH_MAC_US_TICK 1000000U #endif /* ETH_MAC_US_TICK */ /*********************** Descriptors struct def section ************************/ @@ -178,6 +178,7 @@ typedef struct * */ +#ifdef HAL_ETH_USE_PTP /** * @brief ETH Timeupdate structure definition */ @@ -189,6 +190,7 @@ typedef struct /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief DMA Receive Descriptors Wrapper structure definition @@ -400,6 +402,7 @@ typedef enum * */ +#ifdef HAL_ETH_USE_PTP /** * @brief HAL ETH PTP Update type enum definition */ @@ -411,6 +414,7 @@ typedef enum /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief ETH Init Structure definition @@ -436,6 +440,7 @@ typedef struct * */ +#ifdef HAL_ETH_USE_PTP /** * @brief ETH PTP Init Structure definition */ @@ -466,6 +471,7 @@ typedef struct /** * */ +#endif /* HAL_ETH_USE_PTP */ /** * @brief HAL State structures definition @@ -689,58 +695,58 @@ typedef struct /** * @brief Bit definition of TDES0 RF register */ -#define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */ +#define ETH_DMATXNDESCRF_B1AP 0xFFFFFFFFU /*!< Transmit Packet Timestamp Low */ /** * @brief Bit definition of TDES1 RF register */ -#define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */ +#define ETH_DMATXNDESCRF_B2AP 0xFFFFFFFFU /*!< Transmit Packet Timestamp High */ /** * @brief Bit definition of TDES2 RF register */ -#define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */ -#define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */ -#define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */ -#define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */ -#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */ -#define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */ -#define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */ -#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */ -#define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */ -#define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */ +#define ETH_DMATXNDESCRF_IOC 0x80000000U /*!< Interrupt on Completion */ +#define ETH_DMATXNDESCRF_TTSE 0x40000000U /*!< Transmit Timestamp Enable */ +#define ETH_DMATXNDESCRF_B2L 0x3FFF0000U /*!< Buffer 2 Length */ +#define ETH_DMATXNDESCRF_VTIR 0x0000C000U /*!< VLAN Tag Insertion or Replacement mask */ +#define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U /*!< Do not add a VLAN tag. */ +#define ETH_DMATXNDESCRF_VTIR_REMOVE 0x00004000U /*!< Remove the VLAN tag from the packets before transmission. */ +#define ETH_DMATXNDESCRF_VTIR_INSERT 0x00008000U /*!< Insert a VLAN tag. */ +#define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U /*!< Replace the VLAN tag. */ +#define ETH_DMATXNDESCRF_B1L 0x00003FFFU /*!< Buffer 1 Length */ +#define ETH_DMATXNDESCRF_HL 0x000003FFU /*!< Header Length */ /** * @brief Bit definition of TDES3 RF register */ -#define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ -#define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ -#define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ -#define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */ -#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */ -#define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */ -#define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */ -#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */ -#define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/ -#define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */ -#define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */ -#define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */ -#define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */ -#define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */ -#define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */ -#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */ -#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are - enabled, but pseudo header - checksum is not - calculated in hardware */ -#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are - enabled, and pseudo header - checksum is - calculated in hardware. */ -#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */ -#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */ +#define ETH_DMATXNDESCRF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXNDESCRF_CTXT 0x40000000U /*!< Context Type */ +#define ETH_DMATXNDESCRF_FD 0x20000000U /*!< First Descriptor */ +#define ETH_DMATXNDESCRF_LD 0x10000000U /*!< Last Descriptor */ +#define ETH_DMATXNDESCRF_CPC 0x0C000000U /*!< CRC Pad Control mask */ +#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 0x00000000U /*!< CRC Pad Control: CRC and Pad Insertion */ +#define ETH_DMATXNDESCRF_CPC_CRC_INSERT 0x04000000U /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */ +#define ETH_DMATXNDESCRF_CPC_DISABLE 0x08000000U /*!< CRC Pad Control: Disable CRC Insertion */ +#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE 0x0C000000U /*!< CRC Pad Control: CRC Replacement */ +#define ETH_DMATXNDESCRF_SAIC 0x03800000U /*!< SA Insertion Control mask*/ +#define ETH_DMATXNDESCRF_SAIC_DISABLE 0x00000000U /*!< SA Insertion Control: Do not include the source address */ +#define ETH_DMATXNDESCRF_SAIC_INSERT 0x00800000U /*!< SA Insertion Control: Include or insert the source address */ +#define ETH_DMATXNDESCRF_SAIC_REPLACE 0x01000000U /*!< SA Insertion Control: Replace the source address */ +#define ETH_DMATXNDESCRF_THL 0x00780000U /*!< TCP Header Length */ +#define ETH_DMATXNDESCRF_TSE 0x00040000U /*!< TCP segmentation enable */ +#define ETH_DMATXNDESCRF_CIC 0x00030000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXNDESCRF_CIC_DISABLE 0x00000000U /*!< Do Nothing: Checksum Engine is disabled */ +#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 0x00010000U /*!< Only IP header checksum calculation and insertion are enabled. */ +#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 0x00020000U /*!< IP header checksum and payload checksum calculation and insertion are + enabled, but pseudo header + checksum is not + calculated in hardware */ +#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 0x00030000U /*!< IP Header checksum and payload checksum calculation and insertion are + enabled, and pseudo header + checksum is + calculated in hardware. */ +#define ETH_DMATXNDESCRF_TPL 0x0003FFFFU /*!< TCP Payload Length */ +#define ETH_DMATXNDESCRF_FL 0x00007FFFU /*!< Transmit End of Ring */ /* DMA Tx Normal Descriptor Write Back Format @@ -758,36 +764,36 @@ typedef struct /** * @brief Bit definition of TDES0 WBF register */ -#define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */ +#define ETH_DMATXNDESCWBF_TTSL 0xFFFFFFFFU /*!< Buffer1 Address Pointer or TSO Header Address Pointer */ /** * @brief Bit definition of TDES1 WBF register */ -#define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ +#define ETH_DMATXNDESCWBF_TTSH 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ /** * @brief Bit definition of TDES3 WBF register */ -#define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ -#define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ -#define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ -#define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */ -#define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ -#define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */ -#define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */ -#define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ -#define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */ -#define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ -#define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */ -#define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */ -#define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */ -#define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */ +#define ETH_DMATXNDESCWBF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXNDESCWBF_CTXT 0x40000000U /*!< Context Type */ +#define ETH_DMATXNDESCWBF_FD 0x20000000U /*!< First Descriptor */ +#define ETH_DMATXNDESCWBF_LD 0x10000000U /*!< Last Descriptor */ +#define ETH_DMATXNDESCWBF_TTSS 0x00020000U /*!< Tx Timestamp Status */ +#define ETH_DMATXNDESCWBF_DP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXNDESCWBF_TTSE 0x02000000U /*!< Transmit Timestamp Enable */ +#define ETH_DMATXNDESCWBF_ES 0x00008000U /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */ +#define ETH_DMATXNDESCWBF_JT 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXNDESCWBF_FF 0x00002000U /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */ +#define ETH_DMATXNDESCWBF_PCE 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXNDESCWBF_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXNDESCWBF_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXNDESCWBF_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXNDESCWBF_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXNDESCWBF_CC 0x000000F0U /*!< Collision Count */ +#define ETH_DMATXNDESCWBF_ED 0x00000008U /*!< Excessive Deferral */ +#define ETH_DMATXNDESCWBF_UF 0x00000004U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXNDESCWBF_DB 0x00000002U /*!< Deferred Bit */ +#define ETH_DMATXNDESCWBF_IHE 0x00000004U /*!< IP Header Error */ /* @@ -806,35 +812,35 @@ typedef struct /** * @brief Bit definition of Tx context descriptor register 0 */ -#define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */ +#define ETH_DMATXCDESC_TTSL 0xFFFFFFFFU /*!< Transmit Packet Timestamp Low */ /** * @brief Bit definition of Tx context descriptor register 1 */ -#define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */ +#define ETH_DMATXCDESC_TTSH 0xFFFFFFFFU /*!< Transmit Packet Timestamp High */ /** * @brief Bit definition of Tx context descriptor register 2 */ -#define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */ -#define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */ +#define ETH_DMATXCDESC_IVT 0xFFFF0000U /*!< Inner VLAN Tag */ +#define ETH_DMATXCDESC_MSS 0x00003FFFU /*!< Maximum Segment Size */ /** * @brief Bit definition of Tx context descriptor register 3 */ -#define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ -#define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */ -#define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */ -#define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */ -#define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */ -#define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */ -#define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */ -#define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */ -#define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */ -#define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */ -#define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */ -#define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */ +#define ETH_DMATXCDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXCDESC_CTXT 0x40000000U /*!< Context Type */ +#define ETH_DMATXCDESC_OSTC 0x08000000U /*!< One-Step Timestamp Correction Enable */ +#define ETH_DMATXCDESC_TCMSSV 0x04000000U /*!< One-Step Timestamp Correction Input or MSS Valid */ +#define ETH_DMATXCDESC_CDE 0x00800000U /*!< Context Descriptor Error */ +#define ETH_DMATXCDESC_IVTIR 0x000C0000U /*!< Inner VLAN Tag Insert or Replace Mask */ +#define ETH_DMATXCDESC_IVTIR_DISABLE 0x00000000U /*!< Do not add the inner VLAN tag. */ +#define ETH_DMATXCDESC_IVTIR_REMOVE 0x00040000U /*!< Remove the inner VLAN tag from the packets before transmission. */ +#define ETH_DMATXCDESC_IVTIR_INSERT 0x00080000U /*!< Insert the inner VLAN tag. */ +#define ETH_DMATXCDESC_IVTIR_REPLACE 0x000C0000U /*!< Replace the inner VLAN tag. */ +#define ETH_DMATXCDESC_IVLTV 0x00020000U /*!< Inner VLAN Tag Valid */ +#define ETH_DMATXCDESC_VLTV 0x00010000U /*!< VLAN Tag Valid */ +#define ETH_DMATXCDESC_VT 0x0000FFFFU /*!< VLAN Tag */ /** * @} @@ -861,20 +867,20 @@ typedef struct /** * @brief Bit definition of Rx normal descriptor register 0 read format */ -#define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */ +#define ETH_DMARXNDESCRF_BUF1AP 0xFFFFFFFFU /*!< Header or Buffer 1 Address Pointer */ /** * @brief Bit definition of Rx normal descriptor register 2 read format */ -#define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */ +#define ETH_DMARXNDESCRF_BUF2AP 0xFFFFFFFFU /*!< Buffer 2 Address Pointer */ /** * @brief Bit definition of Rx normal descriptor register 3 read format */ -#define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */ -#define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */ -#define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */ +#define ETH_DMARXNDESCRF_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXNDESCRF_IOC 0x40000000U /*!< Interrupt Enabled on Completion */ +#define ETH_DMARXNDESCRF_BUF2V 0x02000000U /*!< Buffer 2 Address Valid */ +#define ETH_DMARXNDESCRF_BUF1V 0x01000000U /*!< Buffer 1 Address Valid */ /* DMA Rx Normal Descriptor write back format @@ -892,80 +898,80 @@ typedef struct /** * @brief Bit definition of Rx normal descriptor register 0 write back format */ -#define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */ -#define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */ +#define ETH_DMARXNDESCWBF_IVT 0xFFFF0000U /*!< Inner VLAN Tag */ +#define ETH_DMARXNDESCWBF_OVT 0x0000FFFFU /*!< Outer VLAN Tag */ /** * @brief Bit definition of Rx normal descriptor register 1 write back format */ -#define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */ -#define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */ -#define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */ -#define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */ -#define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */ -#define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */ -#define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */ -#define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */ -#define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */ -#define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */ -#define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */ -#define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */ -#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */ -#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */ -#define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */ -#define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */ -#define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */ -#define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */ -#define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */ -#define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */ -#define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */ -#define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */ -#define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */ -#define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */ -#define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */ -#define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */ -#define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */ +#define ETH_DMARXNDESCWBF_OPC 0xFFFF0000U /*!< OAM Sub-Type Code, or MAC Control Packet opcode */ +#define ETH_DMARXNDESCWBF_TD 0x00008000U /*!< Timestamp Dropped */ +#define ETH_DMARXNDESCWBF_TSA 0x00004000U /*!< Timestamp Available */ +#define ETH_DMARXNDESCWBF_PV 0x00002000U /*!< PTP Version */ +#define ETH_DMARXNDESCWBF_PFT 0x00001000U /*!< PTP Packet Type */ +#define ETH_DMARXNDESCWBF_PMT_NO 0x00000000U /*!< PTP Message Type: No PTP message received */ +#define ETH_DMARXNDESCWBF_PMT_SYNC 0x00000100U /*!< PTP Message Type: SYNC (all clock types) */ +#define ETH_DMARXNDESCWBF_PMT_FUP 0x00000200U /*!< PTP Message Type: Follow_Up (all clock types) */ +#define ETH_DMARXNDESCWBF_PMT_DREQ 0x00000300U /*!< PTP Message Type: Delay_Req (all clock types) */ +#define ETH_DMARXNDESCWBF_PMT_DRESP 0x00000400U /*!< PTP Message Type: Delay_Resp (all clock types) */ +#define ETH_DMARXNDESCWBF_PMT_PDREQ 0x00000500U /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */ +#define ETH_DMARXNDESCWBF_PMT_PDRESP 0x00000600U /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */ +#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP 0x00000700U /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */ +#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE 0x00000800U /*!< PTP Message Type: Announce */ +#define ETH_DMARXNDESCWBF_PMT_MANAG 0x00000900U /*!< PTP Message Type: Management */ +#define ETH_DMARXNDESCWBF_PMT_SIGN 0x00000A00U /*!< PTP Message Type: Signaling */ +#define ETH_DMARXNDESCWBF_PMT_RESERVED 0x00000F00U /*!< PTP Message Type: PTP packet with Reserved message type */ +#define ETH_DMARXNDESCWBF_IPCE 0x00000080U /*!< IP Payload Error */ +#define ETH_DMARXNDESCWBF_IPCB 0x00000040U /*!< IP Checksum Bypassed */ +#define ETH_DMARXNDESCWBF_IPV6 0x00000020U /*!< IPv6 header Present */ +#define ETH_DMARXNDESCWBF_IPV4 0x00000010U /*!< IPv4 header Present */ +#define ETH_DMARXNDESCWBF_IPHE 0x00000008U /*!< IP Header Error */ +#define ETH_DMARXNDESCWBF_PT 0x00000003U /*!< Payload Type mask */ +#define ETH_DMARXNDESCWBF_PT_UNKNOWN 0x00000000U /*!< Payload Type: Unknown type or IP/AV payload not processed */ +#define ETH_DMARXNDESCWBF_PT_UDP 0x00000001U /*!< Payload Type: UDP */ +#define ETH_DMARXNDESCWBF_PT_TCP 0x00000002U /*!< Payload Type: TCP */ +#define ETH_DMARXNDESCWBF_PT_ICMP 0x00000003U /*!< Payload Type: ICMP */ /** * @brief Bit definition of Rx normal descriptor register 2 write back format */ -#define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */ -#define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */ -#define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */ -#define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */ -#define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */ -#define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */ -#define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */ -#define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */ -#define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */ +#define ETH_DMARXNDESCWBF_L3L4FM 0x20000000U /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */ +#define ETH_DMARXNDESCWBF_L4FM 0x10000000U /*!< Layer 4 Filter Match */ +#define ETH_DMARXNDESCWBF_L3FM 0x08000000U /*!< Layer 3 Filter Match */ +#define ETH_DMARXNDESCWBF_MADRM 0x07F80000U /*!< MAC Address Match or Hash Value */ +#define ETH_DMARXNDESCWBF_HF 0x00040000U /*!< Hash Filter Status */ +#define ETH_DMARXNDESCWBF_DAF 0x00020000U /*!< Destination Address Filter Fail */ +#define ETH_DMARXNDESCWBF_SAF 0x00010000U /*!< SA Address Filter Fail */ +#define ETH_DMARXNDESCWBF_VF 0x00008000U /*!< VLAN Filter Status */ +#define ETH_DMARXNDESCWBF_ARPNR 0x00000400U /*!< ARP Reply Not Generated */ /** * @brief Bit definition of Rx normal descriptor register 3 write back format */ -#define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */ -#define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */ -#define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ -#define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ -#define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */ -#define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */ -#define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */ -#define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */ -#define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */ -#define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */ -#define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */ -#define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */ -#define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */ -#define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */ -#define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */ -#define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */ -#define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */ -#define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */ -#define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */ -#define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */ -#define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */ -#define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */ -#define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */ +#define ETH_DMARXNDESCWBF_OWN 0x80000000U /*!< Own Bit */ +#define ETH_DMARXNDESCWBF_CTXT 0x40000000U /*!< Receive Context Descriptor */ +#define ETH_DMARXNDESCWBF_FD 0x20000000U /*!< First Descriptor */ +#define ETH_DMARXNDESCWBF_LD 0x10000000U /*!< Last Descriptor */ +#define ETH_DMARXNDESCWBF_RS2V 0x08000000U /*!< Receive Status RDES2 Valid */ +#define ETH_DMARXNDESCWBF_RS1V 0x04000000U /*!< Receive Status RDES1 Valid */ +#define ETH_DMARXNDESCWBF_RS0V 0x02000000U /*!< Receive Status RDES0 Valid */ +#define ETH_DMARXNDESCWBF_CE 0x01000000U /*!< CRC Error */ +#define ETH_DMARXNDESCWBF_GP 0x00800000U /*!< Giant Packet */ +#define ETH_DMARXNDESCWBF_RWT 0x00400000U /*!< Receive Watchdog Timeout */ +#define ETH_DMARXNDESCWBF_OE 0x00200000U /*!< Overflow Error */ +#define ETH_DMARXNDESCWBF_RE 0x00100000U /*!< Receive Error */ +#define ETH_DMARXNDESCWBF_DE 0x00080000U /*!< Dribble Bit Error */ +#define ETH_DMARXNDESCWBF_LT 0x00070000U /*!< Length/Type Field */ +#define ETH_DMARXNDESCWBF_LT_LP 0x00000000U /*!< The packet is a length packet */ +#define ETH_DMARXNDESCWBF_LT_TP 0x00010000U /*!< The packet is a type packet */ +#define ETH_DMARXNDESCWBF_LT_ARP 0x00030000U /*!< The packet is a ARP Request packet type */ +#define ETH_DMARXNDESCWBF_LT_VLAN 0x00040000U /*!< The packet is a type packet with VLAN Tag */ +#define ETH_DMARXNDESCWBF_LT_DVLAN 0x00050000U /*!< The packet is a type packet with Double VLAN Tag */ +#define ETH_DMARXNDESCWBF_LT_MAC 0x00060000U /*!< The packet is a MAC Control packet type */ +#define ETH_DMARXNDESCWBF_LT_OAM 0x00070000U /*!< The packet is a OAM packet type */ +#define ETH_DMARXNDESCWBF_ES 0x00008000U /*!< Error Summary */ +#define ETH_DMARXNDESCWBF_PL 0x00007FFFU /*!< Packet Length */ /* DMA Rx context Descriptor @@ -983,18 +989,18 @@ typedef struct /** * @brief Bit definition of Rx context descriptor register 0 */ -#define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */ +#define ETH_DMARXCDESC_RTSL 0xFFFFFFFFU /*!< Receive Packet Timestamp Low */ /** * @brief Bit definition of Rx context descriptor register 1 */ -#define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */ +#define ETH_DMARXCDESC_RTSH 0xFFFFFFFFU /*!< Receive Packet Timestamp High */ /** * @brief Bit definition of Rx context descriptor register 3 */ -#define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */ -#define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */ +#define ETH_DMARXCDESC_OWN 0x80000000U /*!< Own Bit */ +#define ETH_DMARXCDESC_CTXT 0x40000000U /*!< Receive Context Descriptor */ /** * @} @@ -1003,13 +1009,13 @@ typedef struct /** @defgroup ETH_Frame_settings ETH frame settings * @{ */ -#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ -#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ +#define ETH_MAX_PACKET_SIZE 1528U /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ /** * @} */ @@ -1017,14 +1023,14 @@ typedef struct /** @defgroup ETH_Error_Code ETH Error Code * @{ */ -#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */ -#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */ -#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ -#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ -#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */ +#define HAL_ETH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_ETH_ERROR_PARAM 0x00000001U /*!< Busy error */ +#define HAL_ETH_ERROR_BUSY 0x00000002U /*!< Parameter error */ +#define HAL_ETH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ +#define HAL_ETH_ERROR_DMA 0x00000008U /*!< DMA transfer error */ +#define HAL_ETH_ERROR_MAC 0x00000010U /*!< MAC transfer error */ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_ETH_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ /** * @} @@ -1033,12 +1039,12 @@ typedef struct /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes * @{ */ -#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U) -#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U) -#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U) -#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U) -#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U) -#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U) +#define ETH_TX_PACKETS_FEATURES_CSUM 0x00000001U +#define ETH_TX_PACKETS_FEATURES_SAIC 0x00000002U +#define ETH_TX_PACKETS_FEATURES_VLANTAG 0x00000004U +#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG 0x00000008U +#define ETH_TX_PACKETS_FEATURES_TSO 0x00000010U +#define ETH_TX_PACKETS_FEATURES_CRCPAD 0x00000020U /** * @} */ @@ -1172,7 +1178,7 @@ typedef struct * @{ */ #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA -#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U) +#define ETH_DMAARBITRATION_RX1_TX1 0x00000000U #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 @@ -1181,7 +1187,7 @@ typedef struct #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) -#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U) +#define ETH_DMAARBITRATION_TX1_RX1 0x00000000U #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) @@ -1198,7 +1204,7 @@ typedef struct */ #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB -#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U) +#define ETH_BURSTLENGTH_UNSPECIFIED 0x00000000U /** * @} */ @@ -1252,12 +1258,12 @@ typedef struct /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags * @{ */ -#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U) +#define ETH_DMA_RX_NO_ERROR_FLAG 0x00000000U #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0) #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1) #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0) #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 -#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U) +#define ETH_DMA_TX_NO_ERROR_FLAG 0x00000000U #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0) #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1) #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0) @@ -1354,7 +1360,7 @@ typedef struct /** @defgroup ETH_Speed ETH Speed * @{ */ -#define ETH_SPEED_10M ((uint32_t)0x00000000U) +#define ETH_SPEED_10M 0x00000000U #define ETH_SPEED_100M ETH_MACCR_FES /** * @} @@ -1364,7 +1370,7 @@ typedef struct * @{ */ #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM -#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U) +#define ETH_HALFDUPLEX_MODE 0x00000000U /** * @} */ @@ -1393,7 +1399,7 @@ typedef struct /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control * @{ */ -#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U) +#define ETH_SOURCEADDRESS_DISABLE 0x00000000U #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 @@ -1416,7 +1422,7 @@ typedef struct /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison * @{ */ -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) +#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV /** * @} @@ -1425,10 +1431,10 @@ typedef struct /** @defgroup ETH_MAC_addresses ETH MAC addresses * @{ */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) +#define ETH_MAC_ADDRESS0 0x00000000U +#define ETH_MAC_ADDRESS1 0x00000008U +#define ETH_MAC_ADDRESS2 0x00000010U +#define ETH_MAC_ADDRESS3 0x00000018U /** * @} */ @@ -1472,11 +1478,11 @@ typedef struct /** @defgroup HAL_ETH_StateTypeDef ETH States * @{ */ -#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */ -#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */ -#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */ -#define HAL_ETH_STATE_STARTED ((uint32_t)0x00000023U) /*!< an internal process is started */ -#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */ +#define HAL_ETH_STATE_RESET 0x00000000U /*!< Peripheral not yet Initialized or disabled */ +#define HAL_ETH_STATE_READY 0x00000010U /*!< Peripheral Communication started */ +#define HAL_ETH_STATE_BUSY 0x00000023U /*!< an internal process is ongoing */ +#define HAL_ETH_STATE_STARTED 0x00000023U /*!< an internal process is started */ +#define HAL_ETH_STATE_ERROR 0x000000E0U /*!< Error State */ /** * @} */ @@ -1484,8 +1490,8 @@ typedef struct /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status * @{ */ -#define HAL_ETH_PTP_NOT_CONFIGURATED ((uint32_t)0x00000000U) /*!< ETH PTP Configuration not done */ -#define HAL_ETH_PTP_CONFIGURATED ((uint32_t)0x00000001U) /*!< ETH PTP Configuration done */ +#define HAL_ETH_PTP_NOT_CONFIGURATED 0x00000000U /*!< ETH PTP Configuration not done */ +#define HAL_ETH_PTP_CONFIGURATED 0x00000001U /*!< ETH PTP Configuration done */ /** * @} */ @@ -1602,7 +1608,7 @@ typedef struct (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ -#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */ +#define ETH_WAKEUP_EXTI_LINE 0x00400000U /* !< 86 - 64 = 22 */ /** * @brief Enable the ETH WAKEUP Exti Line. diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h index 93003d55b9..c41784ea9d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h @@ -169,8 +169,8 @@ typedef struct /** @defgroup ETHEx_L3_Filter ETHEx L3 Filter * @{ */ -#define ETH_L3_FILTER_0 ((uint32_t)0x00000000) -#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C) +#define ETH_L3_FILTER_0 0x00000000U +#define ETH_L3_FILTER_1 0x0000000CU /** * @} */ @@ -178,8 +178,8 @@ typedef struct /** @defgroup ETHEx_L4_Filter ETHEx L4 Filter * @{ */ -#define ETH_L4_FILTER_0 ((uint32_t)0x00000000) -#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C) +#define ETH_L4_FILTER_0 0x00000000U +#define ETH_L4_FILTER_1 0x0000000CU /** * @} */ @@ -188,7 +188,7 @@ typedef struct * @{ */ #define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN -#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000) +#define ETH_L3_IPV4_MATCH 0x00000000U /** * @} */ @@ -198,7 +198,7 @@ typedef struct */ #define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM #define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM) -#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000) +#define ETH_L3_SRC_ADDR_MATCH_DISABLE 0x00000000U /** * @} */ @@ -208,7 +208,7 @@ typedef struct */ #define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM #define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM) -#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000) +#define ETH_L3_DEST_ADDR_MATCH_DISABLE 0x00000000U /** * @} */ @@ -217,7 +217,7 @@ typedef struct * @{ */ #define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN -#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000) +#define ETH_L4_TCP_MATCH 0x00000000U /** * @} */ @@ -227,7 +227,7 @@ typedef struct */ #define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM #define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) -#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000) +#define ETH_L4_SRC_PORT_MATCH_DISABLE 0x00000000U /** * @} */ @@ -237,7 +237,7 @@ typedef struct */ #define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM #define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM) -#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000) +#define ETH_L4_DEST_PORT_MATCH_DISABLE 0x00000000U /** * @} */ @@ -269,7 +269,7 @@ typedef struct */ #define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC #define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL) -#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000) +#define ETH_VLANTYPECHECK_CVLAN 0x00000000U /** * @} */ @@ -288,8 +288,8 @@ typedef struct /** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag * @{ */ -#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U) -#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U) +#define ETH_INNER_TX_VLANTAG 0x00000001U +#define ETH_OUTER_TX_VLANTAG 0x00000000U /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h index f822f09bb7..28bb380ec3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h @@ -744,6 +744,9 @@ typedef struct * @} */ #endif /* FLASH_OTPBL_LOCKBL */ +/** + * @} + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros @@ -756,9 +759,6 @@ typedef struct * @retval The FLASH Boot Base Address */ #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) - /** - * @} - */ #if defined (FLASH_CR_PSIZE) /** @@ -806,6 +806,9 @@ typedef struct * This return value can be a value of @ref FLASHEx_Programming_Delay */ #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) + /** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FLASHEx_Exported_Functions @@ -1002,10 +1005,6 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); * @} */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h index 25b760ff22..073bad9043 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fmac.h @@ -69,10 +69,12 @@ typedef struct uint32_t FilterParam; /*!< Filter configuration (operation and parameters). Set to 0 if no valid configuration was applied. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. + uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ int16_t *pInput; /*!< Pointer to FMAC input data buffer */ @@ -95,7 +97,8 @@ typedef struct DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */ - DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */ + DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle + parameters */ #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1) void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */ @@ -164,37 +167,39 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer */ typedef struct { - uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). - Ignored if InputBufferSize is set to 0 + uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory + (0x00 to 0xFF). Ignored if InputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ - uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom"). + uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer + (including the optional "headroom"). 0 if a previous configuration should be kept. */ - uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces - in the buffer is lower than this threshold. + uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number + of free spaces in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ - uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). - Ignored if CoeffBufferSize is set to 0 + uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal + memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept. */ - uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). - Ignored if OuputBufferSize is set to 0 + uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal + memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0 (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ - uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom"). + uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer + (including the optional "headroom"). 0 if a previous configuration should be kept. */ - uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values - in the buffer is lower than this threshold. + uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number + of unread values in the buffer is lower than this threshold. This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ @@ -209,14 +214,16 @@ typedef struct uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */ - uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None. + uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None. + uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): + DMA, IT, Polling, None. This parameter can be a value of @ref FMAC_Buffer_Access. */ - uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping - is done when the clipping feature is disabled + uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range + is exceeded, wrapping is done when the clipping feature is disabled and saturation is done when the clipping feature is enabled. This parameter can be a value of @ref FMAC_Clip_State. */ @@ -266,11 +273,11 @@ typedef struct /** @defgroup FMAC_Functions FMAC Functions * @{ */ -#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ -#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ -#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ -#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ -#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -279,18 +286,22 @@ typedef struct * @{ * @note This parameter sets a watermark for buffer full (input) or buffer empty (output). */ -#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 1. */ -#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 2. */ -#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 4. */ -#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. - Output: Buffer empty flag set if the number - of unread values in the buffer is less than 8. */ +#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 1. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 1. */ +#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 2. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 2. */ +#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 4. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 4. */ +#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces + in the buffer is less than 8. + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 8. */ #define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */ /** * @} @@ -323,7 +334,8 @@ typedef struct #define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ #define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ #define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ -#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ +#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag + (this helps in debugging a filter) */ /** * @} */ @@ -335,7 +347,8 @@ typedef struct #define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ #define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ #define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ -#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ +#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable + (this helps in debugging a filter) */ /** * @} */ @@ -345,8 +358,8 @@ typedef struct */ -/* External variables --------------------------------------------------------*/ -/** @defgroup FMAC_External_variables FMAC External variables +/* Exported variables --------------------------------------------------------*/ +/** @defgroup FMAC_Exported_variables FMAC Exported variables * @{ */ /** @@ -358,7 +371,8 @@ typedef struct * @{ */ -/** @brief Reset FMAC handle state. +/** + * @brief Reset FMAC handle state. * @param __HANDLE__ FMAC handle. * @retval None */ @@ -402,7 +416,8 @@ typedef struct #define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -/** @brief Check whether the specified FMAC interrupt occurred or not. +/** + * @brief Check whether the specified FMAC interrupt occurred or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. * This parameter can be any combination of the following values: @@ -416,7 +431,8 @@ typedef struct #define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__)) -/** @brief Clear specified FMAC interrupt status. Dummy macro as the +/** + * @brief Clear specified FMAC interrupt status. Dummy macro as the interrupt status flags are read-only. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to clear. @@ -424,7 +440,8 @@ typedef struct */ #define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */ -/** @brief Check whether the specified FMAC status flag is set or not. +/** + * @brief Check whether the specified FMAC status flag is set or not. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to check. * This parameter can be any combination of the following values: @@ -438,7 +455,8 @@ typedef struct #define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \ ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/** @brief Clear specified FMAC status flag. Dummy macro as no +/** + * @brief Clear specified FMAC status flag. Dummy macro as no flag can be cleared. * @param __HANDLE__ FMAC handle. * @param __FLAG__ FMAC flag to clear. @@ -446,7 +464,8 @@ typedef struct */ #define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */ -/** @brief Check whether the specified FMAC interrupt is enabled or not. +/** + * @brief Check whether the specified FMAC interrupt is enabled or not. * @param __HANDLE__ FMAC handle. * @param __INTERRUPT__ FMAC interrupt to check. * This parameter can be one of the following values: diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h index 6443015b33..7c853ca50f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h @@ -159,6 +159,10 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ & (__INTERRUPT__)) == (__INTERRUPT__)) + +#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ + ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -283,9 +287,6 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); -/** - * @} - */ /** * @} @@ -306,6 +307,9 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /** * @} */ +/** + * @} + */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h index 4b418f2c54..7b709f3e7b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h @@ -1172,9 +1172,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @brief Constants defining division ratio between the timer clock frequency * (fHRTIM) and the dead-time generator clock (fDTG) */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */ -#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */ #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ @@ -2419,10 +2416,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ @@ -3202,7 +3196,7 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); /** * @} */ @@ -3244,7 +3238,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OCChannel, - HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3284,7 +3278,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, - HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3324,7 +3318,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, - HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3364,7 +3358,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, - HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3390,18 +3384,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, * @{ */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef* pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef* pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); @@ -3412,7 +3406,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); /** * @} @@ -3424,22 +3418,22 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef * pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef* pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef* pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef * pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3449,15 +3443,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3522,30 +3516,30 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @{ */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); -uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim); +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); -uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h index 0b882ac0df..f70625056e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h @@ -217,6 +217,10 @@ typedef struct __I2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h index 060f5b64a5..407bf2ccb3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h @@ -101,7 +101,7 @@ typedef struct __I2S_HandleTypeDef I2S_InitTypeDef Init; /*!< I2S communication parameters */ - uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ + const uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ @@ -482,23 +482,23 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca */ /* I/O operation functions ***************************************************/ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout); /* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, uint16_t Size); void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); @@ -521,8 +521,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ @@ -542,6 +542,15 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @} */ +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/* Private functions are defined in stm32h7xx_hal_i2S.c file */ +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup I2S_Private_Macros I2S Private Macros * @{ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h index f789217ab4..67546df1c7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h @@ -867,8 +867,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); */ /* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h index 3ae7d76b8a..4a97f27cad 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h @@ -619,9 +619,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h index f8f0daf54c..ed4e5e5ade 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h @@ -121,7 +121,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -647,19 +647,20 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); */ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, - uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h index a5a21e2339..ef354861f5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h @@ -145,10 +145,6 @@ void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; -/** - * @} - */ - #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) /** * @brief HAL OPAMP Callback ID enumeration definition @@ -165,7 +161,9 @@ typedef enum */ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ - +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h index 27f7fdf6d2..c622c97d26 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h @@ -190,14 +190,14 @@ typedef struct * @brief macros to handle interrupts and specific clock configurations * @{ */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ @@ -351,7 +351,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h index 78d6fcc8b8..3d9040ceb5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h @@ -106,9 +106,6 @@ typedef struct __PSSI_HandleTypeDef */ typedef void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi); /*!< Pointer to a PSSI common callback function */ -/** - * @} - */ /** * @brief HAL PSSI Callback ID enumeration definition */ @@ -124,6 +121,11 @@ typedef enum } HAL_PSSI_CallbackIDTypeDef; + +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup PSSI_Exported_Constants PSSI Exported Constants * @{ @@ -174,7 +176,7 @@ typedef enum * @} */ -/** @defgroup PSSI_ControlSignal Configuration +/** @defgroup ControlSignal_Configuration ControlSignal Configuration * @{ */ #define HAL_PSSI_DE_RDY_DISABLE (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */ @@ -191,7 +193,7 @@ typedef enum */ -/** @defgroup PSSI_Data_Enable_Polarity Data Enable Polarity +/** @defgroup Data_Enable_Polarity Data Enable Polarity * @{ */ #define HAL_PSSI_DEPOL_ACTIVE_LOW 0x0U /*!< Active Low */ @@ -199,7 +201,7 @@ typedef enum /** * @} */ -/** @defgroup PSSI_Reday_Polarity Reday Polarity +/** @defgroup Reday_Polarity Reday Polarity * @{ */ #define HAL_PSSI_RDYPOL_ACTIVE_LOW 0x0U /*!< Active Low */ @@ -208,7 +210,7 @@ typedef enum * @} */ -/** @defgroup PSSI_Clock_Polarity Clock Polarity +/** @defgroup Clock_Polarity Clock Polarity * @{ */ #define HAL_PSSI_FALLING_EDGE 0x0U /*!< Fallling Edge */ @@ -231,7 +233,7 @@ typedef enum #define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */ #define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */ -#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable */ +#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable*/ #define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */ #define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */ @@ -357,6 +359,7 @@ typedef enum */ #define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) + /** * @brief Check whether the PSSI Control signal is valid. * @param __CONTROL__ Control signals configuration @@ -371,6 +374,9 @@ typedef enum ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE ) || \ ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE ) || \ ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE )) + + + /** * @brief Check whether the PSSI Bus Width is valid. * @param __BUSWIDTH__ PSSI Bush width @@ -381,6 +387,7 @@ typedef enum ((__BUSWIDTH__) == HAL_PSSI_16LINES )) /** + * @brief Check whether the PSSI Clock Polarity is valid. * @param __CLOCKPOL__ PSSI Clock Polarity * @retval Valid or not. @@ -388,6 +395,8 @@ typedef enum #define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE ) || \ ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE )) + + /** * @brief Check whether the PSSI Data Enable Polarity is valid. * @param __DEPOL__ PSSI DE Polarity @@ -396,6 +405,7 @@ typedef enum #define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW ) || \ ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH )) + /** * @brief Check whether the PSSI Ready Polarity is valid. * @param __RDYPOL__ PSSI RDY Polarity @@ -403,18 +413,18 @@ typedef enum */ #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW ) || \ - ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) + ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH )) /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup PSSI_Exported_Functions +/** @addtogroup PSSI_Exported_Functions PSSI Exported Functions * @{ */ -/** @addtogroup PSSI_Exported_Functions_Group1 +/** @addtogroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ @@ -425,7 +435,8 @@ void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi); void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi); /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, + pPSSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID); @@ -433,7 +444,8 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS * @} */ -/** @addtogroup PSSI_Exported_Functions_Group2 + +/** @addtogroup PSSI_Exported_Functions_Group2 Input and Output operation functions * @{ */ @@ -443,38 +455,40 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size); HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi); -void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); /** * @} */ -/** @addtogroup PSSI_Exported_Functions_Group3 +/** @addtogroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions * @{ */ -void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi); -void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); -void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); -void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); - +/* Peripheral State functions ***************************************************/ +HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); +uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); /** * @} */ -/** @addtogroup PSSI_Exported_Functions_Group4 +/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks * @{ */ -/* Peripheral State functions ***************************************************/ -HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi); -uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi); +void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi); + /** * @} */ + + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h index c15ca58e49..37a90def9a 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h @@ -72,7 +72,9 @@ typedef struct __RAMECC_HandleTypeDef /* Exported constants --------------------------------------------------------*/ - +/** @defgroup RAMECC_Exported_Constants RAMECC Exported Constants + * @{ + */ /** @defgroup RAMECC_Error_Codes RAMECC Error Codes * @{ */ @@ -113,6 +115,9 @@ typedef struct __RAMECC_HandleTypeDef #define RAMECC_FLAG_DOUBLEERR_W RAMECC_SR_DEBWDF #define RAMECC_FLAGS_ALL (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF) +/** + * @} + */ /** * @} */ @@ -277,8 +282,8 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc); * @} */ -/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions - * @brief Error information functions +/** @defgroup RAMECC_Exported_Functions_Group4 State and Error Functions + * @brief State and Error Functions * @{ */ HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc); @@ -324,10 +329,6 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc); * @} */ -/** @defgroup RAMECC_FLAG RAMECC Monitor flags - * @{ - */ - /* Private functions ---------------------------------------------------------*/ /** @defgroup RAMECC_Private_Functions RAMECC Private Functions * @brief RAMECC private functions @@ -341,10 +342,6 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc); * @} */ -/** - * @} - */ - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h index 59701d1339..1626c6d050 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h @@ -20,7 +20,7 @@ #define STM32H7xx_HAL_RCC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -76,7 +76,7 @@ typedef struct uint32_t PLLFRACN; /*!PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) +#define __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos) /** @brief Macro to select the PLL1 reference frequency range. @@ -7958,9 +7958,9 @@ typedef struct #include "stm32h7xx_hal_rcc_ex.h" /* Exported functions --------------------------------------------------------*/ - /** @addtogroup RCC_Exported_Functions - * @{ - */ +/** @addtogroup RCC_Exported_Functions + * @{ + */ /** @addtogroup RCC_Exported_Functions_Group1 * @{ @@ -7990,7 +7990,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CCSCallback(void); +void HAL_RCC_CSSCallback(void); /** * @} @@ -8013,6 +8013,7 @@ void HAL_RCC_CCSCallback(void); #define CSI_TIMEOUT_VALUE (2U) /* 2 ms */ #define LSI_TIMEOUT_VALUE (2U) /* 2 ms */ #define PLL_TIMEOUT_VALUE (2U) /* 2 ms */ +#define PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */ #define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ #define RCC_DBP_TIMEOUT_VALUE (100U) #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h index 32b16b72c5..2fb1fd2906 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h @@ -20,7 +20,7 @@ #define STM32H7xx_HAL_RCC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -69,7 +69,7 @@ typedef struct uint32_t PLL2FRACN; /*!PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) +#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos) /** @brief Macro to select the PLL3 reference frequency range. * @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range @@ -3127,12 +3134,12 @@ typedef struct #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL))) #endif /* RCC_D3CCIPR_ADCSEL */ - /** @brief Macro to configure the SWPMI1 clock - * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. - * This parameter can be one of the following values: - * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock - * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock - */ +/** @brief Macro to configure the SWPMI1 clock + * @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock + * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock + */ #if defined(RCC_D2CCIP1R_SWPSEL) #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__)) @@ -3152,12 +3159,12 @@ typedef struct #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL))) #endif /* RCC_D2CCIP1R_SWPSEL */ - /** @brief Macro to configure the DFSDM1 clock - * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock - * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock - */ +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock + */ #if defined(RCC_D2CCIP1R_DFSDM1SEL) #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \ MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__)) @@ -3178,12 +3185,12 @@ typedef struct #endif /* RCC_D2CCIP1R_DFSDM1SEL */ #if defined(DFSDM2_BASE) - /** @brief Macro to configure the DFSDM2 clock - * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock - * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock - */ +/** @brief Macro to configure the DFSDM2 clock + * @param __DFSDM2CLKSource__ specifies the DFSDM2 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1: SRDPCLK1 (APB4) selected as DFSDM2 clock + * @arg RCC_DFSDM2CLKSOURCE_SYS: System Clock selected as DFSDM2 clock + */ #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \ MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__)) @@ -3391,7 +3398,7 @@ typedef struct * @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived * from system PCLK, PLL2, PLL3, OSC * This parameter can be one of the following values: - * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI @@ -3409,7 +3416,7 @@ typedef struct /** @brief Macro to get the SPI4/5 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1 + * @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2 * @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2 * @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3 * @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI @@ -3427,7 +3434,7 @@ typedef struct * @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived * from system PCLK, PLL2, PLL3, OSC * This parameter can be one of the following values: - * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI @@ -3439,7 +3446,7 @@ typedef struct /** @brief Macro to get the SPI4 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1 + * @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2 * @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2 * @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3 * @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI @@ -3453,7 +3460,7 @@ typedef struct * @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived * from system PCLK, PLL2, PLL3, OSC * This parameter can be one of the following values: - * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI @@ -3465,7 +3472,7 @@ typedef struct /** @brief Macro to get the SPI5 clock source. * @retval The clock source can be one of the following values: - * @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1 + * @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2 * @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2 * @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3 * @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI @@ -3831,9 +3838,9 @@ typedef struct } \ } while(0) - /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features - * @{ - */ +/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features + * @{ + */ /** * @brief Enable the oscillator clock for frequency error counter. * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. @@ -3884,22 +3891,22 @@ typedef struct /* Exported functions --------------------------------------------------------*/ - /** @addtogroup RCCEx_Exported_Functions - * @{ - */ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ /** @addtogroup RCCEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); uint32_t HAL_RCCEx_GetD1PCLK1Freq(void); uint32_t HAL_RCCEx_GetD3PCLK1Freq(void); uint32_t HAL_RCCEx_GetD1SysClockFreq(void); -void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks); -void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks); -void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks); +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); /** * @} */ @@ -3947,7 +3954,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); * @} */ - /* Private macros ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros * @{ */ @@ -4112,7 +4119,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) || \ ((SOURCE) == RCC_I2C4CLKSOURCE_HSI) || \ ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \ - ((SOURCE) == RCC_I2C3CLKSOURCE_CSI)) + ((SOURCE) == RCC_I2C4CLKSOURCE_CSI)) #if defined(I2C5) #define IS_RCC_I2C5CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3) || \ @@ -4215,7 +4222,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN)) #define IS_RCC_SPI45CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) || \ + (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2) || \ ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) || \ @@ -4223,7 +4230,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE)) #define IS_RCC_SPI4CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) || \ + (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2) || \ ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) || \ @@ -4231,7 +4238,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE)) #define IS_RCC_SPI5CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \ + (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \ ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) || \ ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) || \ ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) || \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h index 9bebc965f1..ad0fa135f4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h @@ -78,10 +78,10 @@ typedef struct uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -#if defined(RTC_CR_TAMPALRM_PU) +#if defined(TAMP) uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ -#endif /* RTC_CR_TAMPALRM_PU */ +#endif /* TAMP */ } RTC_InitTypeDef; /** @@ -195,33 +195,21 @@ typedef struct void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */ -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */ -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */ -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ -#endif /* TAMP_CR1_ITAMP8E */ +#endif /* TAMP */ void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ @@ -244,28 +232,15 @@ typedef enum HAL_RTC_TAMPER1_EVENT_CB_ID = 4u, /*!< RTC Tamper 1 Callback ID */ HAL_RTC_TAMPER2_EVENT_CB_ID = 5u, /*!< RTC Tamper 2 Callback ID */ HAL_RTC_TAMPER3_EVENT_CB_ID = 6u, /*!< RTC Tamper 3 Callback ID */ - -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 12u, /*!< RTC Internal Tamper 1 Callback ID */ -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 13u, /*!< RTC Internal Tamper 2 Callback ID */ -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 14u, /*!< RTC Internal Tamper 3 Callback ID */ -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 15u, /*!< RTC Internal Tamper 4 Callback ID */ -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 16u, /*!< RTC Internal Tamper 5 Callback ID */ -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 17u, /*!< RTC Internal Tamper 6 Callback ID */ -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 19u, /*!< RTC Internal Tamper 8 Callback ID */ -#endif /* TAMP_CR1_ITAMP8E */ +#endif /* TAMP */ HAL_RTC_MSPINIT_CB_ID = 20u, /*!< RTC Msp Init callback ID */ HAL_RTC_MSPDEINIT_CB_ID = 21u /*!< RTC Msp DeInit callback ID */ } HAL_RTC_CallbackIDTypeDef; @@ -301,9 +276,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to #define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 #define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 #define RTC_OUTPUT_WAKEUP RTC_CR_OSEL -#if defined(RTC_CR_TAMPOE) +#if defined(TAMP) #define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE -#endif /* RTC_CR_TAMPOE */ +#endif /* TAMP */ /** * @} */ @@ -320,17 +295,15 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ -#if defined(RTC_CR_TAMPALRM_TYPE) +#if defined(TAMP) #define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000u #define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE #define RTC_ALARM_OUTPUT_TYPE RTC_CR_TAMPALRM_TYPE -#endif /* RTC_CR_TAMPALRM_TYPE */ - -#if defined(RTC_OR_ALARMOUTTYPE) +#else #define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMOUTTYPE #define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000u #define RTC_ALARM_OUTPUT_TYPE RTC_OR_ALARMOUTTYPE -#endif /* RTC_OR_ALARMOUTTYPE */ +#endif /* TAMP */ /** * @} */ @@ -338,10 +311,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT * @{ */ -#if defined(RTC_CR_TAMPALRM_PU) +#if defined(TAMP) #define RTC_OUTPUT_PULLUP_NONE 0x00000000u #define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU -#endif /* RTC_CR_TAMPALRM_PU */ +#endif /* TAMP */ /** * @} */ @@ -349,15 +322,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#if defined(RTC_CR_OUT2EN) +#if defined(TAMP) #define RTC_OUTPUT_REMAP_NONE 0x00000000u #define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN -#endif /* RTC_CR_OUT2EN */ - -#if defined(RTC_OR_OUT_RMP) +#else #define RTC_OUTPUT_REMAP_NONE 0x00000000u #define RTC_OUTPUT_REMAP_POS1 RTC_OR_OUT_RMP -#endif /* RTC_OR_OUT_RMP */ +#endif /* TAMP */ /** * @} */ @@ -523,122 +494,53 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#if defined(RTC_ICSR_RECALPF) +#if defined(TAMP) #define RTC_FLAG_RECALPF RTC_ICSR_RECALPF /*!< Recalibration pending Flag */ -#endif /* RTC_ICSR_RECALPF */ -#if defined(RTC_ICSR_INITF) #define RTC_FLAG_INITF RTC_ICSR_INITF /*!< Initialization pending flag */ -#endif /* RTC_ICSR_INITF */ -#if defined(RTC_ICSR_RSF) #define RTC_FLAG_RSF RTC_ICSR_RSF /*!< Registers synchronization flag */ -#endif /* RTC_ICSR_RSF */ -#if defined(RTC_ICSR_INITS) #define RTC_FLAG_INITS RTC_ICSR_INITS /*!< Initialization status flag */ -#endif /* RTC_ICSR_INITS */ -#if defined(RTC_ICSR_SHPF) #define RTC_FLAG_SHPF RTC_ICSR_SHPF /*!< Shift operation pending flag */ -#endif /* RTC_ICSR_SHPF */ -#if defined(RTC_ICSR_WUTWF) #define RTC_FLAG_WUTWF RTC_ICSR_WUTWF /*!< Wakeup timer write operation pending flag */ -#endif /* RTC_ICSR_WUTWF */ -#if defined(RTC_ICSR_ALRBWF) #define RTC_FLAG_ALRBWF RTC_ICSR_ALRBWF /*!< Alarm B write operation pending flag */ -#endif /* RTC_ICSR_ALRBWF */ -#if defined(RTC_ICSR_ALRAWF) #define RTC_FLAG_ALRAWF RTC_ICSR_ALRAWF /*!< Alarm A write operation pending flag */ -#endif /* RTC_ICSR_ALRAWF */ -#if defined(RTC_SR_ITSF) #define RTC_FLAG_ITSF RTC_SR_ITSF /*!< Internal Time-stamp flag */ -#endif /* RTC_SR_ITSF */ -#if defined(RTC_SR_TSOVF) #define RTC_FLAG_TSOVF RTC_SR_TSOVF /*!< Time-stamp overflow flag */ -#endif /* RTC_SR_TSOVF */ -#if defined(RTC_SR_TSF) #define RTC_FLAG_TSF RTC_SR_TSF /*!< Time-stamp flag */ -#endif /* RTC_SR_TSF */ -#if defined(RTC_SR_WUTF) #define RTC_FLAG_WUTF RTC_SR_WUTF /*!< Wakeup timer flag */ -#endif /* RTC_SR_WUTF */ -#if defined(RTC_SR_ALRBF) #define RTC_FLAG_ALRBF RTC_SR_ALRBF /*!< Alarm B flag */ -#endif /* RTC_SR_ALRBF */ -#if defined(RTC_SR_ALRAF) #define RTC_FLAG_ALRAF RTC_SR_ALRAF /*!< Alarm A flag */ -#endif /* RTC_SR_ALRAF */ -/** - * @} - */ - -/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions - * @{ - */ -#if defined(RTC_SCR_CITSF) -#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ -#endif /* RTC_SCR_CITSF */ -#if defined(RTC_SCR_CTSOVF) -#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ -#endif /* RTC_SCR_CTSOVF */ -#if defined(RTC_SCR_CTSF) -#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ -#endif /* RTC_SCR_CTSF */ -#if defined(RTC_SCR_CWUTF) -#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ -#endif /* RTC_SCR_CWUTF */ -#if defined(RTC_SCR_CALRBF) -#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ -#endif /* RTC_SCR_CALRBF */ -#if defined(RTC_SCR_CALRAF) -#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ -#endif /* RTC_SCR_CALRAF */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions RTC Flags Definitions - * @{ - */ -#if defined(RTC_ISR_RECALPF) +#else #define RTC_FLAG_RECALPF RTC_ISR_RECALPF -#endif /* RTC_ISR_RECALPF */ -#if defined(RTC_ISR_TSOVF) #define RTC_FLAG_TSOVF RTC_ISR_TSOVF -#endif /* RTC_ISR_TSOVF */ -#if defined(RTC_ISR_TSF) #define RTC_FLAG_TSF RTC_ISR_TSF -#endif /* RTC_ISR_TSF */ -#if defined(RTC_ISR_ITSF) #define RTC_FLAG_ITSF RTC_ISR_ITSF -#endif /* RTC_ISR_ITSF */ -#if defined(RTC_ISR_WUTF) #define RTC_FLAG_WUTF RTC_ISR_WUTF -#endif /* RTC_ISR_WUTF */ -#if defined(RTC_ISR_ALRBF) #define RTC_FLAG_ALRBF RTC_ISR_ALRBF -#endif /* RTC_ISR_ALRBF */ -#if defined(RTC_ISR_ALRAF) #define RTC_FLAG_ALRAF RTC_ISR_ALRAF -#endif /* RTC_ISR_ALRAF */ -#if defined(RTC_ISR_INITF) #define RTC_FLAG_INITF RTC_ISR_INITF -#endif /* RTC_ISR_INITF */ -#if defined(RTC_ISR_RSF) #define RTC_FLAG_RSF RTC_ISR_RSF -#endif /* RTC_ISR_RSF */ -#if defined(RTC_ISR_INITS) #define RTC_FLAG_INITS RTC_ISR_INITS -#endif /* RTC_ISR_INITS */ -#if defined(RTC_ISR_SHPF) #define RTC_FLAG_SHPF RTC_ISR_SHPF -#endif /* RTC_ISR_SHPF */ -#if defined(RTC_ISR_WUTWF) #define RTC_FLAG_WUTWF RTC_ISR_WUTWF -#endif /* RTC_ISR_WUTWF */ -#if defined(RTC_ISR_ALRBWF) #define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF -#endif /* RTC_ISR_ALRBWF */ -#if defined(RTC_ISR_ALRAWF) #define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF -#endif /* RTC_ISR_ALRAWF */ +#endif /* TAMP */ +/** + * @} + */ + +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#if defined(TAMP) +#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ +#endif /* TAMP + */ /** * @} */ @@ -687,6 +589,17 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to (__HANDLE__)->Instance->WPR = 0xFFU; \ } while(0u) +/** + * @brief Check whether the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#if defined(TAMP) +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ICSR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) +#else +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) +#endif /* TAMP */ + /** * @brief Add 1 hour (summer time change). * @param __HANDLE__ specifies the RTC handle. @@ -780,12 +693,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#if defined(RTC_MISR_ALRAMF) +#if defined(TAMP) #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U) -#endif /* RTC_MISR_ALRAMF */ -#if defined(RTC_ISR_ALRAF) +#else #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U) -#endif /* RTC_ISR_ALRAF */ +#endif /* TAMP */ /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -798,7 +710,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to */ #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#if defined(RTC_SR_ALRAF) +#if defined(TAMP) /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__ specifies the RTC handle. @@ -809,8 +721,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @retval None */ #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_SR_ALRAF */ -#if defined(RTC_ISR_ALRAF) +#else /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__ specifies the RTC handle. @@ -823,7 +734,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @retval None */ #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_ALRAF */ +#endif /* TAMP */ /** * @brief Clear the RTC Alarm's pending flags. @@ -834,12 +745,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#if defined(RTC_SCR_CALRAF) -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__) -#endif /* RTC_SCR_CALRAF */ -#if defined(RTC_ISR_ALRAF) +#if defined(TAMP) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = __FLAG__) +#else #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))) -#endif /* RTC_ISR_ALRAF */ +#endif /* TAMP */ /** @@ -1086,13 +996,13 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_INIT_MASK 0xFFFFFFFFu -#if defined(RTC_ICSR_INIT) && defined(RTC_ICSR_RSF) +#if defined(TAMP) +#define RTC_ICSR_RESERVED_MASK 0x000100FFu #define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) -#endif /* RTC_ICSR_INIT && RTC_ICSR_RSF */ - -#if defined(RTC_ISR_INIT) && defined(RTC_ISR_RSF) +#else +#define RTC_ISR_RESERVED_MASK 0x0003FFFFu #define RTC_RSF_MASK (~(RTC_ISR_INIT | RTC_ISR_RSF)) -#endif /* RTC_ISR_INIT && RTC_ISR_RSF */ +#endif /* TAMP */ #define RTC_TIMEOUT_VALUE 1000u @@ -1111,18 +1021,18 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ -#if defined(RTC_CR_TAMPOE) +#if defined(TAMP) #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ ((OUTPUT) == RTC_OUTPUT_TAMPER)) -#else /* RTC_CR_TAMPOE not defined */ +#else #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ ((OUTPUT) == RTC_OUTPUT_WAKEUP)) -#endif /* RTC_CR_TAMPOE */ +#endif /* TAMP */ #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ ((FORMAT) == RTC_HOURFORMAT_24)) @@ -1133,10 +1043,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) -#if defined(RTC_CR_TAMPALRM_PU) +#if defined(TAMP) #define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ ((TYPE) == RTC_OUTPUT_PULLUP_ON)) -#endif /* RTC_CR_TAMPALRM_PU */ +#endif /* TAMP */ #define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ ((REMAP) == RTC_OUTPUT_REMAP_POS1)) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h index f5798de18c..23ed81a5ca 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc_ex.h @@ -80,24 +80,22 @@ typedef struct * @} */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) /** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition * @{ */ typedef struct { uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin. - This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */ + This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins_Definitions */ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ } RTC_InternalTamperTypeDef; /** * @} */ -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_ATCR1_TAMP1AM) /** @defgroup RTCEx_Active_Seed_Size Seed size Definitions * @{ */ @@ -130,10 +128,10 @@ typedef struct This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */ uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ } RTC_ATampInputTypeDef; @@ -147,7 +145,7 @@ typedef struct This parameter can be a value of @ref RTCEx_ActiveTamper_Async_prescaler */ uint32_t TimeStampOnTamperDetection; /*!< Specifies the timeStamp on tamper detection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ uint32_t ActiveOutputChangePeriod; /*!< Specifies the Active Tamper output change period . This parameter can be a value from 0 to 7. */ @@ -164,7 +162,7 @@ typedef struct /** * @} */ -#endif /* TAMP_ATCR1_TAMP1AM */ +#endif /* TAMP */ /** * @} @@ -183,12 +181,11 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Number_Definitions RTC Backup Registers Number Definitions * @{ */ -#if defined(RTC_BKP_NUMBER) -#define BKP_REG_NUMBER RTC_BKP_NUMBER -#endif /* RTC_BKP_NUMBER */ -#if defined(TAMP_BKP_NUMBER) +#if defined(TAMP) #define BKP_REG_NUMBER TAMP_BKP_NUMBER -#endif /* TAMP_BKP_NUMBER */ +#else +#define BKP_REG_NUMBER RTC_BKP_NUMBER +#endif /* TAMP */ /** * @} */ @@ -262,25 +259,15 @@ typedef struct /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions * @{ */ -#if defined(TAMP_CR1_TAMP1E) -#define RTC_TAMPER_1 TAMP_CR1_TAMP1E -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) -#define RTC_TAMPER_2 TAMP_CR1_TAMP2E -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) -#define RTC_TAMPER_3 TAMP_CR1_TAMP3E -#endif /* TAMP_CR1_TAMP3E */ - -#if defined(RTC_TAMPCR_TAMP1E) +#if defined(TAMP) +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E +#else #define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) #define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) #define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E -#endif /* RTC_TAMPCR_TAMP3E */ +#endif /* TAMP */ #define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3) /** @@ -290,33 +277,23 @@ typedef struct /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions * @{ */ -#if defined(TAMP_IER_TAMP1IE) +#if defined(TAMP) #define RTC_IT_TAMP1 TAMP_IER_TAMP1IE /*!< Enable Tamper 1 Interrupt */ -#endif /* TAMP_IER_TAMP1IE */ -#if defined(TAMP_IER_TAMP2IE) #define RTC_IT_TAMP2 TAMP_IER_TAMP2IE /*!< Enable Tamper 2 Interrupt */ -#endif /* TAMP_IER_TAMP2IE */ -#if defined(TAMP_IER_TAMP3IE) #define RTC_IT_TAMP3 TAMP_IER_TAMP3IE /*!< Enable Tamper 3 Interrupt */ -#endif /* TAMP_IER_TAMP3IE */ - -#if defined(RTC_TAMPCR_TAMP1IE) +#else #define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */ -#endif /* RTC_TAMPCR_TAMP1IE */ -#if defined(RTC_TAMPCR_TAMP2IE) #define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */ -#endif /* RTC_TAMPCR_TAMP2IE */ -#if defined(RTC_TAMPCR_TAMP3IE) #define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /*!< Enable Tamper 3 Interrupt */ -#endif /* RTC_TAMPCR_TAMP3IE */ +#endif /* TAMP */ -#if defined(RTC_TAMPCR_TAMPIE) -#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /*!< Enable all Tamper Interrupts */ -#define RTC_IT_TAMPALL RTC_IT_TAMP -#else /* RTC_TAMPCR_TAMPIE not defined */ +#if defined(TAMP) #define RTC_IT_TAMP 0x00000000u /*!< No such feature in RTC3 */ #define RTC_IT_TAMPALL (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3) -#endif /* RTC_TAMPCR_TAMPIE */ +#else +#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /*!< Enable all Tamper Interrupts */ +#define RTC_IT_TAMPALL RTC_IT_TAMP +#endif /* TAMP */ /** * @} */ @@ -324,31 +301,20 @@ typedef struct /** @defgroup RTCEx_Internal_Tamper_Pins_Definitions RTCEx Internal Tamper Pins Definition * @{ */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) #define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) #define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) #define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) #define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) #define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) #define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) #define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E + #define RTC_INT_TAMPER_ALL (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\ RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\ RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\ RTC_INT_TAMPER_8) -#endif /* TAMP_CR1_ITAMP8E */ +#endif /* TAMP */ /** * @} */ @@ -356,27 +322,15 @@ typedef struct /** @defgroup RTCEx_Internal_Tamper_Interrupt_Definitions RTC Internal Tamper Interrupt * @{ */ -#if defined(TAMP_IER_ITAMP1IE) +#if defined(TAMP) #define RTC_INTERNAL_TAMPER1_INTERRUPT TAMP_IER_ITAMP1IE /*!< Enable Internal Tamper 1 Interrupt */ -#endif /* TAMP_IER_ITAMP1IE */ -#if defined(TAMP_IER_ITAMP2IE) #define RTC_INTERNAL_TAMPER2_INTERRUPT TAMP_IER_ITAMP2IE /*!< Enable Internal Tamper 2 Interrupt */ -#endif /* TAMP_IER_ITAMP2IE */ -#if defined(TAMP_IER_ITAMP3IE) #define RTC_INTERNAL_TAMPER3_INTERRUPT TAMP_IER_ITAMP3IE /*!< Enable Internal Tamper 3 Interrupt */ -#endif /* TAMP_IER_ITAMP3IE */ -#if defined(TAMP_IER_ITAMP4IE) #define RTC_INTERNAL_TAMPER4_INTERRUPT TAMP_IER_ITAMP4IE /*!< Enable Internal Tamper 4 Interrupt */ -#endif /* TAMP_IER_ITAMP4IE */ -#if defined(TAMP_IER_ITAMP5IE) #define RTC_INTERNAL_TAMPER5_INTERRUPT TAMP_IER_ITAMP5IE /*!< Enable Internal Tamper 5 Interrupt */ -#endif /* TAMP_IER_ITAMP5IE */ -#if defined(TAMP_IER_ITAMP6IE) #define RTC_INTERNAL_TAMPER6_INTERRUPT TAMP_IER_ITAMP6IE /*!< Enable Internal Tamper 6 Interrupt */ -#endif /* TAMP_IER_ITAMP6IE */ -#if defined(TAMP_IER_ITAMP8IE) #define RTC_INTERNAL_TAMPER8_INTERRUPT TAMP_IER_ITAMP8IE /*!< Enable Internal Tamper 8 Interrupt */ -#endif /* TAMP_IER_ITAMP8IE */ +#endif /* TAMP */ /** * @} */ @@ -384,30 +338,20 @@ typedef struct /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions * @{ */ -#define RTC_TAMPERTRIGGER_RISINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ -#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x02u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0x01u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x02u /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ #define RTC_TAMPERTRIGGER_LOWLEVEL 0x04u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ #define RTC_TAMPERTRIGGER_HIGHLEVEL 0x08u /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ -#if defined(TAMP_CR2_TAMP1TRG) +#if defined(TAMP) #define RTC_TAMPER_1_TRIGGER TAMP_CR2_TAMP1TRG -#endif /* TAMP_CR2_TAMP1TRG */ -#if defined(TAMP_CR2_TAMP2TRG) #define RTC_TAMPER_2_TRIGGER TAMP_CR2_TAMP2TRG -#endif /* TAMP_CR2_TAMP2TRG */ -#if defined(TAMP_CR2_TAMP3TRG) #define RTC_TAMPER_3_TRIGGER TAMP_CR2_TAMP3TRG -#endif /* TAMP_CR2_TAMP3TRG */ - -#if defined(RTC_TAMPCR_TAMP1TRG) +#else #define RTC_TAMPER_1_TRIGGER RTC_TAMPCR_TAMP1TRG -#endif /* RTC_TAMPCR_TAMP1TRG */ -#if defined(RTC_TAMPCR_TAMP2TRG) #define RTC_TAMPER_2_TRIGGER RTC_TAMPCR_TAMP2TRG -#endif /* RTC_TAMPCR_TAMP2TRG */ -#if defined(RTC_TAMPCR_TAMP3TRG) #define RTC_TAMPER_3_TRIGGER RTC_TAMPCR_TAMP3TRG -#endif /* RTC_TAMPCR_TAMP3TRG */ +#endif /* TAMP */ #define RTC_TAMPER_X_TRIGGER (RTC_TAMPER_1_TRIGGER |\ RTC_TAMPER_2_TRIGGER |\ @@ -419,34 +363,23 @@ typedef struct /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions * @{ */ -#if defined(TAMP_CR2_TAMP1NOERASE) -#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u -#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u -#endif /* TAMP_CR2_TAMP1NOERASE */ -#if defined(RTC_TAMPCR_TAMP1NOERASE) +#if defined(TAMP) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u +#else #define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000u #define RTC_TAMPER_ERASE_BACKUP_DISABLE RTC_TAMPCR_TAMP1NOERASE -#endif /* RTC_TAMPCR_TAMP1NOERASE */ +#endif /* TAMP */ -#if defined(TAMP_CR2_TAMP1NOERASE) +#if defined(TAMP) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 TAMP_CR2_TAMP1NOERASE -#endif /* TAMP_CR2_TAMP1NOERASE */ -#if defined(TAMP_CR2_TAMP2NOERASE) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 TAMP_CR2_TAMP2NOERASE -#endif /* TAMP_CR2_TAMP2NOERASE */ -#if defined(TAMP_CR2_TAMP3NOERASE) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 TAMP_CR2_TAMP3NOERASE -#endif /* TAMP_CR2_TAMP3NOERASE */ - -#if defined(RTC_TAMPCR_TAMP1NOERASE) +#else #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 RTC_TAMPCR_TAMP1NOERASE -#endif /* RTC_TAMPCR_TAMP1NOERASE */ -#if defined(RTC_TAMPCR_TAMP2NOERASE) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 RTC_TAMPCR_TAMP2NOERASE -#endif /* RTC_TAMPCR_TAMP2NOERASE */ -#if defined(RTC_TAMPCR_TAMP3NOERASE) #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3 RTC_TAMPCR_TAMP3NOERASE -#endif /* RTC_TAMPCR_TAMP3NOERASE */ +#endif /* TAMP */ #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK (RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\ RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\ @@ -458,34 +391,23 @@ typedef struct /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions * @{ */ -#if defined(TAMP_CR2_TAMP1MSK) -#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u -#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u -#endif /* TAMP_CR2_TAMP1MSK */ -#if defined(RTC_TAMPCR_TAMP1MF) +#if defined(TAMP) +#define RTC_TAMPERMASK_FLAG_DISABLE 0x00u +#define RTC_TAMPERMASK_FLAG_ENABLE 0x01u +#else #define RTC_TAMPERMASK_FLAG_DISABLE 0x00000000u #define RTC_TAMPERMASK_FLAG_ENABLE RTC_TAMPCR_TAMP1MF -#endif /* RTC_TAMPCR_TAMP1MF */ +#endif /* TAMP */ -#if defined(TAMP_CR2_TAMP1MSK) +#if defined(TAMP) #define RTC_TAMPER_1_MASK_FLAG TAMP_CR2_TAMP1MSK -#endif /* TAMP_CR2_TAMP1MSK */ -#if defined(TAMP_CR2_TAMP2MSK) #define RTC_TAMPER_2_MASK_FLAG TAMP_CR2_TAMP2MSK -#endif /* TAMP_CR2_TAMP2MSK */ -#if defined(TAMP_CR2_TAMP3MSK) #define RTC_TAMPER_3_MASK_FLAG TAMP_CR2_TAMP3MSK -#endif /* TAMP_CR2_TAMP3MSK */ - -#if defined(RTC_TAMPCR_TAMP1MF) +#else #define RTC_TAMPER_1_MASK_FLAG RTC_TAMPCR_TAMP1MF -#endif /* RTC_TAMPCR_TAMP1MF */ -#if defined(RTC_TAMPCR_TAMP2MF) #define RTC_TAMPER_2_MASK_FLAG RTC_TAMPCR_TAMP2MF -#endif /* RTC_TAMPCR_TAMP2MF */ -#if defined(RTC_TAMPCR_TAMP3MF) #define RTC_TAMPER_3_MASK_FLAG RTC_TAMPCR_TAMP3MF -#endif /* RTC_TAMPCR_TAMP3MF */ +#endif /* TAMP */ #define RTC_TAMPER_X_MASK_FLAG (RTC_TAMPER_1_MASK_FLAG |\ RTC_TAMPER_2_MASK_FLAG |\ @@ -497,7 +419,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions * @{ */ -#if defined(TAMP_FLTCR_TAMPFLT) +#if defined(TAMP) #define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ #define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 @@ -508,8 +430,7 @@ typedef struct consecutive samples at the active level */ #define RTC_TAMPERFILTER_MASK TAMP_FLTCR_TAMPFLT /*!< Masking all bits except those of field TAMPFLT[1:0]. */ -#endif /* TAMP_FLTCR_TAMPFLT */ -#if defined(RTC_TAMPCR_TAMPFLT) +#else #define RTC_TAMPERFILTER_DISABLE 0x00000000u /*!< Tamper filter is disabled */ #define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 @@ -520,7 +441,7 @@ typedef struct consecutive samples at the active level. */ #define RTC_TAMPERFILTER_MASK RTC_TAMPCR_TAMPFLT /*!< Masking all bits except those of field TAMPFLT[1:0]. */ -#endif /* RTC_TAMPCR_TAMPFLT */ +#endif /* TAMP */ /** * @} */ @@ -528,7 +449,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions * @{ */ -#if defined(TAMP_FLTCR_TAMPFREQ) +#if defined(TAMP) #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled @@ -547,8 +468,7 @@ typedef struct with a frequency = RTCCLK / 256 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK TAMP_FLTCR_TAMPFREQ /*!< Masking all bits except those of field TAMPFREQ[2:0]*/ -#endif /* TAMP_FLTCR_TAMPFREQ */ -#if defined(RTC_TAMPCR_TAMPFREQ) +#else #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000u /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled @@ -567,7 +487,7 @@ typedef struct with a frequency = RTCCLK / 256 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAMPCR_TAMPFREQ /*!< Masking all bits except those of field TAMPFREQ[2:0]*/ -#endif /* RTC_TAMPCR_TAMPFREQ */ +#endif /* TAMP */ /** * @} */ @@ -575,7 +495,7 @@ typedef struct /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions * @{ */ -#if defined(TAMP_FLTCR_TAMPPRCH) +#if defined(TAMP) #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before @@ -586,8 +506,7 @@ typedef struct sampling during 8 RTCCLK cycles */ #define RTC_TAMPERPRECHARGEDURATION_MASK TAMP_FLTCR_TAMPPRCH /*!< Masking all bits except those of field TAMPPRCH[1:0] */ -#endif /* TAMP_FLTCR_TAMPPRCH */ -#if defined(RTC_TAMPCR_TAMPPRCH) +#else #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000u /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before @@ -598,7 +517,7 @@ typedef struct sampling during 8 RTCCLK cycles */ #define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAMPCR_TAMPPRCH /*!< Masking all bits except those of field TAMPPRCH[1:0] */ -#endif /* RTC_TAMPCR_TAMPPRCH */ +#endif /* TAMP */ /** * @} */ @@ -606,16 +525,15 @@ typedef struct /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions * @{ */ -#if defined(RTC_CR_TAMPTS) +#if defined(TAMP) #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_CR_TAMPTS /*!< Masking all bits except bit TAMPTS */ -#endif /* RTC_CR_TAMPTS */ -#if defined(RTC_TAMPCR_TAMPTS) +#else #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000u /*!< TimeStamp on Tamper Detection event is not saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAMPCR_TAMPTS /*!< Masking all bits except bit TAMPTS */ -#endif /* RTC_TAMPCR_TAMPTS */ +#endif /* TAMP */ /** * @} */ @@ -623,16 +541,15 @@ typedef struct /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions * @{ */ -#if defined(TAMP_FLTCR_TAMPPUDIS) +#if defined(TAMP) #define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< Tamper pins are pre-charged before sampling */ #define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ #define RTC_TAMPER_PULLUP_MASK TAMP_FLTCR_TAMPPUDIS /*!< Maskin all bits except bit TAMPPUDIS */ -#endif /* TAMP_FLTCR_TAMPPUDIS */ -#if defined(RTC_TAMPCR_TAMPPUDIS) +#else #define RTC_TAMPER_PULLUP_ENABLE 0x00000000u /*!< TimeStamp on Tamper Detection event saved */ #define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< TimeStamp on Tamper Detection event is not saved */ #define RTC_TAMPER_PULLUP_MASK RTC_TAMPCR_TAMPPUDIS /*!< Maskin all bits except bit TAMPPUDIS */ -#endif /* RTC_TAMPCR_TAMPPUDIS */ +#endif /* TAMP */ /** * @} */ @@ -640,11 +557,11 @@ typedef struct /** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Output Definitions * @{ */ -#if defined(RTC_CR_TAMPOE) +#if defined(TAMP) #define RTC_TAMPERDETECTIONOUTPUT_DISABLE 0x00000000u /*!< The tamper flag is not routed on TAMPALRM */ #define RTC_TAMPERDETECTIONOUTPUT_ENABLE RTC_CR_TAMPOE /*!< The tamper flag is routed on TAMPALRM combined with the signal provided by OSEL and with the polarity provided by POL */ -#endif /* RTC_CR_TAMPOE */ +#endif /* TAMP */ /** * @} */ @@ -652,25 +569,15 @@ typedef struct /** @defgroup RTC_Tamper_Flags_Definitions RTC Tamper Flags Definitions * @{ */ -#if defined(TAMP_SR_TAMP1F) +#if defined(TAMP) #define RTC_FLAG_TAMP1F TAMP_SR_TAMP1F -#endif /* TAMP_SR_TAMP1F */ -#if defined(TAMP_SR_TAMP2F) #define RTC_FLAG_TAMP2F TAMP_SR_TAMP2F -#endif /* TAMP_SR_TAMP2F */ -#if defined(TAMP_SR_TAMP3F) #define RTC_FLAG_TAMP3F TAMP_SR_TAMP3F -#endif /* TAMP_SR_TAMP3F */ - -#if defined(RTC_ISR_TAMP1F) +#else #define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F -#endif /* RTC_ISR_TAMP1F */ -#if defined(RTC_ISR_TAMP2F) #define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F -#endif /* RTC_ISR_TAMP2F */ -#if defined(RTC_ISR_TAMP3F) #define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F -#endif /* RTC_ISR_TAMP3F */ +#endif /* TAMP */ /** * @} */ @@ -743,10 +650,10 @@ typedef struct /** @defgroup RTCEx_Tamper_Registers_Offset RTC Tamper Registers Offset * @{ */ -#if defined (TAMP_CR1_TAMP1E) +#if defined(TAMP) /* Add this offset to RTC registers base address to reach TAMP registers base address. */ #define TAMP_OFFSET (TAMP_BASE - RTC_BASE) -#endif /* TAMP_CR1_TAMP1E */ +#endif /* TAMP */ /** * @} */ @@ -871,12 +778,11 @@ typedef struct * @arg RTC_FLAG_WUTF WakeUpTimer interrupt flag * @retval None */ -#if defined(RTC_SR_WUTF) +#if defined(TAMP) #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* RTC_SR_WUTF */ -#if defined(RTC_ISR_WUTF) +#else #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_WUTF */ +#endif /* TAMP */ /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. @@ -888,7 +794,7 @@ typedef struct */ #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#if defined(RTC_SR_WUTF) +#if defined(TAMP) /** * @brief Get the selected RTC WakeUpTimer's flag status. * @param __HANDLE__ specifies the RTC handle. @@ -898,8 +804,7 @@ typedef struct * @retval Flag status */ #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_SR_WUTF */ -#if defined(RTC_ISR_WUTF) +#else /** * @brief Get the selected RTC WakeUpTimer's flag status. * @param __HANDLE__ specifies the RTC handle. @@ -910,7 +815,7 @@ typedef struct * @retval Flag status */ #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_WUTF */ +#endif /* TAMP */ /** * @brief Clear the RTC Wake Up timer's pending flags. @@ -920,12 +825,11 @@ typedef struct * @arg @ref RTC_FLAG_WUTF * @retval None */ -#if defined(RTC_SCR_CWUTF) +#if defined(TAMP) #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__) -#endif /* RTC_SCR_CWUTF */ -#if defined(RTC_ISR_WUTF) +#else #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) -#endif /* RTC_ISR_WUTF */ +#endif /* TAMP */ /* ========================================================================== */ /* ##### RTC Tamper exported macros ##### */ @@ -936,72 +840,66 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E)) -#endif /* TAMP_CR1_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP1E) +#else #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) -#endif /* RTC_TAMPCR_TAMP1E */ +#endif /* TAMP */ /** * @brief Disable the RTC Tamper1 input detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E)) -#endif /* TAMP_CR1_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP1E) +#else #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) -#endif /* RTC_TAMPCR_TAMP1E */ +#endif /* TAMP */ /** * @brief Enable the RTC Tamper2 input detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(TAMP_CR1_TAMP2E) +#if defined(TAMP) #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E)) -#endif /* TAMP_CR1_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP2E) +#else #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) -#endif /* RTC_TAMPCR_TAMP2E */ +#endif /* TAMP */ /** * @brief Disable the RTC Tamper2 input detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(TAMP_CR1_TAMP2E) +#if defined(TAMP) #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E)) -#endif /* TAMP_CR1_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP2E) +#else #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) -#endif /* RTC_TAMPCR_TAMP2E */ +#endif /* TAMP */ /** * @brief Enable the RTC Tamper3 input detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(TAMP_CR1_TAMP3E) +#if defined(TAMP) #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E)) -#endif /* TAMP_CR1_TAMP3E */ -#if defined(RTC_TAMPCR_TAMP3E) +#else #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) -#endif /* RTC_TAMPCR_TAMP3E */ +#endif /* TAMP */ /** * @brief Disable the RTC Tamper3 input detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(TAMP_CR1_TAMP3E) +#if defined(TAMP) #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E)) -#endif /* TAMP_CR1_TAMP3E */ -#if defined(RTC_TAMPCR_TAMP3E) +#else #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) -#endif /* RTC_TAMPCR_TAMP3E */ +#endif /* TAMP */ /** * @brief Enable the RTC Tamper interrupt. @@ -1014,12 +912,11 @@ typedef struct * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#if defined(TAMP_IER_TAMP1IE) +#if defined(TAMP) #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__)) -#endif /* TAMP_IER_TAMP1IE */ -#if defined(RTC_TAMPCR_TAMP1IE) +#else #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) -#endif /* RTC_TAMPCR_TAMP1IE */ +#endif /* TAMP */ /** * @brief Disable the RTC Tamper interrupt. @@ -1032,12 +929,11 @@ typedef struct * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval None */ -#if defined(TAMP_IER_TAMP1IE) +#if defined(TAMP) #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__)) -#endif /* TAMP_IER_TAMP1IE */ -#if defined(RTC_TAMPCR_TAMP1IE) +#else #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) -#endif /* RTC_TAMPCR_TAMP1IE */ +#endif /* TAMP */ /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. @@ -1049,12 +945,11 @@ typedef struct * @arg RTC_FLAG_TAMP3F: Tamper3 interrupt flag * @retval Flag status */ -#if defined(TAMP_SR_TAMP1F) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* TAMP_SR_TAMP1F */ -#if defined(RTC_ISR_TAMP1F) +#else #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_TAMP1F */ +#endif /* TAMP */ /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. @@ -1067,12 +962,11 @@ typedef struct * @arg RTC_IT_TAMP3: Tamper3 interrupt * @retval Flag status */ -#if defined(TAMP_IER_TAMP1IE) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* TAMP_IER_TAMP1IE */ -#if defined(RTC_TAMPCR_TAMP1IE) +#else #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* RTC_TAMPCR_TAMP1IE */ +#endif /* TAMP */ /** * @brief Get the selected RTC Tamper's flag status. @@ -1084,12 +978,11 @@ typedef struct * @arg RTC_FLAG_TAMP3F: Tamper3 flag * @retval Flag status */ -#if defined(TAMP_SR_TAMP1F) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* TAMP_SR_TAMP1F */ -#if defined(RTC_ISR_TAMP1F) -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_TAMP1F */ +#else +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) +#endif /* TAMP */ /** * @brief Clear the RTC Tamper's pending flags. @@ -1101,12 +994,11 @@ typedef struct * @arg RTC_FLAG_TAMP3F: Tamper3 flag * @retval None */ -#if defined(TAMP_SCR_CTAMP1F) +#if defined(TAMP) #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__)) -#endif /* TAMP_SCR_CTAMP1F */ -#if defined(RTC_ISR_TAMP1F) +#else #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) -#endif /* RTC_ISR_TAMP1F */ +#endif /* TAMP */ /** * @brief Get the frequency at which each of the Tamper inputs are sampled. @@ -1121,12 +1013,11 @@ typedef struct * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 * @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 */ -#if defined(TAMP_FLTCR_TAMPFREQ) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK))) -#endif /* TAMP_FLTCR_TAMPFREQ */ -#if defined(RTC_TAMPCR_TAMPFREQ) +#else #define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__) ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK))) -#endif /* RTC_TAMPCR_TAMPFREQ */ +#endif /* TAMP */ /** * @brief Get the number of consecutive samples at the specified level needed @@ -1139,12 +1030,11 @@ typedef struct * @arg RTC_TAMPERFILTER_4SAMPLE * @arg RTC_TAMPERFILTER_8SAMPLE */ -#if defined(TAMP_FLTCR_TAMPFLT) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK))) -#endif /* TAMP_FLTCR_TAMPFLT */ -#if defined(RTC_TAMPCR_TAMPFLT) +#else #define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__) ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERFILTER_MASK))) -#endif /* RTC_TAMPCR_TAMPFLT */ +#endif /* TAMP */ /** * @brief Get the pull-up resistors precharge duration. @@ -1156,12 +1046,11 @@ typedef struct * @arg RTC_TAMPERPRECHARGEDURATION_4RTCCLK * @arg RTC_TAMPERPRECHARGEDURATION_8RTCCLK */ -#if defined(TAMP_FLTCR_TAMPPRCH) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK))) -#endif /* TAMP_FLTCR_TAMPPRCH */ -#if defined(RTC_TAMPCR_TAMPPRCH) +#else #define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__) ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERPRECHARGEDURATION_MASK))) -#endif /* RTC_TAMPCR_TAMPPRCH */ +#endif /* TAMP */ /** * @brief Get the pull-up resistors status. @@ -1171,12 +1060,11 @@ typedef struct * @arg RTC_TAMPER_PULLUP_ENABLE * @arg RTC_TAMPER_PULLUP_DISABLE */ -#if defined(TAMP_FLTCR_TAMPPUDIS) +#if defined(TAMP) #define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__) ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK))) -#endif /* TAMP_FLTCR_TAMPPUDIS */ -#if defined(RTC_TAMPCR_TAMPPUDIS) +#else #define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__) ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPER_PULLUP_MASK))) -#endif /* RTC_TAMPCR_TAMPPUDIS */ +#endif /* TAMP */ /* ========================================================================== */ /* ##### RTC TimeStamp exported macros ##### */ @@ -1224,12 +1112,11 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#if defined(RTC_SR_TSF) +#if defined(TAMP) #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U) -#endif /* RTC_SR_TSF */ -#if defined(RTC_ISR_TSF) +#else #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_TSF */ +#endif /* TAMP */ /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -1249,12 +1136,11 @@ typedef struct * @arg RTC_FLAG_TSOVF * @retval Flag status */ -#if defined(RTC_SR_TSF) +#if defined(TAMP) #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_SR_TSF */ -#if defined(RTC_ISR_TSF) +#else #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_TSF */ +#endif /* TAMP */ /** * @brief Clear the RTC Time Stamp's pending flags. @@ -1265,12 +1151,11 @@ typedef struct * @arg RTC_FLAG_TSOVF * @retval None */ -#if defined(RTC_SCR_CTSF) +#if defined(TAMP) #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__) -#endif /* RTC_SCR_CTSF */ -#if defined(RTC_ISR_TSF) +#else #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))) -#endif /* RTC_ISR_TSF */ +#endif /* TAMP */ /** * @brief Enable the RTC internal TimeStamp peripheral. @@ -1294,12 +1179,11 @@ typedef struct * @arg RTC_FLAG_ITSF * @retval Flag status */ -#if defined(RTC_SR_ITSF) +#if defined(TAMP) #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_SR_ITSF */ -#if defined(RTC_ISR_ITSF) +#else #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_ITSF */ +#endif /* TAMP */ /** * @brief Clear the RTC Internal Time Stamp's pending flags. @@ -1310,36 +1194,33 @@ typedef struct * @note This flag must be cleared together with TSF flag. * @retval None */ -#if defined(RTC_SCR_CITSF) +#if defined(TAMP) #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__) -#endif /* RTC_SCR_CITSF */ -#if defined(RTC_ISR_ITSF) +#else #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))) -#endif /* RTC_ISR_ITSF */ +#endif /* TAMP */ /** * @brief Enable the RTC TimeStamp on Tamper detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(RTC_CR_TAMPTS) +#if defined(TAMP) #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK)) -#endif /* RTC_CR_TAMPTS */ -#if defined(RTC_TAMPCR_TAMPTS) +#else #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK)) -#endif /* RTC_TAMPCR_TAMPTS */ +#endif /* TAMP */ /** * @brief Disable the RTC TimeStamp on Tamper detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#if defined(RTC_CR_TAMPTS) +#if defined(TAMP) #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK)) -#endif /* RTC_CR_TAMPTS */ -#if defined(RTC_TAMPCR_TAMPTS) +#else #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK)) -#endif /* RTC_TAMPCR_TAMPTS */ +#endif /* TAMP */ /** * @brief Get activation status of the RTC TimeStamp on Tamper detection. @@ -1349,14 +1230,13 @@ typedef struct * @arg RTC_TIMESTAMPONTAMPERDETECTION_ENABLE * @arg RTC_TIMESTAMPONTAMPERDETECTION_DISABLE */ -#if defined(RTC_CR_TAMPTS) +#if defined(TAMP) #define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__) ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK) -#endif /* RTC_CR_TAMPTS */ -#if defined(RTC_TAMPCR_TAMPTS) +#else #define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK) -#endif /* RTC_TAMPCR_TAMPTS */ +#endif /* TAMP */ -#if defined(RTC_CR_TAMPOE) +#if defined(TAMP) /** * @brief Enable the RTC Tamper detection output. * @param __HANDLE__ specifies the RTC handle. @@ -1370,7 +1250,7 @@ typedef struct * @retval None */ #define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE)) -#endif /* RTC_CR_TAMPOE */ +#endif /* TAMP */ /* ========================================================================== */ /* ##### Extended RTC Peripheral Control exported macros ##### */ @@ -1412,12 +1292,11 @@ typedef struct * @arg RTC_FLAG_SHPF * @retval Flag status */ -#if defined(RTC_ICSR_SHPF) +#if defined(TAMP) #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ICSR_SHPF */ -#if defined(RTC_ISR_SHPF) +#else #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) -#endif /* RTC_ISR_SHPF */ +#endif /* TAMP */ /* ========================================================================== */ /* ##### RTC Wake-up Interrupt exported macros ##### */ @@ -1798,30 +1677,17 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -#if defined(RTC_TAMPER_1) HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER_1 */ -#if defined(RTC_TAMPER_2) HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER_2 */ -#if defined(RTC_TAMPER_3) HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* RTC_TAMPER_3 */ -#if defined(RTC_TAMPER_1) void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER_1 */ -#if defined(RTC_TAMPER_2) void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER_2 */ -#if defined(RTC_TAMPER_3) void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* RTC_TAMPER_3 */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); -#endif /* TAMP_CR1_ITAMP1E */ void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); @@ -1829,15 +1695,10 @@ void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(TAMP_ATCR1_TAMP1AM) HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); -#endif /* TAMP_ATCR1_TAMP1AM */ -#if defined(TAMP_ATSEEDR_SEED) HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); -#endif /* TAMP_ATSEEDR_SEED */ -#if defined(TAMP_ATCR1_TAMP1AM) HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); -#endif /* TAMP_ATCR1_TAMP1AM */ +#endif /* TAMP */ /** * @} @@ -1895,10 +1756,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -#if defined(TAMP_COUNTR) +#if defined(TAMP) HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); -#endif /* TAMP_COUNTR */ +#endif /* TAMP */ /** * @} */ @@ -2005,15 +1866,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_X) != 0x00U) && \ (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U)) -#if defined(RTC_ALL_TAMPER_INTERRUPT) #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) \ - ((((__INTERRUPT__) & ( RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT )) != 0x00U) && \ - (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))) == 0x00U)) -#else /* RTC_ALL_TAMPER_INTERRUPT not defined */ -#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) \ - ((((__INTERRUPT__) & RTC_TAMPER_X_INTERRUPT ) != 0x00U) && \ - (((__INTERRUPT__) & (~RTC_TAMPER_X_INTERRUPT)) == 0x00U)) -#endif /* RTC_ALL_TAMPER_INTERRUPT */ + ((((__INTERRUPT__) & ( RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL )) != 0x00U) && \ + (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL))) == 0x00U)) #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ @@ -2051,10 +1906,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) -#if defined(RTC_CR_TAMPOE) +#if defined(TAMP) #define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(__MODE__) (((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \ ((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_DISABLE)) -#endif /* RTC_CR_TAMPOE */ +#endif /* TAMP */ #define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \ ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h index 892daa2f14..f9ca3649bb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h @@ -816,8 +816,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); * @{ */ /* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h index a946aeab0e..edc87c2861 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h @@ -69,7 +69,8 @@ typedef struct /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ -HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h index d465de6cc5..83fa74fded 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h @@ -126,7 +126,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< SD locking object */ - uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ uint32_t TxXferSize; /*!< SD Tx Transfer size */ @@ -634,18 +634,18 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, - uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h index 3aaaa7de7c..823ab354d9 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h @@ -1377,8 +1377,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) * @{ */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h index b53b0b4666..77578d191c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h @@ -150,7 +150,7 @@ typedef enum */ typedef struct { - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */ @@ -172,7 +172,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -215,6 +215,7 @@ typedef struct __SPI_HandleTypeDef void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ @@ -235,8 +236,9 @@ typedef enum HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ - HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */ - HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ } HAL_SPI_CallbackIDTypeDef; @@ -860,24 +862,24 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); #if defined(USE_SPI_RELOAD_TRANSFER) -HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); #endif /* USE_SPI_RELOAD_TRANSFER */ @@ -898,6 +900,7 @@ void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); /** * @} */ @@ -907,8 +910,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ @@ -922,19 +925,40 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); * @{ */ -/** @brief Set the SPI transmit-only mode. +/** @brief Set the SPI transmit-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR) +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) -/** @brief Set the SPI receive-only mode. +/** @brief Set the SPI receive-only mode in 1Line configuration. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR) +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ ((MODE) == SPI_MODE_MASTER)) @@ -1015,13 +1039,13 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ ((NSSP) == SPI_NSS_PULSE_DISABLE)) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ @@ -1078,6 +1102,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h index 9e583faef2..3e32a0e633 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h @@ -72,7 +72,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h index 157cc9c2e3..6daa529659 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h @@ -1824,7 +1824,7 @@ mode. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ - ((__MODE__) == TIM_UIFREMAP_ENALE)) + ((__MODE__) == TIM_UIFREMAP_ENABLE)) #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ @@ -1884,6 +1884,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ + ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ ((__CHANNEL__) == TIM_CHANNEL_3)) @@ -2203,7 +2206,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -2225,7 +2228,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2247,7 +2251,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2332,21 +2337,25 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, @@ -2356,7 +2365,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2393,17 +2402,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2417,9 +2426,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h index 026d01d90f..ebad016677 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h @@ -88,51 +88,51 @@ typedef struct /** @defgroup TIMEx_Remap TIM Extended Remapping * @{ */ -#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ -#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */ -#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */ - -#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ -#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */ -#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */ -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ -#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */ -#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */ -#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */ - -#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ -#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */ -#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */ -#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */ -#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */ -#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */ - -#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ -#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */ - -#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */ -#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */ -#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */ -#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */ -#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */ - -#define TIM_TIM23_ETR_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */ -#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */ -#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */ - -#define TIM_TIM24_ETR_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */ -#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */ -#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */ -#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */ -#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */ +#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ +#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */ +#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */ +#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */ +#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */ +#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */ +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ + +#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */ +#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */ +#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */ +#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ + +#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ +#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */ + +#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */ +#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */ +#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */ +#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */ +#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */ + +#define TIM_TIM23_ETR_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */ +#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */ +#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */ + +#define TIM_TIM24_ETR_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */ +#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */ +#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */ +#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */ +#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */ /** * @} */ @@ -150,10 +150,10 @@ typedef struct /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ -#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ /** * @} */ @@ -180,61 +180,61 @@ typedef struct /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection * @{ */ -#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */ -#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1_TI1 is connected to COMP1 OUT */ - -#define TIM_TIM8_TI1_GPIO 0x00000000U /* !< TIM8_TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8_TI1 is connected to COMP2 OUT */ - -#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to GPIO */ -#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2_TI4 is connected to COMP1 OUT */ -#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2_TI4 is connected to COMP2 OUT */ -#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */ - -#define TIM_TIM3_TI1_GPIO 0x00000000U /* !< TIM3_TI1 is connected to GPIO */ -#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3_TI1 is connected to COMP1 OUT */ -#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3_TI1 is connected to COMP2 OUT */ -#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */ - -#define TIM_TIM5_TI1_GPIO 0x00000000U /* !< TIM5_TI1 is connected to GPIO */ -#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */ -#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */ - -#define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */ -#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */ - -#define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */ -#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */ -#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */ -#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15_TI1 is connected to RCC LSE */ -#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI */ -#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */ - -#define TIM_TIM15_TI2_GPIO 0x00000000U /* !< TIM15_TI2 is connected to GPIO */ -#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15_TI2 is connected to TIM2 CH2 */ -#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM3 CH2 */ -#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */ - -#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16 TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 TI1 is connected to RCC LSI */ -#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 TI1 is connected to RCC LSE */ -#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */ - -#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */ -#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */ -#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */ - -#define TIM_TIM23_TI4_GPIO 0x00000000U /* !< TIM23_TI4 is connected to GPIO */ -#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23_TI4 is connected to COMP1 OUT */ -#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23_TI4 is connected to COMP2 OUT */ -#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */ - -#define TIM_TIM24_TI1_GPIO 0x00000000U /* !< TIM24_TI1 is connected to GPIO */ -#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24_TI1 is connected to CAN TMP */ -#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24_TI1 is connected to CAN RTP */ -#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */ +#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1_TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ + +#define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8_TI1 is connected to GPIO */ +#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP2 OUT */ + +#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ +#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */ + +#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ +#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ +#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5_TI1 is connected to GPIO */ +#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to CAN TMP */ +#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to CAN RTP */ + +#define TIM_TIM12_TI1_GPIO 0x00000000U /*!< TIM12 TI1 is connected to GPIO */ +#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */ + +#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */ +#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 */ +#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 */ +#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM4 CH1 */ +#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15_TI1 is connected to RCC LSE */ +#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to RCC CSI */ +#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to RCC MCO2 */ + +#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */ +#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM2 CH2 */ +#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM3 CH2 */ +#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM4 CH2 */ + +#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 TI1 is connected to RCC LSI */ +#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to RCC LSE */ +#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to WKUP_IT */ + +#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 TI1 is connected to SPDIF FS */ +#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to RCC HSE 1Mhz */ +#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to RCC MCO1 */ + +#define TIM_TIM23_TI4_GPIO 0x00000000U /*!< TIM23_TI4 is connected to GPIO */ +#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23_TI4 is connected to COMP1 OUT */ +#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23_TI4 is connected to COMP2 OUT */ +#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */ + +#define TIM_TIM24_TI1_GPIO 0x00000000U /*!< TIM24_TI1 is connected to GPIO */ +#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24_TI1 is connected to CAN TMP */ +#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24_TI1 is connected to CAN RTP */ +#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24_TI1 is connected to CAN SOC */ /** * @} */ @@ -370,7 +370,7 @@ typedef struct * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -403,7 +403,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -422,7 +423,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -456,12 +458,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); #if defined(TIM_BREAK_INPUT_SUPPORT) HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); #endif /* TIM_BREAK_INPUT_SUPPORT */ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); @@ -493,8 +495,8 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h index b20dec2435..c6fced0281 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h @@ -197,7 +197,7 @@ typedef enum /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, * HAL_UART_RECEPTION_TORTO = 0x02U, @@ -205,6 +205,17 @@ typedef enum */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -239,6 +250,8 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -808,7 +821,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -819,6 +832,16 @@ typedef void (*pUART_RxEventCallbackTypeDef) * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + /** * @} */ @@ -1669,8 +1692,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); */ /* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h index b60f9547cb..a9415bc184 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h @@ -178,6 +178,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h index 7afa3c1050..ffb8f7b328 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h @@ -1150,8 +1150,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); */ /* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h index 95c261b81a..a216926dbe 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h @@ -401,6 +401,14 @@ extern "C" { * @} */ +/** @defgroup ADC_LL_Alias_definition ADC Alias definition + * @{ + */ +#define LL_ADC_SetChannelPreSelection LL_ADC_SetChannelPreselection /* Alias of LL_ADC_SetChannelPreselection for backward compatibility. */ + +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Macros ADC Private Macros @@ -637,6 +645,7 @@ typedef struct #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ +#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag ADC LDO output voltage ready bit */ #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */ #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */ #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */ @@ -894,7 +903,7 @@ typedef struct /** * @} */ -#endif +#endif /* ADC_VER_V5_V90 */ #endif /* ADC_VER_V5_V90 */ @@ -940,7 +949,7 @@ typedef struct #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */ #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */ -#endif +#endif /* ADC_VER_V5_V90 */ #else /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */ @@ -1047,7 +1056,7 @@ typedef struct /** * @} */ -#endif +#endif /* ADC_VER_V5_V90 */ /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ @@ -1362,14 +1371,14 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config * @{ */ -#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ -#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC3_TR1_AWDFILT_1 ) /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC3_TR1_AWDFILT_2 ) /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 ) /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ +#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */ /** * @} */ @@ -2850,7 +2859,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 MODIFY_REG(ADCx->CALFACT, SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK, CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S))); -#endif +#endif /* ADC_VER_V5_V90 */ } /** @@ -2881,7 +2890,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); #else return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); -#endif +#endif /* ADC_VER_V5_V90 */ } /** @@ -2919,7 +2928,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32 timeout_cpu_cycles--; } } -#else /* ADC_VER_V5_V90 */ +#else uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT; MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor); MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord); @@ -2927,7 +2936,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32 { timeout_cpu_cycles--; } -#endif +#endif /* ADC_VER_V5_V90 */ } /** @@ -2958,7 +2967,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, ui return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT)); #else return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT)); -#endif +#endif /* ADC_VER_V5_V90 */ } /** * @brief Set ADC resolution. @@ -3034,12 +3043,14 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * @rmtoll CFGR RES LL_ADC_GetResolution * @param ADCx ADC instance * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_16B + * @arg @ref LL_ADC_RESOLUTION_16B (1) * @arg @ref LL_ADC_RESOLUTION_14B * @arg @ref LL_ADC_RESOLUTION_12B * @arg @ref LL_ADC_RESOLUTION_10B * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B **Value available for ADC3 on STM32H72x/3x devices only ** + * @arg @ref LL_ADC_RESOLUTION_6B (2) + * (1): Specific to ADC instance: ADC1, ADC2 + * (2): Specific to ADC instance: ADC3 */ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) { @@ -3222,7 +3233,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_19 * @retval None */ -__STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) if (ADCx != ADC3) @@ -3236,6 +3247,55 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C #endif /* ADC_VER_V5_V90 */ } +/** + * @brief Gets ADC pre-selected Channel. + * @note This function gets the pre-selected ADC channel. + * @note Caution: Channel selections is dependent to ADC instance and IP version: + * For STM32H72x/3x This is applicable only for ADC1/ADC2 + * For Rest of STM32H7xxx This is applicable on all the ADCs instances. + * + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_19 + * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected) + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) +{ +#if defined(ADC_VER_V5_V90) + if (ADCx != ADC3) + { + /* Gets preselected ADC channel */ + return (uint32_t)(READ_BIT(ADCx->PCSEL_RES0, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL))); + } + else + { + return 0UL; + } +#else + /* Gets preselected ADC channel */ + return (uint32_t)(READ_BIT(ADCx->PCSEL, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL))); +#endif /* ADC_VER_V5_V90 */ +} + /** * @brief Set ADC selected offset number 1, 2, 3 or 4. * @note This function set the 2 items of offset configuration: @@ -3245,8 +3305,8 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C * - Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. + * offset has to be left-aligned on bit 15 (handling maximum ADC resolution 16 bit), + * the LSB (right bits) are set to 0. * @note This function enables the offset, by default. It can be forced * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset @@ -3306,7 +3366,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). * Other channels are slow channels (conversion rate: refer to reference manual). - * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel) @@ -3403,8 +3463,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * Offset level (offset to be subtracted from the raw * converted data). * @note Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. + * offset has to be left-aligned on bit 15 (handling maximum ADC resolution 16 bit), + * the LSB (right bits) are set to 0. * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n @@ -3415,7 +3475,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_2 * @arg @ref LL_ADC_OFFSET_3 * @arg @ref LL_ADC_OFFSET_4 - * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF + * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) { @@ -5510,7 +5570,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha MODIFY_REG(ADCx->DIFSEL, Channel & ADC_SINGLEDIFF_CHANNEL_MASK, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK))); -#endif +#endif /* ADC_VER_V5_V90 */ } /** @@ -5562,7 +5622,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); #else return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); -#endif +#endif /* ADC_VER_V5_V90 */ } /** @@ -6032,7 +6092,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ + (AWDThresholdsHighLow)); return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT)); -#endif +#endif /* ADC_VER_V5_V90 */ } #if defined(ADC_VER_V5_V90) @@ -6302,6 +6362,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift * @param ADCx ADC instance * @param Ratio This parameter can be in the range from 1 to 1024. + * In the case of ADC3 can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 * @param Shift This parameter can be one of the following values: * @arg @ref LL_ADC_OVS_SHIFT_NONE * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 @@ -6319,7 +6388,20 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) { +#if defined(ADC_VER_V5_V90) + if(ADCx==ADC3) + { + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC3_CFGR2_OVSR), (Shift | Ratio)); + } + else + { + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos)))); + } +#else + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos)))); + +#endif /* ADC_VER_V5_V90 */ } /** @@ -6328,10 +6410,32 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio * @param ADCx ADC instance * @retval Ratio This parameter can be in the from 1 to 1024. + * In the case of ADC3 can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) { +#if defined(ADC_VER_V5_V90) + if(ADCx==ADC3) + { + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC3_CFGR2_OVSR)); + } + else + { + return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos); + } +#else + return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos); + +#endif /* ADC_VER_V5_V90 */ } /** @@ -6397,7 +6501,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) { MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST)); } -#endif +#endif /* ADC_VER_V5_V90 */ } @@ -7416,6 +7520,17 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } +/** + * @brief Get flag ADC LDO output voltage ready bit. + * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + /** * @brief Get flag ADC analog watchdog 1 flag * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h index 996eb750ed..fd48624af4 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bdma.h @@ -61,10 +61,15 @@ static const uint8_t LL_BDMA_CH_OFFSET_TAB[] = /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @defgroup BDMA_LL_Private_Macros BDMA Private Macros + * @{ + */ #if !defined(UNUSED) #define UNUSED(x) ((void)(x)) #endif - +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure @@ -337,6 +342,9 @@ typedef struct * @} */ +/** + * @} + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros * @{ @@ -2434,14 +2442,6 @@ void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h index 44637a187f..3a57e61e20 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_bus.h @@ -245,7 +245,7 @@ extern "C" { #define LL_APB3_GRP1_PERIPH_WWDG1 RCC_APB3ENR_WWDG1EN #if defined(RCC_APB3ENR_WWDGEN) #define LL_APB3_GRP1_PERIPH_WWDG LL_APB3_GRP1_PERIPH_WWDG1 /* for backward compatibility*/ -#endif +#endif /* RCC_APB3ENR_WWDGEN */ /** * @} */ @@ -534,7 +534,7 @@ extern "C" { * AHB3ENR IOMNGREN LL_AHB3_GRP1_EnableClock\n (*) * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_EnableClock\n (*) * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_EnableClock\n (*) - * AHB3ENR GFXMMU LL_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_EnableClock\n (*) * AHB3ENR SDMMC1EN LL_AHB3_GRP1_EnableClock\n * AHB3ENR FLASHEN LL_AHB3_GRP1_EnableClock\n (*) * AHB3ENR DTCM1EN LL_AHB3_GRP1_EnableClock\n (*) @@ -584,7 +584,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) * AHB3ENR IOMNGREN LL_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_IsEnabledClock\n (*) - * AHB3ENR GFXMMU LL_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR SDMMC1EN LL_AHB3_GRP1_IsEnabledClock\n * AHB3ENR FLASHEN LL_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR DTCM1EN LL_AHB3_GRP1_IsEnabledClock\n (*) @@ -615,7 +615,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -630,7 +630,7 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * AHB3ENR IOMNGREN LL_AHB3_GRP1_DisableClock\n (*) * AHB3ENR OTFDEC1EN LL_AHB3_GRP1_DisableClock\n (*) * AHB3ENR OTFDEC2EN LL_AHB3_GRP1_DisableClock\n (*) - * AHB3ENR GFXMMU LL_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_AHB3_GRP1_DisableClock\n (*) * AHB3ENR SDMMC1EN LL_AHB3_GRP1_DisableClock\n (*) * AHB3ENR FLASHEN LL_AHB3_GRP1_DisableClock\n (*) * AHB3ENR DTCM1EN LL_AHB3_GRP1_DisableClock\n (*) @@ -911,7 +911,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -1163,7 +1163,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n (*) * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset (*) + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ForceReset\n (*) * AHB2RSTR FMACRST LL_AHB2_GRP1_ForceReset\n * AHB2RSTR CORDICRST LL_AHB2_GRP1_ForceReset * @param Periphs This parameter can be a combination of the following values: @@ -1240,7 +1240,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n (*) * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset (*) + * AHB2RSTR BDMA1RST LL_AHB2_GRP1_ReleaseReset\n (*) * AHB2RSTR FMACRST LL_AHB2_GRP1_ReleaseReset\n * AHB2RSTR CORDICRST LL_AHB2_GRP1_ReleaseReset * @param Periphs This parameter can be a combination of the following values: @@ -1433,7 +1433,7 @@ __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -1699,7 +1699,7 @@ __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -1929,7 +1929,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -2301,7 +2301,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -2529,7 +2529,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -2859,7 +2859,7 @@ __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -3210,8 +3210,49 @@ __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs) /** * @brief Enable clock gating for AXI bus peripherals. - * @rmtoll - * @param : + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG * @retval None */ __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) @@ -3229,8 +3270,49 @@ __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs) /** * @brief Disable clock gating for AXI bus peripherals. - * @rmtoll - * @param : + * @rmtoll CKGAENR AXICKG LL_CKGA_Enable\n + * CKGAENR AHBCKG LL_CKGA_Enable\n + * CKGAENR CPUCKG LL_CKGA_Enable\n + * CKGAENR SDMMCCKG LL_CKGA_Enable\n + * CKGAENR MDMACKG LL_CKGA_Enable\n + * CKGAENR DMA2DCKG LL_CKGA_Enable\n + * CKGAENR LTDCCKG LL_CKGA_Enable\n + * CKGAENR GFXMMUMCKG LL_CKGA_Enable\n + * CKGAENR AHB12CKG LL_CKGA_Enable\n + * CKGAENR AHB34CKG LL_CKGA_Enable\n + * CKGAENR FLIFTCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI2CKG LL_CKGA_Enable\n + * CKGAENR FMCCKG LL_CKGA_Enable\n + * CKGAENR OCTOSPI1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM1CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM2CKG LL_CKGA_Enable\n + * CKGAENR AXIRAM3CKG LL_CKGA_Enable\n + * CKGAENR GFXMMUSCKG LL_CKGA_Enable\n + * CKGAENR ECCRAMCKG LL_CKGA_Enable\n + * CKGAENR EXTICKG LL_CKGA_Enable\n + * CKGAENR JTAGCKG LL_CKGA_Enable + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_CKGA_PERIPH_AXI + * @arg @ref LL_CKGA_PERIPH_AHB + * @arg @ref LL_CKGA_PERIPH_CPU + * @arg @ref LL_CKGA_PERIPH_SDMMC + * @arg @ref LL_CKGA_PERIPH_MDMA + * @arg @ref LL_CKGA_PERIPH_DMA2D + * @arg @ref LL_CKGA_PERIPH_LTDC + * @arg @ref LL_CKGA_PERIPH_GFXMMUM + * @arg @ref LL_CKGA_PERIPH_AHB12 + * @arg @ref LL_CKGA_PERIPH_AHB34 + * @arg @ref LL_CKGA_PERIPH_FLIFT + * @arg @ref LL_CKGA_PERIPH_OCTOSPI2 + * @arg @ref LL_CKGA_PERIPH_FMC + * @arg @ref LL_CKGA_PERIPH_OCTOSPI1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM1 + * @arg @ref LL_CKGA_PERIPH_AXIRAM2 + * @arg @ref LL_CKGA_PERIPH_AXIRAM3 + * @arg @ref LL_CKGA_PERIPH_GFXMMUS + * @arg @ref LL_CKGA_PERIPH_ECCRAM + * @arg @ref LL_CKGA_PERIPH_EXTI + * @arg @ref LL_CKGA_PERIPH_JTAG * @retval None */ __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) @@ -3261,7 +3343,7 @@ __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs) * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_EnableClock\n (*) * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_EnableClock\n (*) * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_EnableClock\n (*) - * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_EnableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_EnableClock\n (*) * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_EnableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA @@ -3301,7 +3383,7 @@ __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) - * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_IsEnabledClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_IsEnabledClock\n (*) * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_IsEnabledClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA @@ -3322,7 +3404,7 @@ __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -3337,7 +3419,7 @@ __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * AHB3ENR IOMNGREN LL_C1_AHB3_GRP1_DisableClock\n (*) * AHB3ENR OTFDEC1EN LL_C1_AHB3_GRP1_DisableClock\n (*) * AHB3ENR OTFDEC2EN LL_C1_AHB3_GRP1_DisableClock\n (*) - * AHB3ENR GFXMMU LL_C1_AHB3_GRP1_DisableClock\n (*) + * AHB3ENR GFXMMUEN LL_C1_AHB3_GRP1_DisableClock\n (*) * AHB3ENR SDMMC1EN LL_C1_AHB3_GRP1_DisableClock * @param Periphs This parameter can be a combination of the following values: * @arg @ref LL_AHB3_GRP1_PERIPH_MDMA @@ -3536,7 +3618,7 @@ __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -3724,7 +3806,7 @@ __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -3924,7 +4006,7 @@ __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -4106,7 +4188,7 @@ __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -4301,7 +4383,7 @@ __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -4543,7 +4625,7 @@ __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -4723,7 +4805,7 @@ __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -4957,7 +5039,7 @@ __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -5157,7 +5239,7 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -5335,7 +5417,7 @@ __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -5497,7 +5579,7 @@ __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -5683,7 +5765,7 @@ __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -5865,7 +5947,7 @@ __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -6059,7 +6141,7 @@ __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -6301,7 +6383,7 @@ __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -6474,7 +6556,7 @@ __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U); } /** @@ -6688,7 +6770,7 @@ __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs) */ __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs) { - return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U); + return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U); } /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h index 61b8e9b496..4fce9ae9a1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_comp.h @@ -52,6 +52,12 @@ extern "C" { */ /* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_LL_Private_Macros COMP Private Macros + * @{ + */ +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h index b798e7bf0b..fe1f6f9efc 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cordic.h @@ -347,7 +347,7 @@ __STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Fun * @arg @ref LL_CORDIC_FUNCTION_NATURALLOG * @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT */ -__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC)); } @@ -400,7 +400,7 @@ __STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Pr * @arg @ref LL_CORDIC_PRECISION_14CYCLES * @arg @ref LL_CORDIC_PRECISION_15CYCLES */ -__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION)); } @@ -439,7 +439,7 @@ __STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale) * @arg @ref LL_CORDIC_SCALE_6 * @arg @ref LL_CORDIC_SCALE_7 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE)); } @@ -466,7 +466,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWr * @arg @ref LL_CORDIC_NBWRITE_1 * @arg @ref LL_CORDIC_NBWRITE_2 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS)); } @@ -493,7 +493,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRea * @arg @ref LL_CORDIC_NBREAD_1 * @arg @ref LL_CORDIC_NBREAD_2 */ -__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES)); } @@ -520,7 +520,7 @@ __STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSiz * @arg @ref LL_CORDIC_INSIZE_32BITS * @arg @ref LL_CORDIC_INSIZE_16BITS */ -__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE)); } @@ -547,7 +547,7 @@ __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutS * @arg @ref LL_CORDIC_OUTSIZE_32BITS * @arg @ref LL_CORDIC_OUTSIZE_16BITS */ -__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE)); } @@ -588,7 +588,7 @@ __STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U); } @@ -629,7 +629,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U); } @@ -662,7 +662,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx) * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U); } @@ -677,7 +677,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx) * @arg @ref LL_CORDIC_DMA_REG_DATA_OUT * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *CORDICx, uint32_t Direction) { uint32_t data_reg_addr; @@ -709,7 +709,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint3 * @param CORDICx CORDIC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *CORDICx) { return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U); } @@ -740,7 +740,7 @@ __STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InDat * @param CORDICx CORDIC Instance * @retval 32-bit output data of CORDIC processing. */ -__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx) +__STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) { return (uint32_t)(READ_REG(CORDICx->RDATA)); } @@ -755,7 +755,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx); +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h index 4917f65154..2b63e8f33d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_cortex.h @@ -174,6 +174,8 @@ extern "C" { #define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ #define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ #define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ + +/* Legacy Define */ #define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ /** * @} @@ -592,7 +594,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO - * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h index 0c2c3998a2..c214f7808d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h @@ -58,8 +58,12 @@ * @} */ +/** @addtogroup DelayBlock_LL_Exported_Functions + * @{ + */ + /* Peripheral Control functions ************************************************/ -/** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions +/** @addtogroup HAL_DELAY_LL_Group1 * @{ */ HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx); @@ -70,6 +74,9 @@ HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, u * @} */ +/** + * @} + */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h index 4d18318bd5..100a2c55de 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h @@ -62,7 +62,9 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] = */ /* Private macros ------------------------------------------------------------*/ - +/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros + * @{ + */ /** * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. @@ -72,6 +74,9 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] = */ #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) +/** + * @} + */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) @@ -3133,7 +3138,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) } /** - * @brief Check if Half transfer interrup is enabled. + * @brief Check if Half transfer interrupt is enabled. * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -3177,7 +3182,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea } /** - * @brief Check if Transfer complete interrup is enabled. + * @brief Check if Transfer complete interrupt is enabled. * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -3221,7 +3226,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre } /** - * @brief Check if FIFO error interrup is enabled. + * @brief Check if FIFO error interrupt is enabled. * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h index b489388dbb..63253aed04 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_fmac.h @@ -48,11 +48,12 @@ extern "C" { * @brief Flag defines which can be used with LL_FMAC_ReadReg function * @{ */ -#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */ -#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ -#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ -#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ -#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ +#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag + (this helps in debugging a filter) */ +#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */ +#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */ +#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */ +#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */ /** * @} */ @@ -61,11 +62,12 @@ extern "C" { * @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions * @{ */ -#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */ -#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ -#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ -#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ -#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ +#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable + (this helps in debugging a filter) */ +#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */ +#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */ +#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */ +#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */ /** * @} */ @@ -74,10 +76,14 @@ extern "C" { * @brief Watermark defines that can be used for buffer full (input) or buffer empty (output) * @{ */ -#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */ -#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */ -#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */ -#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */ +#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there + is less than 1 free/unread space. */ +#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there + are less than 2 free/unread spaces. */ +#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there + are less than 4 free/unread spaces. */ +#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there + are less than 8 free/empty spaces. */ /** * @} */ @@ -85,11 +91,11 @@ extern "C" { /** @defgroup FMAC_LL_EC_FUNC FMAC functions * @{ */ -#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ -#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ -#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ -#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ -#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ +#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */ +#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */ +#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */ +#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */ +#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */ /** * @} */ @@ -97,8 +103,8 @@ extern "C" { /** @defgroup FMAC_LL_EC_PROCESSING FMAC processing * @{ */ -#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ -#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ +#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */ +#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h index f037e4f301..d3f3608fe1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hrtim.h @@ -1439,7 +1439,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncI * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT */ -__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN)); } @@ -1490,7 +1490,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t S * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE */ -__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT)); } @@ -1521,7 +1521,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t Sync * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 */ -__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC)); } @@ -1711,7 +1711,7 @@ __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outp * @arg @ref LL_HRTIM_OUTPUT_TE2 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL); } @@ -1742,7 +1742,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_OUTPUT_TE2 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL); } @@ -2027,7 +2027,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E */ -__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) +__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const uint32_t shift = ((3U * ADCTrig) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift); @@ -2461,7 +2461,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST */ -__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) +__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + REG_OFFSET_TAB_ADCxR[ADCTrig])); @@ -2542,7 +2542,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL); } @@ -2591,7 +2591,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2644,7 +2644,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_MODE_SINGLESHOT * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2710,7 +2710,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_E * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2773,7 +2773,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_TIMER_E * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2837,7 +2837,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2889,7 +2889,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -2955,7 +2955,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3040,7 +3040,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION * @arg @ref LL_HRTIM_UPDATETRIG_RESET */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3115,7 +3115,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); @@ -3174,7 +3174,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_TIMER_E * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + @@ -3234,7 +3234,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + @@ -3286,7 +3286,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval Counter Value between 0 and 0xFFFF */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + @@ -3331,7 +3331,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval Period Value between 0 and 0xFFFF */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + @@ -3376,7 +3376,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval Repetition Value between 0 and 0xFF */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + @@ -3425,7 +3425,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + @@ -3474,7 +3474,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + @@ -3523,7 +3523,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + @@ -3572,7 +3572,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + @@ -3739,7 +3739,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + @@ -3759,7 +3759,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_TIMER_E * @retval Captured value */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + @@ -3779,7 +3779,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_E * @retval Captured value */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + @@ -3953,7 +3953,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + @@ -4013,7 +4013,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_TIMER_E * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -4099,7 +4099,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -4161,7 +4161,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -4251,7 +4251,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_FAULT_5 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + @@ -4329,7 +4329,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); @@ -4438,7 +4438,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -4460,7 +4460,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2 */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -4576,7 +4576,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); @@ -4665,7 +4665,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_EELATCH_DISABLED * @arg @ref LL_HRTIM_EELATCH_ENABLED */ -__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); @@ -4757,7 +4757,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -4798,7 +4798,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval RisingValue Value between 0 and 0x1FF */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -4843,7 +4843,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_DT_RISING_POSITIVE * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -4884,7 +4884,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval FallingValue Value between 0 and 0x1FF */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -4929,7 +4929,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -4949,7 +4949,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_TIMER_E * @retval None */ -__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + @@ -5121,7 +5121,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + @@ -5181,7 +5181,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 */ -__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + @@ -5256,7 +5256,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 */ -__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + @@ -5505,7 +5505,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + @@ -5746,7 +5746,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + @@ -5847,7 +5847,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -5905,7 +5905,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou * @arg @ref LL_HRTIM_OUT_NO_IDLE * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -5964,7 +5964,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -6027,7 +6027,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -6085,7 +6085,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -6143,7 +6143,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + @@ -6172,7 +6172,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + @@ -6238,7 +6238,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE */ -__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) +__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output) { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + @@ -6397,7 +6397,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u * @arg External event source 3 * @arg External event source 4 */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -6472,7 +6472,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve * @arg @ref LL_HRTIM_EE_POLARITY_HIGH * @arg @ref LL_HRTIM_EE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -6550,7 +6550,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -6614,7 +6614,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + @@ -6694,7 +6694,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event * @arg @ref LL_HRTIM_EE_FILTER_14 * @arg @ref LL_HRTIM_EE_FILTER_15 */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event) { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); return (READ_BIT(HRTIMx->sCommonRegs.EECR3, @@ -6729,7 +6729,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Pr * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8 */ -__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD)); } @@ -6821,7 +6821,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + @@ -6875,7 +6875,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa * @arg @ref LL_HRTIM_FLT_POLARITY_LOW * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + @@ -6957,7 +6957,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul * @arg @ref LL_HRTIM_FLT_FILTER_14 * @arg @ref LL_HRTIM_FLT_FILTER_15 */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + @@ -6992,7 +6992,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t P * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8 */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD)); } @@ -7085,7 +7085,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) * @arg @ref LL_HRTIM_FAULT_5 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) +__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + @@ -7141,7 +7141,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode) * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM); } @@ -7195,7 +7195,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t Clo * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK); } @@ -7250,7 +7250,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Pr * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768 */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC); } @@ -7283,7 +7283,7 @@ __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx) { uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); @@ -7435,7 +7435,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig) * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR); } @@ -7462,7 +7462,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t Comp * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR); } @@ -7489,7 +7489,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Perio * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... * The maximum value is 0x0000 FFDF. */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx) { return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER); } @@ -7522,7 +7522,7 @@ __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BME bit in HRTIM_BMCR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL); } @@ -7558,7 +7558,7 @@ __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx) * @arg @ref LL_HRTIM_BM_STATUS_NORMAL * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING */ -__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx) { return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT)); } @@ -7588,7 +7588,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL); } @@ -7610,7 +7610,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL); } @@ -7632,7 +7632,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL); } @@ -7654,7 +7654,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL); } @@ -7676,7 +7676,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL); } @@ -7698,7 +7698,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL); } @@ -7720,7 +7720,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BMPER bit in HRTIM_ISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL); } @@ -7742,7 +7742,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYNC bit in HRTIM_MISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL); } @@ -7783,7 +7783,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -7829,7 +7829,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -7874,7 +7874,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -7919,7 +7919,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -7964,7 +7964,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8009,7 +8009,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8050,7 +8050,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8091,7 +8091,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8132,7 +8132,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8173,7 +8173,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8214,7 +8214,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8255,7 +8255,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8296,7 +8296,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8337,7 +8337,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + @@ -8382,7 +8382,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -8415,7 +8415,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL); } @@ -8448,7 +8448,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL); } @@ -8481,7 +8481,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL); } @@ -8514,7 +8514,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL); } @@ -8547,7 +8547,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL); } @@ -8580,7 +8580,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL); } @@ -8613,7 +8613,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL); } @@ -8676,7 +8676,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -8743,7 +8743,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -8810,7 +8810,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -8877,7 +8877,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -8944,7 +8944,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9011,7 +9011,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9072,7 +9072,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9133,7 +9133,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9194,7 +9194,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9255,7 +9255,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9316,7 +9316,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9377,7 +9377,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim * @arg @ref LL_HRTIM_TIMER_E * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9438,7 +9438,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time * @arg @ref LL_HRTIM_TIMER_E * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9499,7 +9499,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T * @arg @ref LL_HRTIM_TIMER_E * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9544,7 +9544,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) * @param HRTIMx High Resolution Timer instance * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx) { return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL); } @@ -9607,7 +9607,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_TIMER_E * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9674,7 +9674,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9741,7 +9741,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9808,7 +9808,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9875,7 +9875,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -9942,7 +9942,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10003,7 +10003,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10064,7 +10064,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10125,7 +10125,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10186,7 +10186,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10247,7 +10247,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10308,7 +10308,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10369,7 +10369,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t * @arg @ref LL_HRTIM_TIMER_E * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + @@ -10430,7 +10430,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_TIMER_E * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0). */ -__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) +__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer) { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h index 39ba9807fb..fd120b64de 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lptim.h @@ -339,6 +339,19 @@ typedef struct * @{ */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions * @{ @@ -346,7 +359,7 @@ typedef struct ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} @@ -376,7 +389,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -418,7 +431,7 @@ __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) { CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); } @@ -429,7 +442,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *const LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); } @@ -472,7 +485,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -501,7 +514,7 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @param LPTIMx Low-Power Timer instance * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -528,7 +541,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); } @@ -543,7 +556,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -571,7 +584,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *const LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -620,7 +633,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -647,7 +660,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); } @@ -691,7 +704,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -773,7 +786,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -866,7 +879,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * (*) Value not defined in all devices. \n * */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -881,7 +894,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -895,7 +908,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -931,7 +944,7 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } @@ -973,7 +986,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -988,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -1026,7 +1039,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -1065,7 +1078,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -1078,13 +1091,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) * @{ */ + /** * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM + * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); } @@ -1095,18 +1109,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } /** * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval None */ -__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) { SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); } @@ -1117,7 +1131,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1139,7 +1153,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1162,7 +1176,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } @@ -1185,7 +1199,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1208,7 +1222,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1231,7 +1245,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1272,7 +1286,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } @@ -1305,7 +1319,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } @@ -1338,7 +1352,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -1371,7 +1385,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } @@ -1404,7 +1418,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } @@ -1437,7 +1451,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } @@ -1470,7 +1484,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h index 3fef9da74d..fe66becb5b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_lpuart.h @@ -522,7 +522,7 @@ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -555,7 +555,7 @@ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -590,7 +590,7 @@ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -625,7 +625,7 @@ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -767,7 +767,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint * @arg @ref LL_LPUART_DIRECTION_TX * @arg @ref LL_LPUART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -801,7 +801,7 @@ __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity * @arg @ref LL_LPUART_PARITY_EVEN * @arg @ref LL_LPUART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -828,7 +828,7 @@ __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t * @arg @ref LL_LPUART_WAKEUP_IDLELINE * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); } @@ -857,7 +857,7 @@ __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t Dat * @arg @ref LL_LPUART_DATAWIDTH_8B * @arg @ref LL_LPUART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); } @@ -890,7 +890,7 @@ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -937,7 +937,7 @@ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t Pre * @arg @ref LL_LPUART_PRESCALER_DIV128 * @arg @ref LL_LPUART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -964,7 +964,7 @@ __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_ * @arg @ref LL_LPUART_STOPBITS_1 * @arg @ref LL_LPUART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); } @@ -1022,7 +1022,7 @@ __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t Swap * @arg @ref LL_LPUART_TXRX_STANDARD * @arg @ref LL_LPUART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); } @@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); } @@ -1076,7 +1076,7 @@ __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); } @@ -1106,7 +1106,7 @@ __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); } @@ -1137,7 +1137,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_BITORDER_LSBFIRST * @arg @ref LL_LPUART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1181,7 +1181,7 @@ __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_ * @param LPUARTx LPUART Instance * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1194,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) * @arg @ref LL_LPUART_ADDRESS_DETECT_4B * @arg @ref LL_LPUART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); } @@ -1271,7 +1271,7 @@ __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t Ha * @arg @ref LL_LPUART_HWCONTROL_CTS * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1304,7 +1304,7 @@ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1333,7 +1333,7 @@ __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT * @arg @ref LL_LPUART_WAKEUP_ON_RXNE */ -__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); } @@ -1398,7 +1398,8 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri * @arg @ref LL_LPUART_PRESCALER_DIV256 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) { uint32_t lpuartdiv; uint32_t brrresult; @@ -1454,7 +1455,7 @@ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -1485,7 +1486,7 @@ __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : c */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -1508,7 +1509,7 @@ __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -1541,7 +1542,7 @@ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -1568,7 +1569,7 @@ __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint3 * @arg @ref LL_LPUART_DE_POLARITY_HIGH * @arg @ref LL_LPUART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) { return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); } @@ -1587,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -1598,7 +1599,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -1609,7 +1610,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -1620,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -1631,13 +1632,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not @@ -1645,7 +1645,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -1656,13 +1656,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUART * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not @@ -1670,7 +1669,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -1681,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -1692,7 +1691,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -1703,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -1714,7 +1713,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -1725,7 +1724,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -1736,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -1747,7 +1746,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } @@ -1758,7 +1757,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -1769,7 +1768,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -1780,7 +1779,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -1791,7 +1790,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -1802,7 +1801,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -1813,7 +1812,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -1936,8 +1935,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -1961,8 +1959,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -2089,8 +2086,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -2114,8 +2110,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -2237,13 +2232,12 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -2251,7 +2245,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -2262,13 +2256,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled @@ -2276,7 +2269,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -2287,7 +2280,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -2298,7 +2291,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -2309,7 +2302,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -2320,7 +2313,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -2331,7 +2324,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -2342,7 +2335,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -2353,7 +2346,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } @@ -2364,7 +2357,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -2375,7 +2368,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -2416,7 +2409,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -2449,7 +2442,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -2482,7 +2475,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) { return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -2497,7 +2490,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -2529,7 +2522,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) { return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -2540,7 +2533,7 @@ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) * @param LPUARTx LPUART Instance * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) { return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); } @@ -2620,8 +2613,8 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx); -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct); +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h index 7c7e207dbc..bd700dc2b8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h @@ -49,6 +49,9 @@ extern const uint8_t LL_RCC_PrescTable[16]; */ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ #if !defined(UNUSED) #define UNUSED(x) ((void)(x)) #endif @@ -90,15 +93,9 @@ extern const uint8_t LL_RCC_PrescTable[16]; (( __POS__ ) << LL_RCC_POS_SHIFT) | \ (( __REG__ ) << LL_RCC_REG_SHIFT) | \ (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ /** * @} */ -#endif /*USE_FULL_LL_DRIVER*/ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Exported_Types RCC Exported Types @@ -1688,7 +1685,7 @@ __STATIC_INLINE void LL_RCC_HSE_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); } /** @@ -1726,7 +1723,7 @@ __STATIC_INLINE void LL_RCC_HSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); } /** @@ -1736,7 +1733,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL); } /** @@ -1823,7 +1820,7 @@ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); } #else - MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); + MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos); #endif /* RCC_VER_X */ } @@ -1846,7 +1843,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); } #else - return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); #endif /* RCC_VER_X */ } @@ -1885,7 +1882,7 @@ __STATIC_INLINE void LL_RCC_CSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL); } /** @@ -1929,7 +1926,7 @@ __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void) return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); } #else - return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos); #endif /* RCC_VER_X */ } @@ -1956,7 +1953,7 @@ __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value) MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); } #else - MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); + MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos); #endif /* RCC_VER_X */ } @@ -1979,7 +1976,7 @@ __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void) return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); } #else - return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); #endif /* RCC_VER_X */ } @@ -2018,7 +2015,7 @@ __STATIC_INLINE void LL_RCC_HSI48_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL); } /** @@ -2049,7 +2046,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) */ __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL); } /** @@ -2068,9 +2065,9 @@ __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL); } - /* alias */ +/* alias */ #define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady /** * @} @@ -2090,7 +2087,7 @@ __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL); } /** * @} @@ -2108,7 +2105,7 @@ __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL); } #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady /** @@ -2138,7 +2135,7 @@ __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void) */ __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void) { - return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL); + return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL); } #endif /* RCC_GCR_WW1RSC */ @@ -2160,7 +2157,7 @@ __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void) */ __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void) { - return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL); + return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL); } #endif /*DUAL_CORE*/ /** @@ -2189,7 +2186,7 @@ __STATIC_INLINE void LL_RCC_ForceCM4Boot(void) */ __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void) { - return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL); + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL); } /** @@ -2209,7 +2206,7 @@ __STATIC_INLINE void LL_RCC_ForceCM7Boot(void) */ __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void) { - return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL); + return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL); } /** @@ -2240,7 +2237,7 @@ __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void) { - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); } /** @@ -2346,7 +2343,7 @@ __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) */ __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) { - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); } /** @@ -2384,7 +2381,7 @@ __STATIC_INLINE void LL_RCC_LSI_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) { - return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL); + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); } /** @@ -2785,7 +2782,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void) */ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) { - MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); + MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U)); } /** @@ -2898,9 +2895,9 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource) { #if defined(RCC_D1CCIPR_FMCSEL) - uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource)); + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource)); #else - uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource)); + uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource)); #endif /* */ MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource)); } @@ -3149,9 +3146,9 @@ __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource) __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource) { #if defined(RCC_D2CCIP1R_DFSDM1SEL) - MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource); + MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource); #else - MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource); + MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource); #endif /* RCC_D2CCIP1R_DFSDM1SEL */ } @@ -3166,7 +3163,7 @@ __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource) */ __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource) { - MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource); + MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource); } #endif /* DFSDM2_BASE */ @@ -3473,7 +3470,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) #else const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph))); #endif /* RCC_D1CCIPR_FMCSEL */ - return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) ); + return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT)); } /** @@ -4036,7 +4033,7 @@ __STATIC_INLINE void LL_RCC_DisableRTC(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) { - return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL); + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); } /** @@ -4345,7 +4342,7 @@ __STATIC_INLINE void LL_RCC_PLL1_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL); } /** @@ -4398,7 +4395,7 @@ __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL); } /** @@ -4408,7 +4405,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL); } /** @@ -4418,7 +4415,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL); } /** @@ -4428,7 +4425,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL); } /** @@ -4572,7 +4569,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) */ __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N) { - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos); } /** @@ -4596,7 +4593,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) */ __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) { - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos); } /** @@ -4607,7 +4604,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) */ __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) { - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos); } /** @@ -4618,7 +4615,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q) */ __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R) { - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos); } /** @@ -4659,7 +4656,7 @@ __STATIC_INLINE void LL_RCC_PLL2_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL); } /** @@ -4712,7 +4709,7 @@ __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL); } /** @@ -4722,7 +4719,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL); } /** @@ -4732,7 +4729,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL); } /** @@ -4742,7 +4739,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL); } /** @@ -4886,7 +4883,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) */ __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N) { - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos); } /** @@ -4908,7 +4905,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M) */ __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) { - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos); } /** @@ -4919,7 +4916,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P) */ __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) { - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos); } /** @@ -4930,7 +4927,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q) */ __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R) { - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos); + MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos); } /** @@ -4971,7 +4968,7 @@ __STATIC_INLINE void LL_RCC_PLL3_Disable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) { - return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL); + return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL); } /** @@ -5024,7 +5021,7 @@ __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL); } /** @@ -5034,7 +5031,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL); } /** @@ -5044,7 +5041,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL); } /** @@ -5054,7 +5051,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) { - return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL); + return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL); } /** @@ -5198,7 +5195,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) */ __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N) { - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos); } /** @@ -5220,7 +5217,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M) */ __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) { - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos); } /** @@ -5231,7 +5228,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P) */ __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) { - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos); } /** @@ -5242,7 +5239,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q) */ __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R) { - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos); + MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos); } /** @@ -5382,7 +5379,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); } /** @@ -5392,7 +5389,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); } /** @@ -5402,7 +5399,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); } /** @@ -5412,7 +5409,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); } /** @@ -5422,7 +5419,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL); } /** @@ -5432,7 +5429,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL); } /** @@ -5442,7 +5439,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); } /** @@ -5452,7 +5449,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL); } /** @@ -5462,7 +5459,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL); } /** @@ -5472,7 +5469,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); } /** @@ -5482,7 +5479,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) { - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL); + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL); } /** @@ -5497,9 +5494,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) { #if defined(DUAL_CORE) - return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); #else - return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL); #endif /*DUAL_CORE*/ } @@ -5511,7 +5508,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); } #endif /*DUAL_CORE*/ @@ -5522,7 +5519,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); } #if defined(DUAL_CORE) @@ -5533,7 +5530,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); } #endif /*DUAL_CORE*/ @@ -5544,7 +5541,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); } #if defined(DUAL_CORE) @@ -5555,7 +5552,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); } #endif /*DUAL_CORE*/ @@ -5571,9 +5568,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void) __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) { #if defined(DUAL_CORE) - return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); #else - return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL); #endif /*DUAL_CORE*/ } @@ -5585,7 +5582,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); } #endif /*DUAL_CORE*/ @@ -5596,7 +5593,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); } /** @@ -5606,7 +5603,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); } /** @@ -5616,7 +5613,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); } #if defined(RCC_RSR_D1RSTF) @@ -5627,7 +5624,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); } #endif /* RCC_RSR_D1RSTF */ @@ -5639,7 +5636,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL); } #endif /* RCC_RSR_CDRSTF */ @@ -5651,7 +5648,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); } #endif /* RCC_RSR_D2RSTF */ @@ -5668,9 +5665,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void) __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void) { #if defined(DUAL_CORE) - return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); #else - return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL); #endif/*DUAL_CORE*/ } #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */ @@ -5683,7 +5680,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void) */ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void) { - return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL); + return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); } #endif /*DUAL_CORE*/ @@ -5705,7 +5702,7 @@ __STATIC_INLINE void LL_RCC_ClearResetFlags(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); } /** @@ -5715,7 +5712,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); } /** @@ -5725,7 +5722,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); } /** @@ -5735,7 +5732,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); } /** @@ -5745,7 +5742,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); } /** @@ -5755,7 +5752,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); } /** @@ -5765,7 +5762,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); } /** @@ -5775,7 +5772,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); } /** @@ -5785,7 +5782,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); } /** @@ -5795,7 +5792,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); } /** @@ -5805,7 +5802,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); } /** @@ -5815,7 +5812,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); } /** @@ -5825,7 +5822,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); } /** @@ -5835,7 +5832,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); } /** @@ -5845,7 +5842,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void) */ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void) { - return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); } /** @@ -5865,7 +5862,7 @@ __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL); } /** @@ -5875,7 +5872,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL); } /** @@ -5885,7 +5882,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL); } /** @@ -5895,7 +5892,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL); } /** @@ -5905,7 +5902,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL); } /** @@ -5915,7 +5912,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL); } /** @@ -5925,7 +5922,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL); } /** @@ -5935,7 +5932,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL); } /** @@ -5945,7 +5942,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL); } /** @@ -5955,7 +5952,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL); } /** @@ -5965,7 +5962,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL); } /** @@ -5975,7 +5972,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL); } /** @@ -5985,7 +5982,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL); } /** @@ -5995,7 +5992,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL); } /** @@ -6005,7 +6002,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void) */ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void) { - return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL); + return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL); } /** @@ -6234,7 +6231,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); } /** @@ -6244,7 +6241,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); } /** @@ -6254,7 +6251,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); } /** @@ -6264,7 +6261,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); } /** @@ -6274,7 +6271,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL); } /** @@ -6284,7 +6281,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); } /** @@ -6294,7 +6291,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); } /** @@ -6304,7 +6301,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); } /** @@ -6314,7 +6311,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); } /** @@ -6324,7 +6321,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void) */ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void) { - return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL); + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); } /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h index 6863989bdd..760a127301 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rng.h @@ -38,6 +38,15 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RNG_LL_Private_Defines RNG Private Defines + * @{ + */ +/* Health test control register information to use in CCM algorithm */ +#define LL_RNG_HTCFG 0x17590ABCU /*!< Magic number */ +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -627,6 +636,9 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { + /*!< magic number must be written immediately before to RNG_HTCRG */ + WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG); + WRITE_REG(RNGx->HTCR, HTCFG); } @@ -638,6 +650,9 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) */ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) { + /*!< magic number must be written immediately before reading RNG_HTCRG */ + WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG); + return (uint32_t)READ_REG(RNGx->HTCR); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h index ff0477b46d..f1f673a0ea 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rtc.h @@ -234,24 +234,21 @@ typedef struct * @brief Flags defines which can be used with LL_RTC_ReadReg function * @{ */ -#if defined(RTC_SCR_CALRAF) +#if defined(TAMP) #define LL_RTC_SCR_ITSF RTC_SCR_CITSF #define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF #define LL_RTC_SCR_TSF RTC_SCR_CTSF #define LL_RTC_SCR_WUTF RTC_SCR_CWUTF #define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF #define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF -#endif /* RTC_SCR_CALRAF */ -#if defined(RTC_ICSR_ALRAWF) #define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF #define LL_RTC_ICSR_INITF RTC_ICSR_INITF #define LL_RTC_ICSR_RSF RTC_ICSR_RSF #define LL_RTC_ICSR_INITS RTC_ICSR_INITS #define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF #define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF -#endif /* RTC_ICSR_ALRAWF */ -#if defined(RTC_ISR_ALRAWF) +#else #define LL_RTC_ISR_ITSF RTC_ISR_ITSF #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF #define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F @@ -269,7 +266,7 @@ typedef struct #define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF #define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF #define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF -#endif /* RTC_ISR_ALRAWF */ +#endif /* TAMP */ /** * @} */ @@ -282,18 +279,12 @@ typedef struct #define LL_RTC_CR_WUTIE RTC_CR_WUTIE #define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE #define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE -#if defined(RTC_TAMPCR_TAMP3E) +#if !defined(TAMP) #define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE -#endif /* RTC_TAMPCR_TAMP3E */ -#if defined(RTC_TAMPCR_TAMP2E) #define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP1E) #define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMPIE) #define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE -#endif /* RTC_TAMPCR_TAMPIE */ +#endif /* !TAMP */ /** * @} */ @@ -354,14 +345,13 @@ typedef struct /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE * @{ */ -#if defined(RTC_CR_TAMPALRM_TYPE) +#if defined(TAMP) #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ -#endif /* RTC_CR_TAMPALRM_TYPE */ -#if defined(RTC_OR_ALARMOUTTYPE) +#else #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ -#endif /* RTC_OR_ALARMOUTTYPE */ +#endif /* TAMP */ /** * @} */ @@ -455,18 +445,13 @@ typedef struct * @} */ +#if defined(TAMP) /** @defgroup RTC_LL_EC_TAMPER TAMPER * @{ */ -#if defined(TAMP_CR1_TAMP1E) #define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) #define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ -#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -474,15 +459,9 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK * @{ */ -#if defined(TAMP_CR1_TAMP1E) #define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */ -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) #define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */ -#endif /* TAMP_CR1_TAMP3E */ /** * @} */ @@ -490,20 +469,13 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE * @{ */ -#if defined(TAMP_CR1_TAMP1E) #define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) #define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ -#endif /* TAMP_CR1_TAMP3E */ /** * @} */ -#if defined(TAMP_FLTCR_TAMPPRCH) /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ @@ -514,9 +486,7 @@ typedef struct /** * @} */ -#endif /* TAMP_FLTCR_TAMPPRCH */ -#if defined(TAMP_FLTCR_TAMPFLT) /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ @@ -527,9 +497,7 @@ typedef struct /** * @} */ -#endif /* TAMP_FLTCR_TAMPFLT */ -#if defined(TAMP_FLTCR_TAMPFREQ) /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ @@ -544,36 +512,23 @@ typedef struct /** * @} */ -#endif /* TAMP_FLTCR_TAMPFREQ */ /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL * @{ */ -#if defined(TAMP_CR1_TAMP1E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -#endif /* TAMP_CR1_TAMP3E */ /** * @} */ - +#else /** @defgroup RTC_LL_EC_TAMPER TAMPER * @{ */ -#if defined (RTC_TAMPCR_TAMP1E) #define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined (RTC_TAMPCR_TAMP2E) #define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined (RTC_TAMPCR_TAMP3E) #define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ -#endif /* RTC_TAMPCR_TAMP3E */ /** * @} */ @@ -581,15 +536,9 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK * @{ */ -#if defined (RTC_TAMPCR_TAMP1E) #define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined (RTC_TAMPCR_TAMP2E) #define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined (RTC_TAMPCR_TAMP3E) #define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */ -#endif /* RTC_TAMPCR_TAMP3E */ /** * @} */ @@ -597,20 +546,13 @@ typedef struct /** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE * @{ */ -#if defined (RTC_TAMPCR_TAMP1E) #define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined (RTC_TAMPCR_TAMP2E) #define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined (RTC_TAMPCR_TAMP3E) #define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ -#endif /* RTC_TAMPCR_TAMP3E */ /** * @} */ -#if defined(RTC_TAMPCR_TAMPPRCH) /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ @@ -621,9 +563,7 @@ typedef struct /** * @} */ -#endif /* RTC_TAMPCR_TAMPPRCH */ -#if defined(RTC_TAMPCR_TAMPFLT) /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ @@ -634,9 +574,7 @@ typedef struct /** * @} */ -#endif /* RTC_TAMPCR_TAMPFLT */ -#if defined(RTC_TAMPCR_TAMPFREQ) /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ @@ -651,41 +589,29 @@ typedef struct /** * @} */ -#endif /* RTC_TAMPCR_TAMPFREQ */ /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL * @{ */ -#if defined (RTC_TAMPCR_TAMP1E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined (RTC_TAMPCR_TAMP2E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined (RTC_TAMPCR_TAMP3E) #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ -#endif /* RTC_TAMPCR_TAMP3E */ /** * @} */ +#endif /* TAMP */ +#if defined(TAMP) /** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE * @{ */ -#if defined(TAMP_ATCR1_TAMP1AM) #define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */ -#endif /* TAMP_ATCR1_TAMP1AM */ -#if defined(TAMP_ATCR1_TAMP2AM) #define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */ -#endif /* TAMP_ATCR1_TAMP2AM */ -#if defined(TAMP_ATCR1_TAMP3AM) #define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */ -#endif /* TAMP_ATCR1_TAMP3AM */ /** * @} */ -#if defined(TAMP_ATCR1_ATCKSEL) /** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK * @{ */ @@ -700,31 +626,25 @@ typedef struct /** * @} */ -#endif /* TAMP_ATCR1_ATCKSEL */ /** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION * @{ */ -#if defined(TAMP_ATCR1_TAMP1AM) #define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL1_Pos) #define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL1_Pos) #define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL1_Pos) -#endif /* TAMP_ATCR1_TAMP1AM */ -#if defined(TAMP_ATCR1_TAMP2AM) #define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL2_Pos) #define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL2_Pos) #define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL2_Pos) -#endif /* TAMP_ATCR1_TAMP2AM */ -#if defined(TAMP_ATCR1_TAMP3AM) #define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0UL << TAMP_ATCR2_ATOSEL3_Pos) #define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1UL << TAMP_ATCR2_ATOSEL3_Pos) #define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2UL << TAMP_ATCR2_ATOSEL3_Pos) -#endif /* TAMP_ATCR1_TAMP3AM */ /** * @} */ +#endif /* TAMP */ /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV * @{ @@ -1020,7 +940,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } -#if defined(RTC_CR_TAMPALRM_TYPE) +#if defined(TAMP) /** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType @@ -1047,39 +967,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); } -#endif /* RTC_CR_TAMPALRM_TYPE */ - -#if defined(RTC_ICSR_INIT) -/** - * @brief Enable initialization mode - * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) - * and prescaler register (RTC_PRER). - * Counters are stopped and start counting from the new value when INIT is reset. - * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) -{ - /* Set the Initialization mode */ - WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK); -} - -/** - * @brief Disable initialization mode (Free running mode) - * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) -{ - /* Exit Initialization mode */ - WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT); -} - -#endif /* RTC_ICSR_INIT */ - -#if defined(RTC_OR_ALARMOUTTYPE) +#else /** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note Used only when RTC_ALARM is mapped on PC13 @@ -1108,9 +996,37 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); } -#endif /* RTC_OR_ALARMOUTTYPE */ +#endif /* TAMP */ -#if defined(RTC_ISR_INIT) +#if defined(TAMP) +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT); +} + +#else /** * @brief Enable initialization mode * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) @@ -1137,7 +1053,7 @@ __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) /* Exit Initialization mode */ WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); } -#endif /* RTC_ISR_INIT */ +#endif /* TAMP */ /** * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) @@ -1296,7 +1212,7 @@ __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); } -#if defined(RTC_CR_TAMPOE) +#if defined(TAMP) /** * @brief Enable tamper output. * @note When the tamper output is enabled, all external and internal tamper flags @@ -1331,9 +1247,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL); } -#endif /* RTC_CR_TAMPOE */ -#if defined(RTC_CR_TAMPALRM_PU) /** * @brief Enable internal pull-up in output mode. * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp @@ -1366,9 +1280,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL); } -#endif /* RTC_CR_TAMPALRM_PU */ -#if defined(RTC_CR_OUT2EN) /** * @brief Enable RTC_OUT2 output * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) @@ -1404,10 +1316,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL); } - -#endif /* RTC_CR_OUT2EN */ - -#if defined(RTC_OR_OUT_RMP) +#else /** * @brief Enable RTC_OUT remap * @rmtoll OR OUT_RMP LL_RTC_EnableOutRemap @@ -1429,7 +1338,7 @@ __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP); } -#endif /* RTC_OR_OUT_RMP */ +#endif /* TAMP */ /** * @} @@ -2948,7 +2857,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) * @{ */ -#if defined(RTC_TAMPCR_TAMPTS) +#if !defined(TAMP) /** * @brief Activate timestamp on tamper detection event * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper @@ -2970,9 +2879,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); } -#endif /* RTC_TAMPCR_TAMPTS */ - -#if defined(RTC_CR_TAMPTS) +#else /** * @brief Activate timestamp on tamper detection event * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper @@ -2995,7 +2902,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); } -#endif /* RTC_CR_TAMPTS */ +#endif /* !TAMP */ /** * @} @@ -3005,7 +2912,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * @{ */ -#if defined(RTC_TAMPCR_TAMP1E) +#if !defined(TAMP) /** * @brief Enable RTC_TAMPx input detection * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable @@ -3114,9 +3021,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t T { SET_BIT(RTCx->TAMPCR, Tamper); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMPPUDIS) /** * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp @@ -3138,9 +3043,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); } -#endif /* RTC_TAMPCR_TAMPPUDIS */ -#if defined(RTC_TAMPCR_TAMPPRCH) /** * @brief Set RTC_TAMPx precharge duration * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge @@ -3171,9 +3074,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); } -#endif /* RTC_TAMPCR_TAMPPRCH */ -#if defined(RTC_TAMPCR_TAMPFLT) /** * @brief Set RTC_TAMPx filter count * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount @@ -3204,9 +3105,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); } -#endif /* RTC_TAMPCR_TAMPFLT */ -#if defined(RTC_TAMPCR_TAMPFREQ) /** * @brief Set Tamper sampling frequency * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq @@ -3245,9 +3144,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); } -#endif /* RTC_TAMPCR_TAMPFREQ */ -#if defined(RTC_TAMPCR_TAMP1E) /** * @brief Enable Active level for Tamper input * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel @@ -3283,9 +3180,9 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ { CLEAR_BIT(RTCx->TAMPCR, Tamper); } -#endif /* RTC_TAMPCR_TAMP1E */ +#endif /* !TAMP */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) /** * @brief Enable TAMPx input detection * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable @@ -3321,9 +3218,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper) { CLEAR_BIT(TAMPx->CR1, Tamper); } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR2_TAMP1MSK) /** * @brief Enable Tamper mask flag * @note Associated Tamper IT must not enabled when tamper mask is set. @@ -3432,9 +3327,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint3 { CLEAR_BIT(TAMPx->CR2, Tamper); } -#endif /* TAMP_CR2_TAMP1MSK */ -#if defined(TAMP_FLTCR_TAMPPUDIS) /** * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp @@ -3557,7 +3450,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx) { return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ)); } -#endif /* TAMP_FLTCR_TAMPPUDIS */ +#endif /* TAMP */ /** * @} @@ -3672,7 +3565,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) * @{ */ -#if defined(RTC_BKP0R) +#if !defined(TAMP) /** * @brief Writes a data in a specified RTC Backup data register. * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister @@ -3773,9 +3666,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back /* Read the specified register */ return (*(__IO uint32_t *)tmp); } -#endif /* RTC_BKP0R */ - -#if defined(TAMP_BKP0R) +#else /** * @brief Writes a data in a specified Backup data register. * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister @@ -3818,7 +3709,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back */ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) { - uint32_t tmp = 0U; + uint32_t tmp; tmp = (uint32_t)(&(TAMPx->BKP0R)); tmp += (BackupRegister * 4U); @@ -3868,7 +3759,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) { - uint32_t tmp = 0U; + uint32_t tmp; tmp = (uint32_t)(&(TAMPx->BKP0R)); tmp += (BackupRegister * 4U); @@ -3876,7 +3767,7 @@ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t Ba /* Read the specified register */ return (*(__IO uint32_t *)tmp); } -#endif /* TAMP_BKP0R */ +#endif /* !TAMP */ /** * @} @@ -4013,7 +3904,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) * @{ */ -#if defined(RTC_ISR_ITSF) +#if !defined(TAMP) /** * @brief Get Internal Time-stamp flag * @rmtoll RTC_ISR ITSF LL_RTC_IsActiveFlag_ITS @@ -4310,9 +4201,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } -#endif /* RTC_ISR_ITSF */ +#endif /* !TAMP */ -#if defined(RTC_SR_ITSF) +#if defined(TAMP) /** * @brief Get Internal Time-stamp flag * @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS @@ -4378,9 +4269,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL); } -#endif /* RTC_SR_ITSF */ -#if defined(RTC_SCR_CITSF) /** * @brief Clear Internal Time-stamp flag * @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS @@ -4446,9 +4335,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) { SET_BIT(RTCx->SCR, RTC_SCR_CALRAF); } -#endif /* RTC_SCR_CITSF */ -#if defined(RTC_ICSR_RECALPF) /** * @brief Get Recalibration pending Flag * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP @@ -4547,9 +4434,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL); } -#endif /* RTC_ICSR_RECALPF */ -#if defined(RTC_MISR_ALRAMF) /** * @brief Get Alarm A masked flag. * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM @@ -4615,9 +4500,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL); } -#endif /* RTC_MISR_ALRAMF */ -#if defined(TAMP_CR1_TAMP1E) /** * @brief Get tamper 1 detection flag. * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 @@ -4628,9 +4511,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) /** * @brief Get tamper 2 detection flag. * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 @@ -4641,9 +4522,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) /** * @brief Get tamper 3 detection flag. * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3 @@ -4654,9 +4533,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP3E */ -#if defined(TAMP_CR1_TAMP1E) /** * @brief Get tamper 1 interrupt masked flag. * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M @@ -4667,9 +4544,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) /** * @brief Get tamper 2 interrupt masked flag. * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M @@ -4680,9 +4555,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) /** * @brief Get tamper 3 interrupt masked flag. * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M @@ -4693,9 +4566,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP3E */ -#if defined(TAMP_CR1_TAMP1E) /** * @brief Clear tamper 1 detection flag. * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 @@ -4706,9 +4577,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx) { SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F); } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) /** * @brief Clear tamper 2 detection flag. * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 @@ -4719,9 +4588,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx) { SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F); } -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) /** * @brief Clear tamper 3 detection flag. * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3 @@ -4732,7 +4599,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx) { SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F); } -#endif /* TAMP_CR1_TAMP3E */ +#endif /* TAMP */ /** * @} @@ -4838,7 +4705,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); } -#if defined(RTC_TAMPCR_TAMP3E) +#if !defined(TAMP) /** * @brief Enable Tamper 3 interrupt * @rmtoll TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3 @@ -4860,9 +4727,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); } -#endif /* RTC_TAMPCR_TAMP3E */ -#if defined(RTC_TAMPCR_TAMP2E) /** * @brief Enable Tamper 2 interrupt * @rmtoll TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2 @@ -4884,9 +4749,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP1E) /** * @brief Enable Tamper 1 interrupt * @rmtoll TAMPCR TAMP1IE LL_RTC_EnableIT_TAMP1 @@ -4908,9 +4771,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMPIE) /** * @brief Enable all Tamper Interrupt * @rmtoll TAMPCR TAMPIE LL_RTC_EnableIT_TAMP @@ -4932,7 +4793,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); } -#endif /* RTC_TAMPCR_TAMPIE */ +#endif /* !TAMP */ /** * @brief Check if Time-stamp interrupt is enabled or not @@ -4978,7 +4839,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } -#if defined(RTC_TAMPCR_TAMP3E) +#if !defined(TAMP) /** * @brief Check if Tamper 3 interrupt is enabled or not * @rmtoll TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3 @@ -4989,9 +4850,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); } -#endif /* RTC_TAMPCR_TAMP3E */ -#if defined(RTC_TAMPCR_TAMP2E) /** * @brief Check if Tamper 2 interrupt is enabled or not * @rmtoll TAMPCR TAMP2IE LL_RTC_IsEnabledIT_TAMP2 @@ -5003,9 +4862,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP1E) /** * @brief Check if Tamper 1 interrupt is enabled or not * @rmtoll TAMPCR TAMP1IE LL_RTC_IsEnabledIT_TAMP1 @@ -5016,9 +4873,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMPIE) /** * @brief Check if all the TAMPER interrupts are enabled or not * @rmtoll TAMPCR TAMPIE LL_RTC_IsEnabledIT_TAMP @@ -5029,9 +4884,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); } -#endif /* RTC_TAMPCR_TAMPIE */ +#endif /* !TAMP */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) /** * @brief Enable tamper 1 interrupt. * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 @@ -5053,9 +4908,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx) { CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE); } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) /** * @brief Enable tamper 2 interrupt. * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 @@ -5077,9 +4930,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx) { CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE); } -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) /** * @brief Enable tamper 3 interrupt. * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3 @@ -5101,9 +4952,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx) { CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE); } -#endif /* TAMP_CR1_TAMP3E */ -#if defined(TAMP_CR1_TAMP1E) /** * @brief Check if tamper 1 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 @@ -5114,9 +4963,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) /** * @brief Check if tamper 2 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 @@ -5127,9 +4974,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) /** * @brief Check if tamper 3 interrupt is enabled or not. * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3 @@ -5140,13 +4985,11 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx) { return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL); } -#endif /* TAMP_CR1_TAMP3E */ /** * @} */ -#if defined (TAMP_ATCR1_TAMP1AM) /** @defgroup RTC_LL_EF_Active_Tamper Active Tamper * @{ */ @@ -5287,9 +5130,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void) { return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3))); } -#endif /* TAMP_ATCR1_TAMP1AM */ -#if defined(ATSEEDR) /** * @brief Write active tamper seed. * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed @@ -5300,9 +5141,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed) { WRITE_REG(TAMP->ATSEEDR, Seed); } -#endif /* ATSEEDR */ -#if defined(TAMP_ATOR_INITS) /** * @brief Get active tamper initialization status flag. * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS @@ -5322,7 +5161,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void) { return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U); } -#endif /* TAMP_ATOR_INITS */ +#endif /* TAMP */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h index abac58160d..6e12084e4b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_sdmmc.h @@ -279,6 +279,7 @@ typedef struct #define SDMMC_SDR104_SWITCH_PATTERN ((uint32_t)0x80FF1F03U) #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) +#define SDMMC_SDR12_SWITCH_PATTERN ((uint32_t)0x80FFFF00U) #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) @@ -356,12 +357,15 @@ typedef struct #define SDMMC_SPEED_MODE_DEFAULT ((uint32_t)0x00000001U) #define SDMMC_SPEED_MODE_HIGH ((uint32_t)0x00000002U) #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) +#define SDMMC_SPEED_MODE_ULTRA_SDR104 SDMMC_SPEED_MODE_ULTRA #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) +#define SDMMC_SPEED_MODE_ULTRA_SDR50 ((uint32_t)0x00000005U) -#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ - ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ - ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ - ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ +#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ + ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ + ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50) || \ ((MODE) == SDMMC_SPEED_MODE_DDR)) /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h index 3bc388b811..cb623a06fa 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_spi.h @@ -2412,7 +2412,27 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); } +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} /** * @} */ @@ -2440,7 +2460,12 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) { +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ } /** @@ -2479,7 +2504,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); *spitxdr = TxData; #else - SPIx->TXDR = TxData; + *((__IO uint16_t *)&SPIx->TXDR) = TxData; #endif /* __GNUC__ */ } @@ -2583,6 +2608,9 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); /** * @} */ +/** + * @} + */ /** @defgroup I2S_LL I2S * @{ @@ -3711,13 +3739,14 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) LL_SPI_TransmitData32(SPIx, TxData); } + /** * @} */ #if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions * @{ */ @@ -3745,9 +3774,6 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, * @} */ -/** - * @} - */ #ifdef __cplusplus } #endif diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h index cd1ad29134..cea1840eaf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_system.h @@ -542,8 +542,8 @@ __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*) * * (*) value not defined in all devices * @retval None diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h index dfb4ac48b0..f68a4e0bd3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h @@ -979,51 +979,51 @@ typedef struct * @} */ -#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ -#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */ -#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */ -#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */ -#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ -#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */ -#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */ -#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */ - -#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ -#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */ -#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */ -#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */ -#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */ - -#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /* !< TIM2_ETR is connected to GPIO */ -#define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to COMP1 OUT */ -#define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM2_ETR is connected to COMP2 OUT */ -#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */ -#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /* !< TIM2_ETR is connected to SAI1 FS_A */ -#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */ - -#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /* !< TIM3_ETR is connected to GPIO */ -#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /* !< TIM3_ETR is connected to COMP1 OUT */ - -#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /* !< TIM5_ETR is connected to GPIO */ -#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI2 FS_A */ -#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI2 FS_B */ -#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM5_ETR is connected to SAI4 FS_A */ -#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM5_ETR is connected to SAI4 FS_B */ - -#define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /* !< TIM23_ETR is connected to GPIO */ -#define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /* !< TIM23_ETR is connected to COMP1 OUT */ -#define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /* !< TIM23_ETR is connected to COMP2 OUT */ - -#define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /* !< TIM24_ETR is connected to GPIO */ -#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /* !< TIM24_ETR is connected to SAI4 FS_A */ -#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /* !< TIM24_ETR is connected to SAI4 FS_B */ -#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM24_ETR is connected to SAI1 FS_A */ -#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /* !< TIM24_ETR is connected to SAI1 FS_B */ +#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */ +#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */ +#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */ +#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */ +#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */ +#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */ +#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */ +#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */ +#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */ + +#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */ +#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */ +#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */ +#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */ + +#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */ +#define LL_TIM_TIM2_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */ +#define LL_TIM_TIM2_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */ +#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */ +#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */ +#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */ + +#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */ +#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */ + +#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */ +#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */ +#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */ +#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */ +#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */ + +#define LL_TIM_TIM23_ETRSOURCE_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */ +#define LL_TIM_TIM23_ETRSOURCE_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */ +#define LL_TIM_TIM23_ETRSOURCE_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */ + +#define LL_TIM_TIM24_ETRSOURCE_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */ +#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */ +#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */ +#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */ +#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */ /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity * @{ @@ -1219,8 +1219,8 @@ typedef struct /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /* !< TIM1 input 1 is connected to GPIO */ -#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM1 input 1 is connected to COMP1 OUT */ +#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */ +#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1 OUT */ /** * @} */ @@ -1228,8 +1228,8 @@ typedef struct /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /* !< TIM8 input 1 is connected to GPIO */ -#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /* !< TIM8 input 1 is connected to COMP2 OUT */ +#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */ +#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP2 OUT */ /** * @} */ @@ -1237,10 +1237,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap * @{ */ -#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /* !< TIM2 input 4 is connected to GPIO */ -#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM2 input 4 is connected to COMP1 OUT */ -#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM2 input 4 is connected to COMP2 OUT */ -#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */ +#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */ +#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1 OUT */ +#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2 OUT */ +#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */ /** * @} */ @@ -1248,10 +1248,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /* !< TIM3 input 1 is connected to GPIO */ -#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM3 input 1 is connected to COMP1 OUT */ -#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM3 input 1 is connected to COMP2 OUT */ -#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */ +#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */ +#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1 OUT */ +#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2 OUT */ +#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */ /** * @} */ @@ -1259,9 +1259,9 @@ typedef struct /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /* !< TIM5 input 1 is connected to GPIO */ -#define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5 input 1 is connected to CAN TMP */ -#define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5 input 1 is connected to CAN RTP */ +#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */ +#define LL_TIM_TIM5_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to CAN TMP */ +#define LL_TIM_TIM5_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to CAN RTP */ /** * @} */ @@ -1269,8 +1269,8 @@ typedef struct /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /* !< TIM12 input 1 is connected to GPIO */ -#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 input 1 is connected to SPDIF FS */ +#define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000U /*!< TIM12 input 1 is connected to GPIO */ +#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 input 1 is connected to SPDIF FS */ /** * @} */ @@ -1278,13 +1278,13 @@ typedef struct /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /* !< TIM15 input 1 is connected to GPIO */ -#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15 input 1 is connected to TIM2 CH1 */ -#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15 input 1 is connected to TIM3 CH1 */ -#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */ -#define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /* !< TIM15 input 1 is connected to RCC LSE */ -#define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI */ -#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */ +#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */ +#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to TIM2 CH1 */ +#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to TIM3 CH1 */ +#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */ +#define LL_TIM_TIM15_TI1_RMP_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15 input 1 is connected to RCC LSE */ +#define LL_TIM_TIM15_TI1_RMP_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI */ +#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */ /** * @} */ @@ -1292,10 +1292,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap * @{ */ -#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /* !< TIM15 input 2 is connected to GPIO */ -#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /* !< TIM15 input 2 is connected to TIM2 CH2 */ -#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM3 CH2 */ -#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */ +#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */ +#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to TIM2 CH2 */ +#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM3 CH2 */ +#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */ /** * @} */ @@ -1303,10 +1303,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /* !< TIM16 input 1 is connected to GPIO */ -#define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /* !< TIM16 input 1 is connected to RCC LSI */ -#define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /* !< TIM16 input 1 is connected to RCC LSE */ -#define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */ +#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */ +#define LL_TIM_TIM16_TI1_RMP_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to RCC LSI */ +#define LL_TIM_TIM16_TI1_RMP_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to RCC LSE */ +#define LL_TIM_TIM16_TI1_RMP_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */ /** * @} */ @@ -1314,10 +1314,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /* !< TIM17 input 1 is connected to GPIO */ -#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 input 1 is connected to SPDIF FS */ -#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */ -#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */ +#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */ +#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to SPDIF FS */ +#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */ +#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */ /** * @} */ @@ -1325,10 +1325,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM23_TI4_RMP TIM23 Timer Input Ch4 Remap * @{ */ -#define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /* !< TIM23 input 4 is connected to GPIO */ -#define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /* !< TIM23 input 4 is connected to COMP1 OUT */ -#define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /* !< TIM23 input 4 is connected to COMP2 OUT */ -#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */ +#define LL_TIM_TIM23_TI4_RMP_GPIO 0x00000000U /*!< TIM23 input 4 is connected to GPIO */ +#define LL_TIM_TIM23_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23 input 4 is connected to COMP1 OUT */ +#define LL_TIM_TIM23_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23 input 4 is connected to COMP2 OUT */ +#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */ /** * @} */ @@ -1336,10 +1336,10 @@ typedef struct /** @defgroup TIM_LL_EC_TIM24_TI1_RMP TIM24 Timer Input Ch1 Remap * @{ */ -#define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /* !< TIM24 input 1 is connected to GPIO */ -#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */ -#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */ -#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */ +#define LL_TIM_TIM24_TI1_RMP_GPIO 0x00000000U /*!< TIM24 input 1 is connected to GPIO */ +#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */ +#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */ +#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */ #if defined(TIM_BREAK_INPUT_SUPPORT) /** Legacy definitions for compatibility purpose @@ -1382,10 +1382,6 @@ typedef struct * @} */ -/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros - * @{ - */ - /** * @brief HELPER macro retrieving the UIFCPY flag from the counter value. * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); @@ -1529,7 +1525,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -1562,7 +1558,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -1596,7 +1592,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -1623,7 +1619,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -1667,7 +1663,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -1709,7 +1705,7 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } @@ -1746,7 +1742,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -1773,7 +1769,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -1786,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -1813,7 +1809,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -1842,7 +1838,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -1870,7 +1866,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } @@ -1904,7 +1900,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @param Counter Counter value * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter) +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) { return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); } @@ -1983,7 +1979,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -2218,7 +2214,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2284,7 +2280,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -2353,7 +2349,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -2722,7 +2718,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2738,7 +2734,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2754,7 +2750,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2770,7 +2766,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2783,7 +2779,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); } @@ -2796,7 +2792,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR6)); } @@ -2916,7 +2912,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2967,7 +2963,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3042,7 +3038,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3099,7 +3095,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -3156,7 +3152,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -3172,7 +3168,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -3188,7 +3184,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -3204,7 +3200,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -3251,7 +3247,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -3443,7 +3439,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -3899,7 +3895,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -3942,7 +3938,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -4211,7 +4207,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -4233,7 +4229,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -4255,7 +4251,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -4277,7 +4273,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -4299,7 +4295,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -4321,7 +4317,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); } @@ -4343,7 +4339,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); } @@ -4365,7 +4361,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -4387,7 +4383,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -4409,7 +4405,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -4431,7 +4427,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); } @@ -4454,7 +4450,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -4477,7 +4473,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -4500,7 +4496,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -4523,7 +4519,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -4545,7 +4541,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); } @@ -4585,7 +4581,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -4618,7 +4614,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -4651,7 +4647,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -4684,7 +4680,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -4717,7 +4713,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -4750,7 +4746,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -4783,7 +4779,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -4816,7 +4812,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -4856,7 +4852,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -4889,7 +4885,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -4922,7 +4918,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -4955,7 +4951,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -4988,7 +4984,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -5021,7 +5017,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -5054,7 +5050,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -5176,17 +5172,17 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h index 5ff3e38e92..8494c356ab 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usart.h @@ -31,7 +31,8 @@ extern "C" { * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10) /** @defgroup USART_LL USART * @{ @@ -63,6 +64,12 @@ static const uint32_t USART_PRESCALER_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -650,7 +657,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); } @@ -689,7 +696,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); } @@ -728,7 +735,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); } @@ -767,7 +774,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 */ -__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); } @@ -838,7 +845,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); } @@ -916,7 +923,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -950,7 +957,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -977,7 +984,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -1008,7 +1015,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -1041,7 +1048,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); } @@ -1068,7 +1075,7 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } @@ -1100,7 +1107,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } @@ -1131,7 +1138,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } @@ -1162,7 +1169,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } @@ -1241,7 +1248,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc * @arg @ref LL_USART_PRESCALER_DIV128 * @arg @ref LL_USART_PRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); } @@ -1280,7 +1287,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); } @@ -1311,7 +1318,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -1372,7 +1379,7 @@ __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapCo * @arg @ref LL_USART_TXRX_STANDARD * @arg @ref LL_USART_TXRX_SWAPPED */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); } @@ -1399,7 +1406,7 @@ __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); } @@ -1426,7 +1433,7 @@ __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinI * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); } @@ -1455,7 +1462,7 @@ __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); } @@ -1486,7 +1493,7 @@ __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_BITORDER_LSBFIRST * @arg @ref LL_USART_BITORDER_MSBFIRST */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); } @@ -1525,7 +1532,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); } @@ -1593,7 +1600,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); } @@ -1637,7 +1644,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); } @@ -1650,7 +1657,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) * @arg @ref LL_USART_ADDRESS_DETECT_4B * @arg @ref LL_USART_ADDRESS_DETECT_7B */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); } @@ -1739,7 +1746,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -1772,7 +1779,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); } @@ -1805,7 +1812,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); } @@ -1838,7 +1845,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) * @arg @ref LL_USART_WAKEUP_ON_STARTBIT * @arg @ref LL_USART_WAKEUP_ON_RXNE */ -__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); } @@ -1926,7 +1933,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) { uint32_t usartdiv; @@ -1975,7 +1982,7 @@ __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); } @@ -1998,7 +2005,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); } @@ -2045,7 +2052,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); } @@ -2076,7 +2083,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -2105,7 +2112,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2152,7 +2159,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); } @@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); } @@ -2223,7 +2230,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, * @param USARTx USART Instance * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); } @@ -2252,7 +2259,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -2281,7 +2288,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); } @@ -2328,7 +2335,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); } @@ -2374,7 +2381,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); } @@ -2416,7 +2423,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); } @@ -2455,7 +2462,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } @@ -2494,7 +2501,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); } @@ -2529,7 +2536,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); } @@ -2556,7 +2563,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); } @@ -2595,7 +2602,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); } @@ -2626,7 +2633,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_DE_POLARITY_HIGH * @arg @ref LL_USART_DE_POLARITY_LOW */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); } @@ -2929,7 +2936,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); } @@ -2940,7 +2947,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); } @@ -2951,7 +2958,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); } @@ -2962,7 +2969,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); } @@ -2973,13 +2980,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not @@ -2989,7 +2995,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); } @@ -3000,13 +3006,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not @@ -3016,7 +3021,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); } @@ -3029,7 +3034,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); } @@ -3042,7 +3047,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); } @@ -3055,7 +3060,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); } @@ -3066,7 +3071,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); } @@ -3079,7 +3084,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); } @@ -3092,7 +3097,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); } @@ -3105,7 +3110,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); } @@ -3118,7 +3123,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); } @@ -3129,7 +3134,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); } @@ -3140,7 +3145,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); } @@ -3151,7 +3156,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); } @@ -3162,7 +3167,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); } @@ -3175,7 +3180,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } @@ -3186,7 +3191,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); } @@ -3197,7 +3202,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); } @@ -3210,7 +3215,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); } @@ -3223,7 +3228,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); } @@ -3234,7 +3239,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); } @@ -3247,7 +3252,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); } @@ -3260,7 +3265,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); } @@ -3461,8 +3466,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3488,8 +3492,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -3678,8 +3681,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -3705,8 +3707,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -3892,13 +3893,12 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -3908,7 +3908,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); } @@ -3919,13 +3919,12 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled @@ -3935,7 +3934,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); } @@ -3946,7 +3945,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); } @@ -3957,7 +3956,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); } @@ -3968,7 +3967,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); } @@ -3981,7 +3980,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); } @@ -3994,7 +3993,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); } @@ -4007,7 +4006,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); } @@ -4020,7 +4019,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); } @@ -4031,7 +4030,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); } @@ -4044,7 +4043,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); } @@ -4057,7 +4056,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } @@ -4070,7 +4069,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); } @@ -4083,7 +4082,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); } @@ -4096,7 +4095,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); } @@ -4137,7 +4136,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); } @@ -4170,7 +4169,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); } @@ -4203,7 +4202,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) { return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); } @@ -4218,7 +4217,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) { uint32_t data_reg_addr; @@ -4250,7 +4249,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } @@ -4261,7 +4260,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); } @@ -4369,10 +4368,10 @@ __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h index 7909971f5a..59599bf9fc 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h +++ b/system/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h @@ -41,14 +41,13 @@ extern "C" { /** * @brief USB Mode definition */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) typedef enum { - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 -} USB_OTG_ModeTypeDef; + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; /** * @brief URB States definition @@ -61,7 +60,7 @@ typedef enum URB_NYET, URB_ERROR, URB_STALL -} USB_OTG_URBStateTypeDef; +} USB_URBStateTypeDef; /** * @brief Host channel States definition @@ -71,13 +70,14 @@ typedef enum HC_IDLE = 0, HC_XFRC, HC_HALTED, + HC_ACK, HC_NAK, HC_NYET, HC_STALL, HC_XACTERR, HC_BBLERR, HC_DATATGLERR -} USB_OTG_HCStateTypeDef; +} USB_HCStateTypeDef; /** @@ -93,12 +93,12 @@ typedef struct This parameter Depends on the used USB core. This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */ + uint32_t speed; /*!< USB Core speed. This parameter can be any value of @ref PCD_Speed/HCD_Speed (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ - uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. @@ -106,7 +106,7 @@ typedef struct uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ @@ -118,7 +118,7 @@ typedef struct uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ -} USB_OTG_CfgTypeDef; +} USB_CfgTypeDef; typedef struct { @@ -140,25 +140,25 @@ typedef struct uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + uint8_t even_odd_frame; /*!< IFrame parity This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ uint16_t tx_fifo_num; /*!< Transmission FIFO number This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - uint32_t xfer_len; /*!< Current transfer length */ - uint32_t xfer_size; /*!< requested transfer size */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ -} USB_OTG_EPTypeDef; +} USB_EPTypeDef; typedef struct { @@ -209,14 +209,19 @@ typedef struct uint32_t ErrCnt; /*!< Host channel error count. */ - USB_OTG_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ - USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ -} USB_OTG_HCTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -244,18 +249,6 @@ typedef struct * @} */ -/** @defgroup USB_LL Device Speed - * @{ - */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FSLS_SPEED 1U -/** - * @} - */ - /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed * @{ */ @@ -319,7 +312,7 @@ typedef struct /** * @} */ - +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ @@ -331,6 +324,18 @@ typedef struct * @} */ +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + /** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed * @{ */ @@ -341,18 +346,30 @@ typedef struct * @} */ -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type * @{ */ -#define EP_TYPE_CTRL 0U -#define EP_TYPE_ISOC 1U -#define EP_TYPE_BULK 2U -#define EP_TYPE_INTR 3U -#define EP_TYPE_MSK 3U +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U /** * @} */ +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines * @{ */ @@ -375,6 +392,16 @@ typedef struct * @} */ +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines * @{ */ @@ -390,16 +417,15 @@ typedef struct #define HCCHAR_BULK 2U #define HCCHAR_INTR 3U -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U - #define GRXSTS_PKTSTS_IN 2U #define GRXSTS_PKTSTS_IN_XFER_COMP 3U #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U + #define TEST_J 1U #define TEST_K 2U #define TEST_SE0_NAK 3U @@ -423,13 +449,9 @@ typedef struct + USB_OTG_HOST_CHANNEL_BASE\ + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU - -#ifndef USE_USB_DOUBLE_BUFFER -#define USE_USB_DOUBLE_BUFFER 1U -#endif /* USE_USB_DOUBLE_BUFFER */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ @@ -468,7 +490,6 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); @@ -485,6 +506,7 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx); uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/README.md b/system/Drivers/STM32H7xx_HAL_Driver/README.md index 65b1799a1b..4beea88ec5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/README.md +++ b/system/Drivers/STM32H7xx_HAL_Driver/README.md @@ -27,19 +27,7 @@ Details about the content of this release are available in the release note [her ## Compatibility information -In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package: - -It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in this table. - -HAL Driver H7 | CMSIS Device H7 | CMSIS Core | Was delivered in the full MCU package -------------- | --------------- | ---------- | ------------------------------------- -Tag v1.6.0 | Tag v1.6.0 | Tag v5.4.0 | Tag v1.5.0 (and following, if any, till next HAL tag) -Tag v1.7.0 | Tag v1.7.0 | Tag v5.4.0 | Tag v1.6.0 (and following, if any, till next HAL tag) -Tag v1.8.0 | Tag v1.8.0 | Tag v5.4.0 | Tag v1.7.0 (and following, if any, till next HAL tag) -Tag v1.9.0 | Tag v1.9.0 | Tag v5.4.0 | Tag v1.8.0 (and following, if any, till next HAL tag) -Tag v1.10.0 | Tag v1.10.0 | Tag v5.6.0 | Tag v1.9.0 (and following, if any, till next HAL tag) -Tag v1.10.1 | Tag v1.10.1 | Tag v5.6.0 | Tag v1.9.1 (and following, if any, till next HAL tag) -Tag v1.10.2 | Tag v1.10.2 | Tag v5.6.0 | Tag v1.10.0 (and following, if any, till next HAL tag) +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Release_Notes.html) release note. The full **STM32CubeH7** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH7). diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html index 942ecb97aa..3d43c4b61c 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32H7xx_HAL_Driver/Release_Notes.html @@ -43,11 +43,135 @@

Purpose

Update History

- +

Main Changes

  • General updates to fix known defects and implementation enhancements.
    • +
  • HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers.
    • +

  • HAL code quality enhancement for MISRA-C2012 Rule-2.2_c.

    • +
  • HAL Generic +
      +
    • HAL code quality enhancement for MISRA-C2012 Rule-10.4_a: adding sign qualifier.
      • +
    • +
  • HAL RCC +
      +
    • Wait at least 2 CK_REF cycles after FRACEN has been cleared before setting it back.
      • +
    • Macros RCC_SPI4CLKSOURCE_D2PCLK1, RCC_SPI5CLKSOURCE_D2PCLK1, RCC_SPI45CLKSOURCE_D2PCLK1, RCC_SPI45CLKSOURCE_CDPCLK1 and RCC_SPI45CLKSOURCE_PCLK1 were renamed with suffix PCLK2.
      • +
    • Add SPI45 peripheral clock frequency to HAL_RCCEx_GetPeriphCLKFreq().
      • +
    • Rename HAL_RCC_CCSCallback() API to HAL_RCC_CSSCallback().
      • +
    • The last line of the definition of IS_RCC_I2C4CLKSOURCE macro is corrected : RCC_I2C3CLKSOURCE_CSI is changed by RCC_I2C4CLKSOURCE_CSI.
      • +
    • Update HAL_RCC_GetHCLKFreq() to return the right HCLK frequency when a single core product is selected.
      • +
    • +
  • HAL EXTI +
      +
    • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine().
      • +
    • Optimize computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine().
      • +
    • +
  • HAL/LL ADC +
      +
    • Update the LL_ADC_ConfigOverSamplingRatioShift() and the LL_ADC_GetOverSamplingRatio() APIs to correctly set the data resolution for the ADC3.
      • +
    • Add LL_ADC_GetChannelPreselection() API and rename LL_ADC_SetChannelPreSelection() to LL_ADC_SetChannelPreselection().
      • +
    • Update description of offset value range: add mention of oversampling ratio increasing offset maximum value.
      • +
    • +
  • HAL RTC_BKP +
      +
    • Check if the RTC calendar has been previously initialized before entering Initialization mode.
      • +
    • Clear RSF flag using a single ‘write’ operation instead of a ‘read-modify-write’ sequence to avoid clearing other ISR flags if set in the meantime.
      • +
    • Optimize the use of #ifdef … #endif directives for better readability and maintainability.
      • +
    • Rearrange the de-initialization sequence to be compliant with the reference manual.
      • +
    • Move the ‘exit initialization mode’ call after PRER, ALRMAR, ALRMBR, and WUTR registers are reset.
      • +
    • Group the tamper registers reset instruction for better readability.
      • +
    • +
  • LL TIM +
      +
    • Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances.
      • +
    • +
  • HAL HRTIM +
      +
    • Macros HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8, HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 and HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 were removed from HAL library code.
      • +
    • +
  • HAL CRC +
      +
    • Add filter in HAL_CRCEx_Polynomial_Set() to exclude even polynomials.
      • +
    • +
  • HAL CEC +
      +
    • Better performance by removing multiple volatile reads or writes in interrupt handler.
      • +
    • +
  • HAL SDMMC +
      +
    • Update HAL_SD_ConfigSpeedBusOperation() API to add support of switch to Default Speed.
      • +
    • +
  • HAL DSI +
      +
    • Update to align DSI ULPS entry and exit sequences with reference manual.
      • +
    • +
  • HAL CRYP +
      +
    • Rename CRYP Data Type possible values to avoid any eventual usage confusion:
      • +
    • CRYP_DATATYPE_32B renamed CRYP_NO_SWAP
      • +
    • CRYP_DATATYPE_16B renamed CRYP_HALFWORD_SWAP
      • +
    • CRYP_DATATYPE_8B renamed CRYP_BYTE_SWAP
      • +
    • CRYP_DATATYPE_1B renamed CRYP_BIT_SWAP
      • +
    • +
  • HAL SAI +
      +
    • Avoid using magic numbers.
      • +
    • +
  • HAL I2C +
      +
    • Timeout issue using HAL MEM interface through FreeRTOS.
      • +
    • I2C_IsErrorOccurred does not return error if timeout is detected.
      • +
    • The ADDRF flag is cleared too early when the restart is received but the direction has changed.
      • +
    • +
  • HAL/LL SPI +
      +
    • Change argument order in SPI_WaitOnFlagUntilTimeout to be aligned with declaration.
      • +
    • Fix dereferencing pointer warning on GNU compiler inside LL_SPI_ReceiveData16() function.
      • +
    • +
  • HAL ETH +
      +
    • Add missing default callbacks initialization to static function ETH_InitCallbacksToDefault().
      • +
    • Fix MISRAC2012-Rule-2.3 warning in HAL ETH driver: +
        +
      • Unused type declaration
        • +
      • +
    • +
  • HAL UART +
      +
    • Removal of HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs.
      • +
    • Disable the Receiver Timeout Interrupt when data reception is completed.
      • +
    • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior.
      • +
    • +
  • HAL DTS +
      +
    • Correction on IS_DTS_DIVIDER_RATIO_NUMBER macro.
      • +
    • Corrections on register callbacks feature implementation.
      • +
    • Correction on factory temperature value.
      • +
    • Avoid using magic numbers.
      • +
    • +
  • Documentation +
      +
    • Remove redundant word from @note of HAL_InitTick() header description, which may cause confusion when reading the note.
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Backward compatibility

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
  • The following changes done on the HAL drivers require an update of the application code based on older HAL versions
    • Rework of HAL Ethernet driver to resolve problems and improve performance.(compatibility break)
      • @@ -128,11 +252,11 @@

      Main Changes

    • Fix USB BCD data contact timeout
-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Compatibility break with HAL ETH driver V1.10.0 available within STM32CubeFW_H7 V1.9.0
@@ -141,7 +265,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
    • @@ -300,14 +424,14 @@

    Main Changes

  • Add LSI startup time in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT).
-

Known Limitations

+

Known Limitations

  • HAL/ETH
    • A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP
-

Backward compatibility

+

Backward compatibility

  • None
@@ -316,7 +440,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements

  • Fix minor issues related to English typo in comments

    • @@ -602,14 +726,14 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL/ETH
    • A full rework of the ETH HAL driver is planned in order to fix several issues including better synchronization with TCPIP stack for instance LwIP
-

Backward compatibility

+

Backward compatibility

  • None
@@ -618,7 +742,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • First official release of the STM32CubeH7 Firmware Package supporting STM32H72x/3x new devices
  • General updates to fix known defects and implementation enhancements
    • @@ -1212,11 +1336,11 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • Extension RTC APIs HAL_RTCEx_MonotonicCounterIncrement and HAL_RTCEx_MonotonicCounterGet APIs prototypes updated with new parameters Instance (alignment with other STM32 families)
@@ -1225,7 +1349,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • General updates to fix known defects and implementation enhancements
  • HAL: generic @@ -1459,7 +1583,7 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL I2S:
      @@ -1469,7 +1593,7 @@

      Known Limitations

-

Backward compatibility

+

Backward compatibility

  • None
@@ -1478,7 +1602,7 @@

Backward compatibility

-

Main Changes

+

Main Changes

  • Official release with support of STM32H7A3/B3xx/B0xx new devices
    • @@ -2033,7 +2157,7 @@

    Main Changes

-

Known Limitations

+

Known Limitations

  • HAL I2S:
      @@ -2047,7 +2171,7 @@

      Known Limitations

    • New PSSI driver provided supporting both modes : DMA mode recommended/ polling mode has hardware limitation confirmed and mentioned in the STM32H7A3/B3xx/B0xx erratasheet.
-

Backward compatibility

+

Backward compatibility

  • HAL I2S:
      @@ -2071,7 +2195,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements
      • HAL: generic @@ -2346,11 +2470,11 @@

        Main Changes

-

Known Limitations

+

Known Limitations

  • None
-

Backward compatibility

+

Backward compatibility

  • HAL TIM:
      @@ -2368,7 +2492,7 @@

      Backward compatibility

      -

      Main Changes

      +

      Main Changes

      • General updates to fix known defects and implementation enhancements
      • Add support for VOS0 power regulator voltage scaling with 480MHz over clock
        • @@ -2838,7 +2962,7 @@

        Main Changes

      • Update LL_Init1msTick and LL_SetSystemCoreClock description for DUAL CORE lines
    -

    Known Limitations

    +

    Known Limitations

    • HAL SD:
        @@ -2852,7 +2976,7 @@

        Known Limitations

      • Full duplex Transmit/receive feature not available
    -

    Backward compatibility

    +

    Backward compatibility

    • HAL ADC:
        @@ -2904,7 +3028,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • General updates to fix known defects and implementation enhancements
        • Add LL drivers : LL_ADC, LL_BDMA, LL_BUS, LL_COMP, LL_CORTEX, LL_CRC, LL_DAC, LL_DMA, LL_DMA2D, LL_DMAMUX, LL_EXTI, LL_GPIO, LL_HRTIM, LL_HSEM, LL_I2C, LL_IWDG, LL_LPTIM, LL_LPUART, LL_MDMA, LL_OPAMP,LL_PWR, LL_RCC, LL_RNG, LL_RTC, LL_SPI, LL_SWPMI, LL_SYSTEM, LL_TIM, LL_USART, LL_UTILS, LL_WWDG
          • @@ -3173,7 +3297,7 @@

          Main Changes

        • Protect the hcd driver to be used only if the USB_OTG_FS, USB_OTG_HS are enabled
      -

      Known Limitations

      +

      Known Limitations

      • HAL I2S:
          @@ -3181,7 +3305,7 @@

          Known Limitations

        • A new version of this driver will be available in next release with full features tested
      -

      Backward compatibility

      +

      Backward compatibility

      • HAL ADC:
          @@ -3221,7 +3345,7 @@

          Backward compatibility

          -

          Main Changes

          +

          Main Changes

          • Updates to fix known defects on HAL Cortex, HAL RCC and HAL SDMMC drivers
          • HAL Cortex: Driver update to support 16 MPU regions instead of 8. User can now select an MPU regions from MPU_REGION_NUMBER0 to MPU_REGION_NUMBER15
            • @@ -3233,7 +3357,7 @@

            Main Changes

            -

            Main Changes

            +

            Main Changes

            • General updates to fix known defects and enhancements implementation
            • HAL SPI: Driver reworked to fix critical issues
              • @@ -3244,7 +3368,7 @@

              Main Changes

              -

              Main Changes

              +

              Main Changes

              • General updates to fix known defects and enhancements implementation
              • HAL FLASH: Add Mass Erase for both banks
                • @@ -3259,7 +3383,7 @@

                Main Changes

                -

                Main Changes

                +

                Main Changes

                • First official release for STM32H743xx/753xx devices
                diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c index 8e9063f679..b84a46fad2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c @@ -47,11 +47,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32H7xx HAL Driver version number V1.11.0 + * @brief STM32H7xx HAL Driver version number V1.11.1 */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ -#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ +#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ @@ -78,11 +78,11 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Functions HAL Private Functions +/** @addtogroup HAL_Exported_Functions * @{ */ -/** @defgroup HAL_Group1 Initialization and de-initialization Functions +/** @addtogroup HAL_Group1 * @brief Initialization and de-initialization functions * @verbatim @@ -252,7 +252,7 @@ __weak void HAL_MspDeInit(void) * @note In the default implementation, SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals. * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The the SysTick interrupt must have higher priority (numerically lower) + * the SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. * The function is declared as __weak to be overwritten in case of other * implementation in user file. @@ -292,7 +292,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * @} */ -/** @defgroup HAL_Group2 HAL Control functions +/** @addtogroup HAL_Group2 * @brief HAL Control functions * @verbatim @@ -421,7 +421,7 @@ __weak void HAL_Delay(uint32_t Delay) * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment + * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -437,7 +437,7 @@ __weak void HAL_SuspendTick(void) * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment + * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -887,9 +887,6 @@ void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0) MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0); } -/** - * @} - */ #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ #if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) @@ -905,9 +902,6 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1) MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1); } -/** - * @} - */ #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c index c3f408eb41..abdddb4d8d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cec.c @@ -233,7 +233,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) /* Write to CEC Control Register */ hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \ - hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \ + hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \ + hcec->Init.BroadcastMsgNoErrorBitGen | \ hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \ hcec->Init.ListenMode; @@ -412,10 +413,10 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) * @param hcec CEC handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -501,10 +502,10 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call * @param hcec uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID + * @arg HAL_CEC_ERROR_CB_ID Error callback ID + * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID * @retval status */ HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID) @@ -694,7 +695,7 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size) + const uint8_t *pData, uint32_t Size) { /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ @@ -749,7 +750,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator * @param hcec CEC handle * @retval Frame size */ -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec) { return hcec->RxXferSize; } @@ -775,13 +776,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { /* save interrupts register for further error or interrupts handling purposes */ - uint32_t reg; - reg = hcec->Instance->ISR; + uint32_t itflag; + itflag = hcec->Instance->ISR; /* ----------------------------Arbitration Lost Management----------------------------------*/ /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if ((reg & CEC_FLAG_ARBLST) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST)) { hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); @@ -789,7 +790,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Rx Management----------------------------------*/ /* CEC RX byte received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR)) { /* reception is starting */ hcec->RxState = HAL_CEC_STATE_BUSY_RX; @@ -801,7 +802,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* CEC RX end received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND)) { /* clear IT */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); @@ -820,7 +821,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Tx Management----------------------------------*/ /* CEC TX byte request interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR)) { --hcec->TxXferCount; if (hcec->TxXferCount == 0U) @@ -829,14 +830,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* In all cases transmit the byte */ - hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr; hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } /* CEC TX end interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); @@ -854,21 +855,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* ----------------------------Rx/Tx Error Management----------------------------------*/ - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR | - CEC_ISR_TXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | + CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) { - hcec->ErrorCode = reg; + hcec->ErrorCode = itflag; __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) { hcec->Init.RxBuffer -= hcec->RxXferSize; hcec->RxXferSize = 0U; hcec->RxState = HAL_CEC_STATE_READY; } - else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) + else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) { /* Set the CEC state ready to be able to start again the process */ hcec->gState = HAL_CEC_STATE_READY; @@ -957,9 +958,10 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC module. * @retval HAL state */ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = hcec->gState; temp2 = hcec->RxState; @@ -972,7 +974,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC. * @retval CEC Error Code */ -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec) { return hcec->ErrorCode; } @@ -993,4 +995,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) /** * @} */ - diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c index 7ac929a6d6..05218fe9fb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cordic.c @@ -159,8 +159,8 @@ /** @defgroup CORDIC_Private_Functions CORDIC Private Functions * @{ */ -static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff); -static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff); +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff); static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CORDIC_DMAError(DMA_HandleTypeDef *hdma); @@ -555,7 +555,7 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H * contains the CORDIC configuration information. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig) +HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -602,12 +602,12 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; - int32_t *p_tmp_in_buff = pInBuff; + const int32_t *p_tmp_in_buff = pInBuff; int32_t *p_tmp_out_buff = pOutBuff; /* Check parameters setting */ @@ -696,12 +696,12 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; - int32_t *p_tmp_in_buff = pInBuff; + const int32_t *p_tmp_in_buff = pInBuff; int32_t *p_tmp_out_buff = pOutBuff; /* Check parameters setting */ @@ -789,10 +789,10 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t * @param NbCalc Number of CORDIC calculation to process. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc) { - int32_t *tmp_pInBuff = pInBuff; + const int32_t *tmp_pInBuff = pInBuff; /* Check parameters setting */ if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U)) @@ -881,7 +881,7 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t * DMA transfer to and from the Peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection) { uint32_t sizeinbuff; @@ -1169,7 +1169,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) * the configuration information for CORDIC module * @retval HAL state */ -HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic) +HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic) { /* Return CORDIC handle state */ return hcordic->State; @@ -1182,7 +1182,7 @@ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic) * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map */ -uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic) +uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic) { /* Return CORDIC error code */ return hcordic->ErrorCode; @@ -1207,7 +1207,7 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic) * @param ppInBuff Pointer to pointer to input buffer. * @retval none */ -static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff) +static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff) { /* First write of input data in the Write Data register */ WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff); @@ -1233,7 +1233,7 @@ static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_ * @param ppOutBuff Pointer to pointer to output buffer. * @retval none */ -static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) +static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff) { /* First read of output data from the Read Data register */ **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c index d713187136..b4ba3de352 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c @@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol /* Check the parameters */ assert_param(IS_CRC_POL_LENGTH(PolyLength)); - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) { + status = HAL_ERROR; } - - switch (PolyLength) + else { - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - status = HAL_ERROR; - } - break; - - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - status = HAL_ERROR; - break; + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } } if (status == HAL_OK) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c index 33fb7762c3..f076b760a2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp.c @@ -49,7 +49,8 @@ priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() (#)Initialize the CRYP according to the specified parameters : - (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. + (##) The data type: bit swap(1-bit data), byte swap(8-bit data), half word swap(16-bit data) + or no swap(32-bit data). (##) The key size: 128, 192 or 256. (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM. (##) The initialization vector (counter). It is not used in ECB mode. @@ -286,9 +287,9 @@ /** @addtogroup CRYP_Private_Defines * @{ */ -#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ +#define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /*!< The latency of GCM/CCM header phase is 290 clock cycles.*/ #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */ @@ -554,15 +555,17 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD __HAL_LOCK(hcryp); /* Set CRYP parameters */ - hcryp->Init.DataType = pConf->DataType; - hcryp->Init.pKey = pConf->pKey; - hcryp->Init.Algorithm = pConf->Algorithm; - hcryp->Init.KeySize = pConf->KeySize; - hcryp->Init.pInitVect = pConf->pInitVect; - hcryp->Init.Header = pConf->Header; - hcryp->Init.HeaderSize = pConf->HeaderSize; - hcryp->Init.B0 = pConf->B0; - hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, @@ -626,7 +629,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->Header = hcryp->Init.Header ; pConf->HeaderSize = hcryp->Init.HeaderSize; pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -1470,7 +1475,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu hcryp->Phase = CRYP_PHASE_PROCESS; /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); break; @@ -1503,10 +1509,10 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu /* Set the Initialization Vector*/ if (hcryp->Init.Algorithm != CRYP_AES_ECB) { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); } } /* if (DoKeyIVConfig == 1U) */ @@ -1514,7 +1520,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu hcryp->Phase = CRYP_PHASE_PROCESS; /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); break; case CRYP_AES_GCM: @@ -1622,7 +1629,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu hcryp->Phase = CRYP_PHASE_PROCESS; /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); break; case CRYP_AES_ECB: @@ -1697,11 +1705,13 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U) { - if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) + if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) || + (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) { CRYP_TDES_IT(hcryp); /* DES or TDES*/ } - else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR)) + else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || + (hcryp->Init.Algorithm == CRYP_AES_CTR)) { CRYP_AES_IT(hcryp); /*AES*/ } @@ -1863,7 +1873,8 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { - /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the Output FIFO and put them in temporary Buffer + then get CrypOutBuff from temporary buffer */ temp = hcryp->Instance->DOUT; *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; hcryp->CrypOutCount++; @@ -1899,7 +1910,7 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) { if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) { - if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U) { /* Write input block in the IN FIFO */ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -1926,9 +1937,10 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U) { - if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U) + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U) { - /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the Output FIFO and put them in temporary Buffer + then get CrypOutBuff from temporary buffer */ temp = hcryp->Instance->DOUT; *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; hcryp->CrypOutCount++; @@ -2143,51 +2155,51 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti if (DoKeyIVConfig == 1U) { - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ - { - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + /* Wait for BUSY flag to be raised */ + if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); + } + else /*Algorithm CTR */ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); } - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - } -} /* if (DoKeyIVConfig == 1U) */ + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2224,7 +2236,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) { __IO uint32_t count = 0U; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { @@ -2245,54 +2257,54 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) if (DoKeyIVConfig == 1U) { - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) - { - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) + /* Wait for BUSY flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + count-- ; + if (count == 0U) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); + } + else /*Algorithm CTR */ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - } -} /* if (DoKeyIVConfig == 1U) */ + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2345,56 +2357,56 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) if (DoKeyIVConfig == 1U) { - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) - { - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* change ALGOMODE to key preparation for decryption*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) + /* Wait for BUSY flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } + /* Turn back to ALGOMODE of the configuration */ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); + } + else /*Algorithm CTR */ + { + /* Set the Key*/ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - } -} /* if (DoKeyIVConfig == 1U) */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + } + } /* if (DoKeyIVConfig == 1U) */ /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -2402,7 +2414,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) if (hcryp->Size != 0U) { /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); } else { @@ -2473,7 +2486,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ { - /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */ + /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */ temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR; if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) @@ -2539,7 +2552,8 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp = hcryp->Instance->DOUT; *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; @@ -2711,13 +2725,14 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U))) { - /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the Output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUT; } i = 0U; - while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U)) + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -2778,13 +2793,14 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUT; } i = 0U; - while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U)) + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -2915,79 +2931,79 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if (DoKeyIVConfig == 1U) { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /****************************** Init phase **********************************/ + /****************************** Init phase **********************************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /*Wait for the CRYPEN bit to be cleared*/ - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + /*Wait for the CRYPEN bit to be cleared*/ + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } - } - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } - /*************************Payload phase ************************************/ + /*************************Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); - } + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); + } - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); -} /* if (DoKeyIVConfig == 1U) */ + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { @@ -3100,10 +3116,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t { for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUT; } - for (index=0; indexpCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; hcryp->CrypOutCount++; @@ -3161,49 +3178,49 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) /* Configure Key, IV and process message (header and payload) */ if (DoKeyIVConfig == 1U) { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /******************************* Init phase *********************************/ + /******************************* Init phase *********************************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - /***************************** Header phase *********************************/ + /***************************** Header phase *********************************/ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); } /* end of if (DoKeyIVConfig == 1U) */ /* Enable interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); @@ -3257,72 +3274,72 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) if (DoKeyIVConfig == 1U) { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - - /*************************** Init phase ************************************/ + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /*************************** Init phase ************************************/ - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); + hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); + hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - /************************ Header phase *************************************/ + /************************ Header phase *************************************/ - if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /************************ Payload phase ************************************/ + /************************ Payload phase ************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); - } + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); + } - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); -} /* if (DoKeyIVConfig == 1U) */ + } /* if (DoKeyIVConfig == 1U) */ if (hcryp->Size == 0U) { @@ -3335,13 +3352,15 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) else if (hcryp->Size >= 16U) { /* for STM32H7 below rev.B : Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: - Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise TAG is incorrectly generated */ + Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise + TAG is incorrectly generated */ /*DMA transfer must not include the last block in case of Size is not %16 */ wordsize = wordsize - (wordsize % 4U); /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize, + (uint32_t)(hcryp->pCrypOutBuffPtr)); } else /* length of input data is < 16 */ { @@ -3415,10 +3434,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUT; } - for (index=0; indexpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; hcryp->CrypOutCount++; @@ -3479,129 +3499,129 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if (DoKeyIVConfig == 1U) { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /********************** Init phase ******************************************/ + /********************** Init phase ******************************************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); #if defined (CRYP_VER_2_2) - { - /* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } -#else - if (hcryp->Version >= REV_ID_B) - { - /* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } - else /* data has to be swapped according to the DATATYPE */ - { - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + /* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/ + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } - else +#else + if (hcryp->Version >= REV_ID_B) { + /* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } - } -#endif - /* Get tick */ - tickstart = HAL_GetTick(); + else /* data has to be swapped according to the DATATYPE */ + { + if (hcryp->Init.DataType == CRYP_BYTE_SWAP) + { + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_BIT_SWAP) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + } +#endif /* CRYP_VER_2_2 */ + /* Get tick */ + tickstart = HAL_GetTick(); - /*Wait for the CRYPEN bit to be cleared*/ - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + /*Wait for the CRYPEN bit to be cleared*/ + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } } } - } - /************************* Header phase *************************************/ - /* Header block(B1) : associated data length expressed in bytes concatenated - with Associated Data (A)*/ + /************************* Header phase *************************************/ + /* Header block(B1) : associated data length expressed in bytes concatenated + with Associated Data (A)*/ - if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - /********************** Payload phase ***************************************/ + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /********************** Payload phase ***************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); - } + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); + } - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); -} /* if (DoKeyIVConfig == 1U) */ + } /* if (DoKeyIVConfig == 1U) */ if ((hcryp->Size % 16U) != 0U) { @@ -3713,10 +3733,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t { for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUT; } - for (index=0; indexpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; hcryp->CrypOutCount++; @@ -3726,9 +3747,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t #if !defined (CRYP_VER_2_2) else /* No NPBLB, Workaround to be used */ { - /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of - 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption - is selected, then the TAG message will be wrong.*/ + /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext + blocks size is multiple of 128 bits. If lthe size of the last block of payload is inferior to 128 bits, + when CCM decryption is selected, then the TAG message will be wrong.*/ CRYP_Workaround(hcryp, Timeout); } #endif /*End of not defined CRYP_VER_2_2*/ @@ -3775,92 +3796,92 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) /* Configure Key, IV and process message (header and payload) */ if (DoKeyIVConfig == 1U) { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /************ Init phase ************/ + /************ Init phase ************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DR*/ + /*Write the B0 packet into CRYP_DR*/ #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* for STM32H7 rev.B and above data has not to be swapped */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } -#if !defined (CRYP_VER_2_2) - else /* data has to be swapped according to the DATATYPE */ - { - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else { + /* for STM32H7 rev.B and above data has not to be swapped */ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } - } +#if !defined (CRYP_VER_2_2) + else /* data has to be swapped according to the DATATYPE */ + { + if (hcryp->Init.DataType == CRYP_BYTE_SWAP) + { + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_BIT_SWAP) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + } #endif /*End of not defined CRYP_VER_2_2*/ - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); -} /* end of if (DoKeyIVConfig == 1U) */ + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + } /* end of if (DoKeyIVConfig == 1U) */ /* Enable interrupts */ __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); @@ -3911,113 +3932,113 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) if (DoKeyIVConfig == 1U) { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; - /************************** Init phase **************************************/ + /************************** Init phase **************************************/ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; + /* Set the initialization vector (IV) with CTR1 information */ + hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; + hcryp->Instance->IV0RR = hcryp->Init.B0[1]; + hcryp->Instance->IV1LR = hcryp->Init.B0[2]; + hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); - /*Write the B0 packet into CRYP_DR*/ + /*Write the B0 packet into CRYP_DR*/ #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* for STM32H7 rev.B and above data has not to be swapped */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } -#if !defined (CRYP_VER_2_2) - else /* data has to be swapped according to the DATATYPE */ - { - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else { + /* for STM32H7 rev.B and above data has not to be swapped */ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } - } +#if !defined (CRYP_VER_2_2) + else /* data has to be swapped according to the DATATYPE */ + { + if (hcryp->Init.DataType == CRYP_BYTE_SWAP) + { + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP) + { + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); + hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); + } + else if (hcryp->Init.DataType == CRYP_BIT_SWAP) + { + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); + hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); + } + else + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } + } #endif /*End of not defined CRYP_VER_2_2*/ - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) + /*Wait for the CRYPEN bit to be cleared*/ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - /********************* Header phase *****************************************/ + /********************* Header phase *****************************************/ - if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } - /******************** Payload phase *****************************************/ + /******************** Payload phase *****************************************/ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); + /* Disable the CRYP peripheral */ + __HAL_CRYP_DISABLE(hcryp); #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); - } + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); + } - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); } /* if (DoKeyIVConfig == 1U) */ if (hcryp->Size == 0U) @@ -4030,12 +4051,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) } else if (hcryp->Size >= 16U) { - /* for STM32H7 below rev.B :: Size should be %4 otherwise Tag will be incorrectly generated for CCM Decryption, Workaround is implemented in polling mode*/ + /* for STM32H7 below rev.B :: Size should be %4 otherwise Tag will be incorrectly generated for CCM Decryption, + Workaround is implemented in polling mode*/ /*DMA transfer must not include the last block in case of Size is not %16 */ wordsize = wordsize - (wordsize % 4U); /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize, + (uint32_t)(hcryp->pCrypOutBuffPtr)); } else /* length of input data is < 16U */ { @@ -4109,10 +4132,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /*Read the output block from the output FIFO */ for (index = 0U; index < 4U; index++) { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ temp[index] = hcryp->Instance->DOUT; } - for (index=0; indexpCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; hcryp->CrypOutCount++; @@ -4167,7 +4191,7 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) && (negative == 0U)) { - if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U) + if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM) != 0x0U) { /* Write the input block in the IN FIFO */ hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); @@ -4196,13 +4220,14 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) { - /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + /* Read the output block from the Output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ for (i = 0U; i < 4U; i++) { temp[i] = hcryp->Instance->DOUT; } i = 0U; - while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U)) + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -4224,11 +4249,11 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /* Call output transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); #else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4237,59 +4262,59 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) } else if ((hcryp->Size % 16U) != 0U) { - /* Set padding only in case of input fifo interrupt */ - if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U) - { - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); + /* Set padding only in case of input fifo interrupt */ + if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM) != 0x0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); #if !defined (CRYP_VER_2_2) - if (hcryp->Version >= REV_ID_B) + if (hcryp->Version >= REV_ID_B) #endif /*End of not defined CRYP_VER_2_2*/ - { - /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */ - temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR; - - if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || - ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) { - /* Disable the CRYP */ - __HAL_CRYP_DISABLE(hcryp); + /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */ + temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR; - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20); + if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) || + ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Disable the CRYP */ + __HAL_CRYP_DISABLE(hcryp); - /* Enable CRYP to start the final phase */ - __HAL_CRYP_ENABLE(hcryp); + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20); + + /* Enable CRYP to start the final phase */ + __HAL_CRYP_ENABLE(hcryp); + } } - } - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } - /* Write the last input block in the IN FIFO */ - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0U; - loopcounter++; - } + /* Write the last input block in the IN FIFO */ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0U; + loopcounter++; + } - /* Disable the input FIFO Interrupt */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - } + /* Disable the input FIFO Interrupt */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); + } /*Read the output block from the output FIFO */ if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) @@ -4298,16 +4323,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { temp[i] = hcryp->Instance->DOUT; } - if (( (hcryp->Size)/4U)==0U) + if (((hcryp->Size) / 4U) == 0U) { - for (i = 0U; (uint16_t)i<((hcryp->Size)%4U); i++) + for (i = 0U; (uint16_t)i < ((hcryp->Size) % 4U); i++) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; } } i = 0U; - while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U)) + while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) { *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; hcryp->CrypOutCount++; @@ -4457,17 +4482,17 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /* Enter last bytes, padded with zeroes */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[size_in_bytes % 4U]; - hcryp->Instance->DIN = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - } + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[size_in_bytes % 4U]; + hcryp->Instance->DIN = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } } /* Wait for CCF IFEM to be raised */ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) @@ -4561,7 +4586,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); + loopcounter += 4U) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -4757,7 +4783,7 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) __HAL_CRYP_DISABLE(hcryp); /*Update CRYP_IV1R register and ALGOMODE*/ - hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1U); + hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); /* Enable CRYP to start the final phase */ @@ -4820,64 +4846,64 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* configured final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B) + if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_NO_SWAP) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U; + intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= 0xFFFF0000U; + intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= 0xFF000000U; + intermediate_data[lastwordsize - 1U] &= 0xFF000000U; } } - else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B) + else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_BYTE_SWAP) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U); + intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); } } - else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B) + else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_HALFWORD_SWAP) { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16); + intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); } } - else /*CRYP_DATATYPE_1B*/ + else /*CRYP_BIT_SWAP*/ { - if ((npblb %4U)==1U) + if ((npblb % 4U) == 1U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); } - if ((npblb %4U)==2U) + if ((npblb % 4U) == 2U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); } - if ((npblb %4U)==3U) + if ((npblb % 4U) == 3U) { - intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U); + intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c index d9b8a03c95..ddce86e43b 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cryp_ex.c @@ -115,7 +115,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; - /* Correct header length if Init.HeaderSize is actually in bytes */ + /* Correct header length if Init.HeaderSize is actually in bytes */ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) { headerlength /= 4U; @@ -178,28 +178,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u #if !defined (CRYP_VER_2_2) else/* data has to be swapped according to the DATATYPE */ { - if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + if (hcryp->Init.DataType == CRYP_BIT_SWAP) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength)); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength)); } - else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) + else if (hcryp->Init.DataType == CRYP_BYTE_SWAP) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __REV((uint32_t)(headerlength)); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __REV((uint32_t)(inputlength)); } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U); } - else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) + else if (hcryp->Init.DataType == CRYP_NO_SWAP) { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = (uint32_t)(headerlength); @@ -343,7 +343,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u #if !defined (CRYP_VER_2_2) else /* data has to be swapped according to the DATATYPE */ { - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) + if (hcryp->Init.DataType == CRYP_BYTE_SWAP) { hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); ctr0addr += 4U; @@ -353,7 +353,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u ctr0addr += 4U; hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) + else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP) { hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); ctr0addr += 4U; @@ -363,7 +363,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u ctr0addr += 4U; hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) + else if (hcryp->Init.DataType == CRYP_BIT_SWAP) { hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); ctr0addr += 4U; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c index 2425ee342f..ef9bc027a3 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dac.c @@ -1049,13 +1049,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } HAL_Delay(1); @@ -1070,13 +1074,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } HAL_Delay(1U); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c index 50971e783c..e1549e2473 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dcmi.c @@ -134,8 +134,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @addtogroup DCMI_Private_Defines + * @{ + */ #define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */ - +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -1022,7 +1027,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_ /** * @brief Unregister a DCMI Callback - * DCMI callabck is redirected to the weak predefined callback + * DCMI callback is redirected to the weak predefined callback * @param hdcmi DCMI handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -1106,6 +1111,10 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM } #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ +/** + * @} + */ + /** * @} */ @@ -1210,9 +1219,6 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) * @} */ -/** - * @} - */ #endif /* DCMI */ #endif /* HAL_DCMI_MODULE_ENABLED */ /** diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c index f83b8a5cc5..46069d52cd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm.c @@ -819,7 +819,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1109,7 +1109,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1342,7 +1342,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { return (int16_t) hdfsdm_channel->Instance->CHWDATAR; } @@ -1401,7 +1401,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Return DFSDM channel handle state */ return hdfsdm_channel->State; @@ -2393,7 +2393,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg; @@ -2810,7 +2810,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg; @@ -2841,7 +2841,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef *awdParam) + const DFSDM_Filter_AwdParamTypeDef *awdParam) { HAL_StatusTypeDef status = HAL_OK; @@ -2998,7 +2998,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg; @@ -3029,7 +3029,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg; @@ -3059,7 +3059,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg; uint32_t value; @@ -3413,7 +3413,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Return DFSDM filter handle state */ return hdfsdm_filter->State; @@ -3424,7 +3424,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { return hdfsdm_filter->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c index 4b48b0478f..286fd3ef89 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dfsdm_ex.c @@ -94,7 +94,7 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeD * @param PulsesValue Value of pulses to be skipped. * @retval HAL status. */ -HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue) +HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c index b8a17fcdf6..dada223e62 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c @@ -106,6 +106,9 @@ #ifdef HAL_DMA_MODULE_ENABLED /* Private types -------------------------------------------------------------*/ +/** @addtogroup DMA_Private_Types + * @{ + */ typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register */ @@ -118,6 +121,9 @@ typedef struct __IO uint32_t ISR; /*!< BDMA interrupt status register */ __IO uint32_t IFCR; /*!< BDMA interrupt flag clear register */ } BDMA_Base_Registers; +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c index 293a48ac16..ecdacb216e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dsi.c @@ -1835,6 +1835,85 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no ULPS exit or request on data lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* ULPS Request on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_URDL; @@ -1898,6 +1977,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Exit ULPS on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_UEDL; @@ -1947,6 +2078,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1967,6 +2153,86 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no ULPS exit or request on both data and clock lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* Clock lane configuration: no more HS request */ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; @@ -1979,7 +2245,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until all active lanes exit ULPM */ + /* Wait until all active lanes enter ULPM */ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) @@ -2039,9 +2305,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \ + DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \ + DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Turn on the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -2114,6 +2415,62 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Restore clock lane configuration to HS */ hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c index 21faccde8d..9f122a49bd 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dts.c @@ -76,6 +76,12 @@ */ #define TS_TIMEOUT_MS (5UL) +/* @brief DTS factory temperatures + * @note Unit: degree Celsius + */ +#define DTS_FACTORY_TEMPERATURE1 (30UL) +#define DTS_FACTORY_TEMPERATURE2 (130UL) + /** * @} */ @@ -83,9 +89,6 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) -static void DTS_ResetCallback(DTS_HandleTypeDef *hdts); -#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ /* Exported functions --------------------------------------------------------*/ /** @defgroup DTS_Exported_Functions DTS Exported Functions @@ -131,8 +134,13 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts) if (hdts->State == HAL_DTS_STATE_RESET) { #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - DTS_ResetCallback(hdts); + /* Reset the DTS callback to the legacy weak callbacks */ + hdts->EndCallback = HAL_DTS_EndCallback; /* End measure Callback */ + hdts->LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */ + hdts->HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */ + hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */ + hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */ + hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */ if (hdts->MspInitCallback == NULL) { @@ -277,6 +285,180 @@ __weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts) */ } +#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user DTS callback to be used instead of the weak predefined callback. + * @param hdts DTS handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID. + * @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID. + * @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID. + * @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID. + * @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID, + pDTS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + if (pCallback == NULL) + { + /* Update status */ + status = HAL_ERROR; + } + else + { + if (hdts->State == HAL_DTS_STATE_READY) + { + switch (CallbackID) + { + case HAL_DTS_MEAS_COMPLETE_CB_ID : + hdts->EndCallback = pCallback; + break; + case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID : + hdts->AsyncEndCallback = pCallback; + break; + case HAL_DTS_LOW_THRESHOLD_CB_ID : + hdts->LowCallback = pCallback; + break; + case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID : + hdts->AsyncLowCallback = pCallback; + break; + case HAL_DTS_HIGH_THRESHOLD_CB_ID : + hdts->HighCallback = pCallback; + break; + case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID : + hdts->AsyncHighCallback = pCallback; + break; + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = pCallback; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = pCallback; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else if (hdts->State == HAL_DTS_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = pCallback; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = pCallback; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Unregister a user DTS callback. + * DTS callback is redirected to the weak predefined callback. + * @param hdts DTS handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID. + * @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID. + * @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID. + * @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID. + * @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID. + * @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef *hdts, + HAL_DTS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hdts->State == HAL_DTS_STATE_READY) + { + switch (CallbackID) + { + case HAL_DTS_MEAS_COMPLETE_CB_ID : + hdts->EndCallback = HAL_DTS_EndCallback; + break; + case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID : + hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback; + break; + case HAL_DTS_LOW_THRESHOLD_CB_ID : + hdts->LowCallback = HAL_DTS_LowCallback; + break; + case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID : + hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback; + break; + case HAL_DTS_HIGH_THRESHOLD_CB_ID : + hdts->HighCallback = HAL_DTS_HighCallback; + break; + case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID : + hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback; + break; + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = HAL_DTS_MspInit; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = HAL_DTS_MspDeInit; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else if (hdts->State == HAL_DTS_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DTS_MSPINIT_CB_ID : + hdts->MspInitCallback = HAL_DTS_MspInit; + break; + case HAL_DTS_MSPDEINIT_CB_ID : + hdts->MspDeInitCallback = HAL_DTS_MspDeInit; + break; + default : + /* Update status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update status */ + status = HAL_ERROR; + } + + /* Return function status */ + return status; +} +#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ + /** * @} */ @@ -538,11 +720,11 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe if (t0_temp == 0UL) { - t0_temp = 30UL; /* 30 deg C */ + t0_temp = DTS_FACTORY_TEMPERATURE1; /* 30 deg C */ } else if (t0_temp == 1UL) { - t0_temp = 110UL; /* 110 deg C */ + t0_temp = DTS_FACTORY_TEMPERATURE2; /* 130 deg C */ } else { @@ -785,33 +967,6 @@ HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts) * @} */ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DTS_Private_Functions DTS Private Functions - * @{ - */ -#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param hdts pointer to a DTS_HandleTypeDef structure that contains - * the configuration information for DTS module. - * @retval None - */ -static void DTS_ResetCallback(DTS_HandleTypeDef *hdts) -{ - /* Reset the DTS callback to the legacy weak callbacks */ - hdts->DTS_EndCallback = HAL_DTS_EndCallback; /* End measure Callback */ - hdts->DTS_LowCallback = HAL_DTS_LowCallback; /* low threshold Callback */ - hdts->DTS_HighCallback = HAL_DTS_HighCallback; /* high threshold Callback */ - hdts->DTS_AsyncEndCallback = HAL_DTS_AsyncEndCallback; /* Asynchronous end of measure Callback */ - hdts->DTS_AsyncLowCallback = HAL_DTS_AsyncLowCallback; /* Asynchronous low threshold Callback */ - hdts->DTS_AsyncHighCallback = HAL_DTS_AsyncHighCallback; /* Asynchronous high threshold Callback */ -} -#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */ -/** - * @} - */ - /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c index 1b21dd4b34..27d5518899 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_eth.c @@ -194,34 +194,34 @@ /** @addtogroup ETH_Private_Constants ETH Private Constants * @{ */ -#define ETH_MACCR_MASK ((uint32_t)0xFFFB7F7CU) -#define ETH_MACECR_MASK ((uint32_t)0x3F077FFFU) -#define ETH_MACPFR_MASK ((uint32_t)0x800007FFU) -#define ETH_MACWTR_MASK ((uint32_t)0x0000010FU) -#define ETH_MACTFCR_MASK ((uint32_t)0xFFFF00F2U) -#define ETH_MACRFCR_MASK ((uint32_t)0x00000003U) -#define ETH_MTLTQOMR_MASK ((uint32_t)0x00000072U) -#define ETH_MTLRQOMR_MASK ((uint32_t)0x0000007BU) - -#define ETH_DMAMR_MASK ((uint32_t)0x00007802U) -#define ETH_DMASBMR_MASK ((uint32_t)0x0000D001U) -#define ETH_DMACCR_MASK ((uint32_t)0x00013FFFU) -#define ETH_DMACTCR_MASK ((uint32_t)0x003F1010U) -#define ETH_DMACRCR_MASK ((uint32_t)0x803F0000U) -#define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \ - ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \ - ETH_MACPCSR_RWKPFE) +#define ETH_MACCR_MASK 0xFFFB7F7CU +#define ETH_MACECR_MASK 0x3F077FFFU +#define ETH_MACPFR_MASK 0x800007FFU +#define ETH_MACWTR_MASK 0x0000010FU +#define ETH_MACTFCR_MASK 0xFFFF00F2U +#define ETH_MACRFCR_MASK 0x00000003U +#define ETH_MTLTQOMR_MASK 0x00000072U +#define ETH_MTLRQOMR_MASK 0x0000007BU + +#define ETH_DMAMR_MASK 0x00007802U +#define ETH_DMASBMR_MASK 0x0000D001U +#define ETH_DMACCR_MASK 0x00013FFFU +#define ETH_DMACTCR_MASK 0x003F1010U +#define ETH_DMACRCR_MASK 0x803F0000U +#define ETH_MACPCSR_MASK (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \ + ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \ + ETH_MACPCSR_RWKPFE) /* Timeout values */ #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \ ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\ ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE)) -#define ETH_MACTSCR_MASK ((uint32_t)0x0087FF2FU) +#define ETH_MACTSCR_MASK 0x0087FF2FU -#define ETH_MACSTSUR_VALUE ((uint32_t)0xFFFFFFFFU) -#define ETH_MACSTNUR_VALUE ((uint32_t)0xBB9ACA00U) -#define ETH_SEGMENT_SIZE_DEFAULT ((uint32_t)0x218U) +#define ETH_MACSTSUR_VALUE 0xFFFFFFFFU +#define ETH_MACSTNUR_VALUE 0xBB9ACA00U +#define ETH_SEGMENT_SIZE_DEFAULT 0x218U /** * @} */ @@ -1421,7 +1421,7 @@ HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) { #ifdef HAL_ETH_USE_PTP /* Disable Ptp transmission */ - CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, ((uint32_t)0x40000000U)); + CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U)); /* Get timestamp low */ timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; @@ -3334,6 +3334,12 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ heth->EEECallback = HAL_ETH_EEECallback; /* Legacy weak EEECallback */ heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */ +#ifdef HAL_ETH_USE_PTP + heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */ +#endif /* HAL_ETH_USE_PTP */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */ } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c index da129234b0..c9090f75aa 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c @@ -471,7 +471,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL]; - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U); + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c index b136a94683..926865f159 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c @@ -108,7 +108,13 @@ */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ FLASH_ProcessTypeDef pFlash; +/** + * @} + */ /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c index dd2e1ec87a..72e77ea6a8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fmac.c @@ -528,6 +528,8 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac) /** * @brief Register a User FMAC Callback. * @note The User FMAC Callback is to be used instead of the weak predefined callback. + * @note The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register + * callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module. * @param CallbackID ID of the callback to be registered. @@ -562,7 +564,6 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ return HAL_ERROR; } - __HAL_LOCK(hfmac); if (hfmac->State == HAL_FMAC_STATE_READY) { @@ -643,14 +644,14 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_ status = HAL_ERROR; } - __HAL_UNLOCK(hfmac); - return status; } /** * @brief Unregister a FMAC CallBack. * @note The FMAC callback is redirected to the weak predefined callback. + * @note The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register + * callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID. * @param hfmac pointer to a FMAC_HandleTypeDef structure that contains * the configuration information for FMAC module * @param CallbackID ID of the callback to be unregistered. @@ -676,8 +677,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA return HAL_ERROR; } - __HAL_LOCK(hfmac); - if (hfmac->State == HAL_FMAC_STATE_READY) { switch (CallbackID) @@ -760,8 +759,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA status = HAL_ERROR; } - __HAL_UNLOCK(hfmac); - return status; } #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c index 5f4a682d15..48abbcd3fa 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hash.c @@ -1650,7 +1650,7 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; uint32_t inputaddr; uint32_t buffersize; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c index 6182ab4f2a..d0fe63a0b1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hcd.c @@ -197,13 +197,8 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to32K * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, + uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef status; @@ -226,13 +221,9 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].speed = speed; - status = USB_HC_Init(hhcd->Instance, - ch_num, - epnum, - dev_address, - speed, - ep_type, - mps); + status = USB_HC_Init(hhcd->Instance, ch_num, epnum, + dev_address, speed, ep_type, mps); + __HAL_UNLOCK(hhcd); return status; @@ -250,7 +241,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) HAL_StatusTypeDef status = HAL_OK; __HAL_LOCK(hhcd); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + (void)USB_HC_Halt(hhcd->Instance, ch_num); __HAL_UNLOCK(hhcd); return status; @@ -541,8 +532,11 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) (void)USB_FlushTxFifo(USBx, 0x10U); (void)USB_FlushRxFifo(USBx); - /* Restore FS Clock */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + { + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) @@ -1174,82 +1168,78 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; - uint32_t tmpreg; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) - { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); - hhcd->hc[ch_num].state = HC_BBLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - hhcd->hc[ch_num].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { /* ... */ } - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { + /* Clear any pending ACK IT */ + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \ - (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } - hhcd->hc[ch_num].state = HC_XFRC; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) { - USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[ch_num].urb_state = URB_DONE; + USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else @@ -1259,96 +1249,129 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 1U) { - if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U) + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].toggle_in ^= 1U; + hhcd->hc[chnum].toggle_in ^= 1U; } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) { - if (hhcd->hc[ch_num].state == HC_XFRC) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) + { + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + } + else if (hhcd->hc[chnum].state == HC_ACK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + } } - else if (hhcd->hc[ch_num].state == HC_BBLERR) + else if (hhcd->hc[chnum].state == HC_BBLERR) { - hhcd->hc[ch_num].ErrCnt++; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - /* ... */ + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + hhcd->hc[chnum].ErrCnt = 0U; + + (void)USB_HC_Halt(hhcd->Instance, chnum); + } + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) { - hhcd->hc[ch_num].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].state = HC_NAK; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_NAK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } } else { /* ... */ } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } else { @@ -1367,177 +1390,185 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)chnum; uint32_t tmpreg; uint32_t num_packets; - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - if (hhcd->hc[ch_num].do_ping == 1U) + if (hhcd->hc[chnum].do_ping == 1U) { - hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + (void)USB_HC_Halt(hhcd->Instance, chnum); } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) { - hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[chnum].ErrCnt = 0U; /* transaction completed with NYET state, update do ping state */ - if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].do_ping = 1U; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); - hhcd->hc[ch_num].state = HC_XFRC; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) { - hhcd->hc[ch_num].state = HC_NYET; - hhcd->hc[ch_num].do_ping = 1U; - hhcd->hc[ch_num].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + hhcd->hc[chnum].state = HC_NYET; + hhcd->hc[chnum].do_ping = 1U; + hhcd->hc[chnum].ErrCnt = 0U; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) { - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - hhcd->hc[ch_num].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, chnum); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].state = HC_NAK; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; - if (hhcd->hc[ch_num].do_ping == 0U) + if (hhcd->hc[chnum].do_ping == 0U) { - if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH) + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) { - hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[chnum].do_ping = 1U; } } - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + hhcd->hc[chnum].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); } else { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) { - hhcd->hc[ch_num].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + (void)USB_HC_Halt(hhcd->Instance, chnum); + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) + else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) { - if (hhcd->hc[ch_num].state == HC_XFRC) + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); + if (hhcd->hc[chnum].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || - (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) { if (hhcd->Init.dma_enable == 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } - if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; if ((num_packets & 1U) != 0U) { - hhcd->hc[ch_num].toggle_out ^= 1U; + hhcd->hc[chnum].toggle_out ^= 1U; } } } } - else if (hhcd->hc[ch_num].state == HC_NAK) + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + } + else if (hhcd->hc[chnum].state == HC_NAK) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } - else if (hhcd->hc[ch_num].state == HC_NYET) + else if (hhcd->hc[chnum].state == HC_NYET) { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; } - else if (hhcd->hc[ch_num].state == HC_STALL) + else if (hhcd->hc[chnum].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; } - else if ((hhcd->hc[ch_num].state == HC_XACTERR) || - (hhcd->hc[ch_num].state == HC_DATATGLERR)) + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) { - hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 2U) + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) { - hhcd->hc[ch_num].ErrCnt = 0U; - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; } else { - hhcd->hc[ch_num].urb_state = URB_NOTREADY; + hhcd->hc[chnum].urb_state = URB_NOTREADY; /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + USBx_HC(chnum)->HCCHAR = tmpreg; } } else { - /* ... */ + return; } - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); #else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else @@ -1560,10 +1591,10 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) uint32_t GrxstspReg; uint32_t xferSizePktCnt; uint32_t tmpreg; - uint32_t ch_num; + uint32_t chnum; GrxstspReg = hhcd->Instance->GRXSTSP; - ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; @@ -1571,33 +1602,33 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) { - if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len) + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) { (void)USB_ReadPacket(hhcd->Instance, - hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); /* manage multiple Xfer */ - hhcd->hc[ch_num].xfer_buff += pktcnt; - hhcd->hc[ch_num].xfer_count += pktcnt; + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; /* get transfer size packet count */ - xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; - if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) { /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg = USBx_HC(chnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - hhcd->hc[ch_num].toggle_in ^= 1U; + USBx_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; } } else { - hhcd->hc[ch_num].urb_state = URB_ERROR; + hhcd->hc[chnum].urb_state = URB_ERROR; } } break; @@ -1652,7 +1683,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { - if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) + if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) { if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { @@ -1667,7 +1698,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if (hhcd->Init.speed == HCD_SPEED_FULL) { - USBx_HOST->HFIR = 60000U; + USBx_HOST->HFIR = HFIR_60_MHZ; } } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c index 56a3d49114..2e11610e89 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hrtim.c @@ -424,18 +424,18 @@ static uint32_t TimerIdxToTimerId[] = * @{ */ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef * pTimerCfg); static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef * pTimerCfg); static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, @@ -446,29 +446,29 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef * pOutputCfg); static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef * pEventCfg); + const HRTIM_EventCfgTypeDef * pEventCfg); static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Event); -static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel); -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim, +static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx); -static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim, - DMA_HandleTypeDef * hdma); +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, + const DMA_HandleTypeDef * hdma); static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx); @@ -743,7 +743,7 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim) */ HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) { /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -1205,7 +1205,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel, - HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) + const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; HRTIM_OutputCfgTypeDef OutputCfg; @@ -1825,7 +1825,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t PWMChannel, - HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) + const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; uint32_t hrtim_timcr; @@ -2491,7 +2491,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureChannel, - HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) + const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg) { HRTIM_EventCfgTypeDef EventCfg; @@ -3146,7 +3146,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OnePulseChannel, - HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) + const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg) { HRTIM_OutputCfgTypeDef OutputCfg; HRTIM_EventCfgTypeDef EventCfg; @@ -3568,7 +3568,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim, * controller */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, - HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) + const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg) { uint32_t hrtim_bmcr; @@ -3649,7 +3649,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef* pEventCfg) + const HRTIM_EventCfgTypeDef* pEventCfg) { /* Check parameters */ assert_param(IS_HRTIM_EVENT(Event)); @@ -3736,7 +3736,7 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Fault, - HRTIM_FaultCfgTypeDef* pFaultCfg) + const HRTIM_FaultCfgTypeDef* pFaultCfg) { uint32_t hrtim_fltinr1; uint32_t hrtim_fltinr2; @@ -3948,7 +3948,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t ADCTrigger, - HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) + const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg) { uint32_t hrtim_cr1; @@ -4100,7 +4100,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef * pTimerCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4202,7 +4202,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Event, - HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) + const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx)); @@ -4331,7 +4331,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt */ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) + const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg) { uint32_t hrtim_dtr; @@ -4396,7 +4396,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim, */ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) + const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg) { uint32_t hrtim_chpr; @@ -4422,9 +4422,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim, hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW); /* Update the HRTIM registers */ - MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | - HRTIM_CHPR_STRPW) , - hrtim_chpr); + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, + (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW), + hrtim_chpr); hhrtim->State = HAL_HRTIM_STATE_READY; @@ -4581,7 +4581,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - HRTIM_CompareCfgTypeDef* pCompareCfg) + const HRTIM_CompareCfgTypeDef* pCompareCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); @@ -4782,7 +4782,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - HRTIM_CaptureCfgTypeDef* pCaptureCfg) + const HRTIM_CaptureCfgTypeDef* pCaptureCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger)); @@ -4868,7 +4868,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef * pOutputCfg) { /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -5928,7 +5928,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval HAL state */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim) +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim) { /* Return HRTIM state */ return hhrtim->State; @@ -5950,7 +5950,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim) * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @retval Captured value */ -uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit) { @@ -5978,11 +5978,6 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, default: { captured_value = 0xFFFFFFFFUL; - - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); break; } @@ -6018,11 +6013,11 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, * @note Returned output level is taken before the output stage (chopper, * polarity). */ -uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t output_level = (uint32_t)RESET; + uint32_t output_level; /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -6066,20 +6061,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, default: { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - + output_level = 0xFFFFFFFFUL; break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return (uint32_t)HAL_ERROR; - } - return output_level; } @@ -6107,11 +6093,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Output state */ -uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t output_bit = (uint32_t)RESET; + uint32_t output_bit; uint32_t output_state; /* Check parameters */ @@ -6185,20 +6171,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, default: { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - + output_bit = 0UL; break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return (uint32_t)HAL_ERROR; - } - if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET) { /* Output is enabled: output in RUN state (whatever output disable status is)*/ @@ -6246,11 +6223,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Delayed protection status */ -uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output) { - uint32_t delayed_protection_status = (uint32_t)RESET; + uint32_t delayed_protection_status; /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output)); @@ -6298,20 +6275,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, default: { - hhrtim->State = HAL_HRTIM_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hhrtim); - + delayed_protection_status = 0xFFFFFFFFUL; break; } } - if(hhrtim->State == HAL_HRTIM_STATE_ERROR) - { - return (uint32_t)HAL_ERROR; - } - return delayed_protection_status; } @@ -6320,7 +6288,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim, * @param hhrtim pointer to HAL HRTIM handle * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim) +uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim) { uint32_t burst_mode_status; @@ -6343,7 +6311,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim) * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Burst mode controller status */ -uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { uint32_t current_pushpull_status; @@ -6371,7 +6339,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERINDEX_TIMER_E for timer E * @retval Idle Push Pull Status */ -uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { uint32_t idle_pushpull_status; @@ -7501,7 +7469,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @retval None */ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) { uint32_t hrtim_mcr; @@ -7530,8 +7498,8 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim, * @retval None */ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, - uint32_t TimerIdx , - HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) + uint32_t TimerIdx , + const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg) { uint32_t hrtim_timcr; @@ -7559,7 +7527,7 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim, * @retval None */ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, - HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef * pTimerCfg) { uint32_t hrtim_mcr; uint32_t hrtim_bmcr; @@ -7614,7 +7582,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, - HRTIM_TimerCfgTypeDef * pTimerCfg) + const HRTIM_TimerCfgTypeDef * pTimerCfg) { uint32_t hrtim_timcr; uint32_t hrtim_timfltr; @@ -7866,7 +7834,7 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim, static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t Output, - HRTIM_OutputCfgTypeDef * pOutputCfg) + const HRTIM_OutputCfgTypeDef * pOutputCfg) { uint32_t hrtim_outr; uint32_t hrtim_dtr; @@ -7956,7 +7924,7 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim, uint32_t Event, - HRTIM_EventCfgTypeDef *pEventCfg) + const HRTIM_EventCfgTypeDef *pEventCfg) { uint32_t hrtim_eecr1; uint32_t hrtim_eecr2; @@ -8220,7 +8188,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval Interrupt to enable or disable */ -static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8326,7 +8294,7 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2 * @retval DMA request to enable or disable */ -static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, +static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx, uint32_t OCChannel) { @@ -8413,7 +8381,7 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim, return dma_request; } -static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim, +static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL; @@ -8463,8 +8431,8 @@ static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * return hdma; } -static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim, - DMA_HandleTypeDef * hdma) +static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim, + const DMA_HandleTypeDef * hdma) { uint32_t timed_idx = 0xFFFFFFFFU; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c index b36425b005..c9ad0e79d5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c @@ -438,10 +438,14 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -707,6 +711,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) /** * @brief Register a User I2C Callback * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be registered @@ -737,8 +743,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -827,14 +831,14 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } /** * @brief Unregister an I2C Callback * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param CallbackID ID of the callback to be unregistered @@ -857,9 +861,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { switch (CallbackID) @@ -947,8 +948,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -971,8 +970,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hi2c); if (HAL_I2C_STATE_READY == hi2c->State) { @@ -987,8 +984,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1003,9 +998,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hi2c); - if (HAL_I2C_STATE_READY == hi2c->State) { hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ @@ -1019,8 +1011,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hi2c); return status; } @@ -1389,6 +1379,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData return HAL_ERROR; } + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + /* Clear ADDR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); @@ -1785,6 +1788,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_IT; + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2183,67 +2200,99 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->XferISR = I2C_Slave_ISR_DMA; - if (hi2c->hdmatx != NULL) + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; - /* Enable the DMA stream or channel depends on Instance */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); + hi2c->XferCount--; + hi2c->XferSize--; } - else + + if (hi2c->XferCount != 0U) { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - return HAL_ERROR; - } + /* Enable the DMA stream or channel depends on Instance */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + return HAL_ERROR; + } - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } } else { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); } return HAL_OK; @@ -2647,9 +2696,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2669,9 +2715,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2680,30 +2723,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2741,9 +2783,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); @@ -2763,9 +2802,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2774,29 +2810,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; - if (hi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2809,7 +2845,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre /* possible to enable all of these */ /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); return HAL_OK; } @@ -2833,8 +2869,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2856,9 +2890,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -2867,28 +2898,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) - != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } if (hi2c->hdmatx != NULL) { @@ -2923,12 +2962,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2936,11 +2971,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -2980,8 +3015,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3003,9 +3036,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Process Locked */ __HAL_LOCK(hi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; @@ -3014,25 +3044,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->pBuffPtr = pData; hi2c->XferCount = Size; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; if (hi2c->XferCount > MAX_NBYTE_SIZE) { hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; } else { hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); } if (hi2c->hdmarx != NULL) @@ -3068,11 +3108,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -3080,11 +3117,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); } else { @@ -3327,6 +3364,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); return HAL_OK; @@ -3773,6 +3814,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3832,7 +3876,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3869,6 +3914,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3903,7 +3950,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA RX */ @@ -3925,7 +3972,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ if (hi2c->hdmatx != NULL) { /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; /* Abort DMA TX */ @@ -4010,7 +4057,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4050,7 +4098,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - /* Check the parameters */ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) @@ -4109,7 +4160,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t hi2c->XferOptions = XferOptions; hi2c->XferISR = I2C_Slave_ISR_IT; - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4146,6 +4198,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4287,7 +4341,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t return HAL_ERROR; } - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4878,6 +4933,143 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -5159,6 +5351,145 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui return HAL_OK; } +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + /** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -6021,12 +6352,29 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } hi2c->XferISR = NULL; } @@ -6396,13 +6744,16 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } } } } @@ -6433,14 +6784,17 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6469,14 +6823,17 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6543,13 +6900,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6606,14 +6966,11 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + error_code |= HAL_I2C_ERROR_TIMEOUT; status = HAL_ERROR; + + break; } } } @@ -6717,14 +7074,14 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin /* Declaration of tmp to prevent undefined behavior of volatile usage */ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP)), tmp); + I2C_CR2_START | I2C_CR2_STOP)), tmp); } /** @@ -6785,6 +7142,12 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c index ac9a8dc51c..ea7fe37097 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2s.c @@ -192,7 +192,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Define I2S Private Define + * @{ + */ #define I2S_TIMEOUT 0xFFFFUL +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -212,7 +218,7 @@ static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s); static void I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s); static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s); static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, - uint32_t Timeout); + uint32_t Tickstart, uint32_t Timeout); /** * @} */ @@ -803,11 +809,12 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca * between Master and Slave(example: audio streaming). * @retval HAL status */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout) { #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR)); #endif /* __GNUC__ */ + uint32_t tickstart; if ((pData == NULL) || (Size == 0UL)) { @@ -822,10 +829,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /* Process Locked */ __HAL_LOCK(hi2s); + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; + hi2s->pTxBuffPtr = (const uint16_t *)pData; hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; @@ -846,7 +856,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin /* Wait until TXP flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK) + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK) { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); @@ -860,7 +870,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) { /* Transmit data in 32 Bit mode */ - hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr); + hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr); hi2s->pTxBuffPtr += 2; hi2s->TxXferCount--; } @@ -868,9 +878,9 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin { /* Transmit data in 16 Bit mode */ #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr); #else - *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr); + *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr); #endif /* __GNUC__ */ hi2s->pTxBuffPtr++; @@ -878,7 +888,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin } /* Wait until TXP flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK) + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK) { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); @@ -925,6 +935,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint #if defined (__GNUC__) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR)); #endif /* __GNUC__ */ + uint32_t tickstart; if ((pData == NULL) || (Size == 0UL)) { @@ -939,6 +950,9 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint /* Process Locked */ __HAL_LOCK(hi2s); + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_RX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; @@ -965,7 +979,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint while (hi2s->RxXferCount > 0UL) { /* Wait until RXP flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, Timeout) != HAL_OK) + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, tickstart, Timeout) != HAL_OK) { /* Set the error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); @@ -1026,7 +1040,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * @retval HAL status */ -HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout) { uint32_t tmp_TxXferCount; @@ -1056,7 +1070,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; - hi2s->pTxBuffPtr = pTxData; + hi2s->pTxBuffPtr = (const uint16_t *)pTxData; hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; hi2s->pRxBuffPtr = pRxData; @@ -1085,7 +1099,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B)) { /* Transmit data in 32 Bit mode */ - hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr); + hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr); hi2s->pTxBuffPtr += 2; tmp_TxXferCount--; } @@ -1093,9 +1107,9 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p { /* Transmit data in 16 Bit mode */ #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr); #else - *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr); + *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr); #endif /* __GNUC__ */ hi2s->pTxBuffPtr++; @@ -1175,7 +1189,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p * between Master and Slave(example: audio streaming). * @retval HAL status */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size) { if ((pData == NULL) || (Size == 0UL)) { @@ -1193,7 +1207,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = (uint16_t *)pData; + hi2s->pTxBuffPtr = (const uint16_t *)pData; hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; @@ -1325,7 +1339,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u * between Master and Slave(example: audio streaming). * @retval HAL status */ -HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) { if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) @@ -1341,8 +1355,8 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t /* Process Locked */ __HAL_LOCK(hi2s); - hi2s->pTxBuffPtr = pTxData; - hi2s->pRxBuffPtr = pRxData; + hi2s->pTxBuffPtr = (const uint16_t *)pTxData; + hi2s->pRxBuffPtr = pRxData; hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; @@ -1403,7 +1417,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t * between Master and Slave(example: audio streaming). * @retval HAL status */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -1423,7 +1437,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Set state and reset error code */ hi2s->State = HAL_I2S_STATE_BUSY_TX; hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; + hi2s->pTxBuffPtr = (const uint16_t *)pData; hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; @@ -1537,7 +1551,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->State = HAL_I2S_STATE_READY; errorcode = HAL_ERROR; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + return errorcode; } /* Check if the I2S Rx request is already enabled */ @@ -1576,7 +1590,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, * between Master and Slave(example: audio streaming). * @retval HAL status */ -HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, +HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -1595,7 +1609,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ /* Process Locked */ __HAL_LOCK(hi2s); - hi2s->pTxBuffPtr = pTxData; + hi2s->pTxBuffPtr = (const uint16_t *)pTxData; hi2s->pRxBuffPtr = pRxData; hi2s->TxXferSize = Size; @@ -1646,7 +1660,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_ hi2s->State = HAL_I2S_STATE_READY; errorcode = HAL_ERROR; __HAL_UNLOCK(hi2s); - return HAL_ERROR; + return errorcode; } /* Check if the I2S Rx request is already enabled */ @@ -2104,7 +2118,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval HAL state */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s) { return hi2s->State; } @@ -2115,7 +2129,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } @@ -2123,7 +2137,13 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) * @} */ +/** + * @} + */ +/** @addtogroup I2S_Private_Functions + * @{ + */ /** * @brief DMA I2S transmit process complete callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains @@ -2227,6 +2247,21 @@ static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* if DMA is configured in DMA_NORMAL Mode */ + if (hdma->Init.Mode == DMA_NORMAL) + { + /* Disable Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN); + hi2s->TxXferCount = (uint16_t) 0UL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN); + hi2s->RxXferCount = (uint16_t)0UL; + + /* Updated HAL State */ + hi2s->State = HAL_I2S_STATE_READY; + } + /* Call user TxRx complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) hi2s->TxRxCpltCallback(hi2s); @@ -2293,9 +2328,9 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s) #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR)); - *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr); #else - *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr); + *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr); #endif /* __GNUC__ */ hi2s->pTxBuffPtr++; hi2s->TxXferCount--; @@ -2308,13 +2343,14 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s) if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX)) { hi2s->State = HAL_I2S_STATE_READY; - } - /* Call user Tx complete callback */ + + /* Call user Tx complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) - hi2s->TxCpltCallback(hi2s); + hi2s->TxCpltCallback(hi2s); #else - HAL_I2S_TxCpltCallback(hi2s); + HAL_I2S_TxCpltCallback(hi2s); #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } } } @@ -2327,7 +2363,7 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s) static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s) { /* Transmit data */ - hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr); + hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr); hi2s->pTxBuffPtr += 2; hi2s->TxXferCount--; @@ -2339,13 +2375,14 @@ static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s) if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX)) { hi2s->State = HAL_I2S_STATE_READY; - } - /* Call user Tx complete callback */ + + /* Call user Tx complete callback */ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL) - hi2s->TxCpltCallback(hi2s); + hi2s->TxCpltCallback(hi2s); #else - HAL_I2S_TxCpltCallback(hi2s); + HAL_I2S_TxCpltCallback(hi2s); #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ + } } } @@ -2461,23 +2498,19 @@ static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @param Flag Flag checked * @param State Value of the flag expected + * @param Tickstart Tick start value * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, - uint32_t Timeout) + uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set to status*/ while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0UL)) { /* Set the I2S State ready */ hi2s->State = HAL_I2S_STATE_READY; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c index d2874c274f..54a21e0eb5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_irda.c @@ -463,6 +463,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) /** * @brief Register a User IRDA Callback * To be used instead of the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -491,8 +493,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hirda); if (hirda->gState == HAL_IRDA_STATE_READY) { @@ -577,15 +577,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } /** * @brief Unregister an IRDA callback * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID * @param hirda irda handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -605,9 +604,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hirda); - if (HAL_IRDA_STATE_READY == hirda->gState) { switch (CallbackID) @@ -693,9 +689,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hirda); - return status; } #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ @@ -2192,7 +2185,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ uint32_t temp1; @@ -2209,7 +2202,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } @@ -2307,11 +2300,13 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) break; case IRDA_CLOCKSOURCE_PLL2Q: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, + hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_PLL3Q: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, + hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_CSI: tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c index afaaa3eeb8..5a5016f0c6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_lptim.c @@ -1748,7 +1748,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1761,7 +1761,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1774,7 +1774,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2069,9 +2069,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2142,9 +2139,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } @@ -2170,9 +2164,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hlptim); - if (hlptim->State == HAL_LPTIM_STATE_READY) { switch (CallbackID) @@ -2254,9 +2245,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hlptim); - return status; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c index cbead1ee7b..7d20bfa2b5 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c @@ -178,7 +178,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup LTDC_Private_Define LTDC Private Define + * @{ + */ #define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c index d80bc56372..dc7b722acf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdios.c @@ -142,18 +142,29 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup MDIOS_Private_Define MDIOS Private Define + * @{ + */ #define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8) #define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU) #define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF)) #define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U) #define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U) - +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +/** @defgroup MDIOS_Private_Functions MDIOS Private Functions + * @{ + */ static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios); +/** + * @} + */ #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ /* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -434,7 +445,7 @@ HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MD /** * @brief Unregister an MDIOS Callback - * MDIOS callabck is redirected to the weak predefined callback + * MDIOS callback is redirected to the weak predefined callback * @param hmdios mdios handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -931,6 +942,9 @@ HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) */ #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) +/** @addtogroup MDIOS_Private_Functions + * @{ + */ static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios) { /* Init the MDIOS Callback settings */ @@ -939,11 +953,10 @@ static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios) hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; /* Legacy weak ErrorCallback */ hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; /* Legacy weak WakeUpCallback */ } -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - /** * @} */ +#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ #endif /* HAL_MDIOS_MODULE_ENABLED */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c index 880a9e828b..0aa5d66313 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mmc.c @@ -456,8 +456,15 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* wait 74 Cycles: required power up waiting time before starting the MMC initialization sequence */ - sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); - HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); @@ -594,7 +601,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, - uint32_t NumberOfBlocks, uint32_t Timeout) + uint32_t NumberOfBlocks, + uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -789,7 +797,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; @@ -799,7 +807,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u uint32_t data; uint32_t dataremaining; uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; + const uint8_t *tempbuff = pData; if (NULL == pData) { @@ -985,8 +993,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, - uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -1098,7 +1106,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1212,8 +1220,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, - uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -1327,7 +1335,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1865,6 +1873,9 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) /** * @brief Register a User MMC Callback * To be used instead of the weak (surcharged) predefined callback + * @note The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in + * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID + * and HAL_MMC_MSP_DEINIT_CB_ID. * @param hmmc : MMC handle * @param CallbackId : ID of the callback to be registered * This parameter can be one of the following values: @@ -1893,9 +1904,6 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hmmc); - if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) @@ -1964,14 +1972,15 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hmmc); return status; } /** * @brief Unregister a User MMC Callback * MMC Callback is redirected to the weak (surcharged) predefined callback + * @note The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in + * HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID + * and HAL_MMC_MSP_DEINIT_CB_ID. * @param hmmc : MMC handle * @param CallbackId : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1991,9 +2000,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hmmc); - if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) @@ -2062,8 +2068,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hmmc); return status; } #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ @@ -2692,35 +2696,90 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) */ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) { - HAL_MMC_CardStateTypeDef CardState; + uint32_t error_code; + uint32_t tickstart; - /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + if (hmmc->State == HAL_MMC_STATE_BUSY) + { + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); - /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /*we will send the CMD12 in all cases in order to stop the data transfers*/ + /*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/ + /*Other scenario will return HAL_ERROR*/ - /* If IDMA Context, disable Internal DMA */ - hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + error_code = hmmc->ErrorCode; + if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT)) + { + return HAL_ERROR; + } - hmmc->State = HAL_MMC_STATE_READY; + tickstart = HAL_GetTick(); + if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD) + { + if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE) + { + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } - /* Initialize the MMC operation */ - hmmc->Context = MMC_CONTEXT_NONE; + if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT) + { + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) + { + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + } + else + { + /* Nothing to do*/ + } - CardState = HAL_MMC_GetCardState(hmmc); - if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); - } - if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) - { - return HAL_ERROR; + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */ + + /*SDMMC ready for clear data flags*/ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + /* If IDMA Context, disable Internal DMA */ + hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; } return HAL_OK; } - /** * @brief Abort the current transfer and disable the MMC (IT mode). * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains @@ -3868,7 +3927,7 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) { uint32_t count; uint32_t data; - uint8_t *tmp; + const uint8_t *tmp; tmp = hmmc->pTxBuffPtr; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c index 2a03a91616..7107b19611 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_opamp.c @@ -964,49 +964,6 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop return trimmingvalue; } -/** - * @} - */ - - -/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the OPAMP handle state. - * @param hopamp OPAMP handle - * @retval HAL state - */ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) -{ - /* Check the OPAMP handle allocation */ - if(hopamp == NULL) - { - return HAL_OPAMP_STATE_RESET; - } - - /* Check the parameter */ - assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); - - /* Return OPAMP handle state */ - return hopamp->State; -} - -/** - * @} - */ - #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) /** * @brief Register a User OPAMP Callback @@ -1140,7 +1097,47 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL } #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ - /** + +/** + * @} + */ + + +/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the OPAMP handle state. + * @param hopamp OPAMP handle + * @retval HAL state + */ +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp) +{ + /* Check the OPAMP handle allocation */ + if(hopamp == NULL) + { + return HAL_OPAMP_STATE_RESET; + } + + /* Check the parameter */ + assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance)); + + /* Return OPAMP handle state */ + return hopamp->State; +} + +/** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c index 3695b21a4b..be96346414 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c @@ -318,7 +318,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function @@ -432,7 +432,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -1004,8 +1004,8 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->CID & (0x1U << 8)) == 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; @@ -1033,8 +1033,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->CID & (0x1U << 8)) == 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -1709,8 +1709,8 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->CID & (0x1U << 8)) == 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; @@ -1733,8 +1733,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); - if ((hpcd->Init.battery_charging_enable == 1U) && - (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + if (((USBx->CID & (0x1U << 8)) == 0U) && + (hpcd->Init.battery_charging_enable == 1U)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -1794,6 +1794,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, /* Assign a Tx FIFO */ ep->tx_fifo_num = ep->num; } + /* Set initial data PID. */ if (ep_type == EP_TYPE_BULK) { @@ -1827,7 +1828,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; ep->is_in = 0U; } - ep->num = ep_addr & EP_ADDR_MSK; + ep->num = ep_addr & EP_ADDR_MSK; __HAL_LOCK(hpcd); (void)USB_DeactivateEndpoint(hpcd->Instance, ep); @@ -1862,14 +1863,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); return HAL_OK; } @@ -1910,14 +1904,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, ep->dma_addr = (uint32_t)pBuf; } - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - } + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); return HAL_OK; } @@ -2100,6 +2087,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) return hpcd->State; } +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Set the USB Device high speed test mode. * @param hpcd PCD handle @@ -2127,6 +2115,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) return HAL_OK; } +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c index 58dc661cda..4e6b2bd6de 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c @@ -180,7 +180,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) (without charging capability) */ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; + USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(50U); if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) @@ -196,9 +196,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { /* start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ - USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN; + USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; + USBx->GCCFG |= USB_OTG_GCCFG_SDEN; HAL_Delay(50U); if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c index 44cd6b70ed..cdb48fa0ee 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pssi.c @@ -30,7 +30,7 @@ (#) Declare a PSSI_HandleTypeDef handle structure, for example: PSSI_HandleTypeDef hpssi; - (#) Initialize the PSSI low level resources by implementing the HAL_PSSI_MspInit() API: + (#) Initialize the PSSI low level resources by implementing the @ref HAL_PSSI_MspInit() API: (##) Enable the PSSIx interface clock (##) PSSI pins configuration (+++) Enable the clock for the PSSI GPIOs @@ -50,8 +50,8 @@ (#) Configure the Communication Bus Width, Control Signals, Input Polarity and Output Polarity in the hpssi Init structure. - (#) Initialize the PSSI registers by calling the HAL_PSSI_Init(), configure also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_PSSI_MspInit(&hpssi) API. + (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API. (#) For PSSI IO operations, two operation modes are available within this driver : @@ -59,44 +59,44 @@ *** Polling mode IO operation *** ================================= [..] - (+) Transmit an amount of data by byte in blocking mode using HAL_PSSI_Transmit() - (+) Receive an amount of data by byte in blocking mode using HAL_PSSI_Receive() + (+) Transmit an amount of data by byte in blocking mode using @ref HAL_PSSI_Transmit() + (+) Receive an amount of data by byte in blocking mode using @ref HAL_PSSI_Receive() *** DMA mode IO operation *** ============================== [..] (+) Transmit an amount of data in non-blocking mode (DMA) using - HAL_PSSI_Transmit_DMA() - (+) At transmission end of transfer, HAL_PSSI_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_PSSI_TxCpltCallback() + @ref HAL_PSSI_Transmit_DMA() + (+) At transmission end of transfer, @ref HAL_PSSI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_TxCpltCallback() (+) Receive an amount of data in non-blocking mode (DMA) using - HAL_PSSI_Receive_DMA() - (+) At reception end of transfer, HAL_PSSI_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_PSSI_RxCpltCallback() - (+) In case of transfer Error, HAL_PSSI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_PSSI_ErrorCallback() - (+) Abort a PSSI process communication with Interrupt using HAL_PSSI_Abort_IT() - (+) End of abort process, HAL_PSSI_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_PSSI_AbortCpltCallback() + @ref HAL_PSSI_Receive_DMA() + (+) At reception end of transfer, @ref HAL_PSSI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_RxCpltCallback() + (+) In case of transfer Error, @ref HAL_PSSI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_ErrorCallback() + (+) Abort a PSSI process communication with Interrupt using @ref HAL_PSSI_Abort_IT() + (+) End of abort process, @ref HAL_PSSI_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer @ref HAL_PSSI_AbortCpltCallback() *** PSSI HAL driver macros list *** ================================== [..] Below the list of most used macros in PSSI HAL driver. - (+) HAL_PSSI_ENABLE : Enable the PSSI peripheral - (+) HAL_PSSI_DISABLE : Disable the PSSI peripheral - (+) HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not - (+) HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag - (+) HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt - (+) HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt + (+) @ref HAL_PSSI_ENABLE : Enable the PSSI peripheral + (+) @ref HAL_PSSI_DISABLE : Disable the PSSI peripheral + (+) @ref HAL_PSSI_GET_FLAG : Check whether the specified PSSI flag is set or not + (+) @ref HAL_PSSI_CLEAR_FLAG : Clear the specified PSSI pending flag + (+) @ref HAL_PSSI_ENABLE_IT : Enable the specified PSSI interrupt + (+) @ref HAL_PSSI_DISABLE_IT : Disable the specified PSSI interrupt *** Callback registration *** ============================================= - Use Functions HAL_PSSI_RegisterCallback() or HAL_PSSI_RegisterAddrCallback() + Use Functions @ref HAL_PSSI_RegisterCallback() or @ref HAL_PSSI_RegisterAddrCallback() to register an interrupt callback. - Function HAL_PSSI_RegisterCallback() allows to register following callbacks: + Function @ref HAL_PSSI_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : callback for transmission end of transfer. (+) RxCpltCallback : callback for reception end of transfer. (+) ErrorCallback : callback for error detection. @@ -107,9 +107,9 @@ and a pointer to the user callback function. - Use function HAL_PSSI_UnRegisterCallback to reset a callback to the default + Use function @ref HAL_PSSI_UnRegisterCallback to reset a callback to the default weak function. - HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + @ref HAL_PSSI_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : callback for transmission end of transfer. @@ -120,29 +120,28 @@ (+) MspDeInitCallback : callback for Msp DeInit. - By default, after the HAL_PSSI_Init() and when the state is HAL_PSSI_STATE_RESET + By default, after the @ref HAL_PSSI_Init() and when the state is @ref HAL_PSSI_STATE_RESET all callbacks are set to the corresponding weak functions: - examples HAL_PSSI_TxCpltCallback(), HAL_PSSI_RxCpltCallback(). + examples @ref HAL_PSSI_TxCpltCallback(), @ref HAL_PSSI_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_PSSI_Init()/ HAL_PSSI_DeInit() only when + reset to the legacy weak functions in the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_PSSI_Init()/ HAL_PSSI_DeInit() + If MspInit or MspDeInit are not null, the @ref HAL_PSSI_Init()/ @ref HAL_PSSI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - Callbacks can be registered/unregistered in HAL_PSSI_STATE_READY state only. + Callbacks can be registered/unregistered in @ref HAL_PSSI_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_PSSI_STATE_READY or HAL_PSSI_STATE_RESET state, + in @ref HAL_PSSI_STATE_READY or @ref HAL_PSSI_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_PSSI_RegisterCallback() before calling HAL_PSSI_DeInit() - or HAL_PSSI_Init() function. + using @ref HAL_PSSI_RegisterCallback() before calling @ref HAL_PSSI_DeInit() + or @ref HAL_PSSI_Init() function. [..] (@) You can refer to the PSSI HAL driver header file for more useful macros @endverbatim - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -189,8 +188,16 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma); /* Private functions to handle IT transfer */ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode); + +/* Private functions for PSSI transfer IRQ handler */ + + /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ + /** * @} @@ -203,8 +210,8 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi */ /** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -281,8 +288,9 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi) /*---------------------------- PSSIx CR Configuration ----------------------*/ /* Configure PSSIx: Control Signal and Bus Width*/ - MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DERDYCFG|PSSI_CR_EDM|PSSI_CR_DEPOL|PSSI_CR_RDYPOL, - hpssi->Init.ControlSignal|hpssi->Init.DataEnablePolarity|hpssi->Init.ReadyPolarity|hpssi->Init.BusWidth); + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL, + hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity | + hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth); hpssi->ErrorCode = HAL_PSSI_ERROR_NONE; hpssi->State = HAL_PSSI_STATE_READY; @@ -364,6 +372,9 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi) /** * @brief Register a User PSSI Callback * To be used instead of the weak predefined callback + * @note The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in + * HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID + * and HAL_PSSI_MSPDEINIT_CB_ID. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @param CallbackID ID of the callback to be registered @@ -377,7 +388,8 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, + pPSSI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -388,8 +400,6 @@ HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_ return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hpssi); if (HAL_PSSI_STATE_READY == hpssi->State) { @@ -458,14 +468,15 @@ HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpssi); return status; } /** * @brief Unregister an PSSI Callback * PSSI callback is redirected to the weak predefined callback + * @note The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in + * HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID + * and HAL_PSSI_MSPDEINIT_CB_ID. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. * @param CallbackID ID of the callback to be unregistered @@ -482,9 +493,6 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hpssi); - if (HAL_PSSI_STATE_READY == hpssi->State) { switch (CallbackID) @@ -552,8 +560,6 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hpssi); return status; } @@ -563,8 +569,8 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS */ /** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -614,13 +620,9 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u uint32_t tickstart; uint32_t transfer_size = Size; -#if defined (__GNUC__) - __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR)); -#endif /* __GNUC__ */ - if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) || - ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) || - ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U))) + ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) || + ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U))) { hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED; return HAL_ERROR; @@ -638,7 +640,7 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u /* Configure transfer parameters */ hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL); + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL); /* DMA Disable */ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; @@ -673,6 +675,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS) { uint16_t *pbuffer = (uint16_t *)pData; + __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR); + while (transfer_size > 0U) { /* Init tickstart for timeout management*/ @@ -687,11 +691,7 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u return HAL_ERROR; } /* Write data to DR */ -#if defined (__GNUC__) - *pdr_16bits = *pbuffer; -#else - *(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer; -#endif /* __GNUC__ */ + *dr = *pbuffer; /* Increment Buffer pointer */ pbuffer++; @@ -772,13 +772,10 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui { uint32_t tickstart; uint32_t transfer_size = Size; -#if defined (__GNUC__) - __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR)); -#endif /* __GNUC__ */ if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) || - ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) || - ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U))) + ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) || + ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U))) { hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED; return HAL_ERROR; @@ -795,8 +792,8 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui /* Disable the selected PSSI peripheral */ HAL_PSSI_DISABLE(hpssi); /* Configure transfer parameters */ - hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE)?0U:PSSI_CR_CKPOL); - + hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL); /* DMA Disable */ hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE; @@ -829,6 +826,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS) { uint16_t *pbuffer = (uint16_t *)pData; + __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR); while (transfer_size > 0U) { @@ -845,12 +843,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui } /* Read data from DR */ -#if defined (__GNUC__) - *pbuffer = *pdr_16bits; -#else - *pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR); -#endif /* __GNUC__ */ - + *pbuffer = *dr; pbuffer++; transfer_size -= 2U; @@ -956,15 +949,17 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa { /* Configure BusWidth */ - if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) { - MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL)); + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); } else { - MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL)); + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)); } /* Set the PSSI DMA transfer complete callback */ @@ -978,7 +973,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa hpssi->hdmatx->XferAbortCallback = NULL; /* Enable the DMA */ - dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR, hpssi->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR, + hpssi->XferSize); } else { @@ -1094,15 +1090,16 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat { /* Configure BusWidth */ - if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) + if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) { - MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U)); + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); } else { - MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | - ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U)); + MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, + PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | + ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U)); } /* Set the PSSI DMA transfer complete callback */ @@ -1116,7 +1113,8 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat hpssi->hdmarx->XferAbortCallback = NULL; /* Enable the DMA */ - dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData, hpssi->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData, + hpssi->XferSize); } else { @@ -1270,9 +1268,9 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi) * @} */ -/** @defgroup PSSI_Exported_Functions_Group3 IRQ Handler and Callbacks - * @{ - */ +/** @defgroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /** * @brief This function handles PSSI event interrupt request. @@ -1450,9 +1448,9 @@ __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi) * @} */ -/** @defgroup PSSI_Exported_Functions_Group4 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * +/** @defgroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions + * @brief Peripheral State, Mode and Error functions + * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### @@ -1479,11 +1477,11 @@ HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi) /** -* @brief Return the PSSI error code. + * @brief Return the PSSI error code. * @param hpssi Pointer to a PSSI_HandleTypeDef structure that contains * the configuration information for the specified PSSI. -* @retval PSSI Error Code -*/ + * @retval PSSI Error Code + */ uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi) { return hpssi->ErrorCode; @@ -1608,7 +1606,8 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode) */ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmperror; @@ -1649,7 +1648,8 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmperror; @@ -1690,7 +1690,8 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma) { - PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ hpssi->hdmatx->XferAbortCallback = NULL; @@ -1723,7 +1724,8 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma) * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status) { @@ -1746,7 +1748,8 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi } void PSSI_DMAError(DMA_HandleTypeDef *hdma) { - PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmperror; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c index 628f8f0413..0c0116b740 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ramecc.c @@ -219,10 +219,6 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc) * @} */ -/** - * @} - */ - /** @addtogroup RAMECC_Exported_Functions_Group2 * @verbatim @@ -501,7 +497,9 @@ void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc) hramecc->DetectErrorCallback(hramecc); } } - +/** + * @} + */ /** @addtogroup RAMECC_Exported_Functions_Group3 * @@ -671,16 +669,11 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc) /** * @} */ -#endif /* HAL_RAMECC_MODULE_ENABLED */ /** * @} */ - -/** - * @} - */ - +#endif /* HAL_RAMECC_MODULE_ENABLED */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c index c95945d6bb..8c987ac8ef 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c @@ -189,15 +189,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { uint32_t tickstart; - /* Increasing the CPU frequency */ - if(FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) { return HAL_ERROR; } @@ -231,7 +231,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemD2Clock = HSI_VALUE; /* Adapt Systick interrupt period */ - if(HAL_InitTick(uwTickPrio) != HAL_OK) + if (HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -252,8 +252,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) tickstart = HAL_GetTick(); /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON \ - | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON \ + | RCC_CR_HSI48ON | RCC_CR_CSSHSEON); /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) @@ -330,25 +330,25 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) #endif /* Reset PLLCKSELR register to default value */ - RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5; + RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5; /* Reset PLLCFGR register to default value */ WRITE_REG(RCC->PLLCFGR, 0x01FF0000U); /* Reset PLL1DIVR register to default value */ - WRITE_REG(RCC->PLL1DIVR,0x01010280U); + WRITE_REG(RCC->PLL1DIVR, 0x01010280U); /* Reset PLL1FRACR register */ CLEAR_REG(RCC->PLL1FRACR); /* Reset PLL2DIVR register to default value */ - WRITE_REG(RCC->PLL2DIVR,0x01010280U); + WRITE_REG(RCC->PLL2DIVR, 0x01010280U); /* Reset PLL2FRACR register */ CLEAR_REG(RCC->PLL2FRACR); /* Reset PLL3DIVR register to default value */ - WRITE_REG(RCC->PLL3DIVR,0x01010280U); + WRITE_REG(RCC->PLL3DIVR, 0x01010280U); /* Reset PLL3FRACR register */ CLEAR_REG(RCC->PLL3FRACR); @@ -365,25 +365,25 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) CLEAR_REG(RCC->CIER); /* Clear all interrupts flags */ - WRITE_REG(RCC->CICR,0xFFFFFFFFU); + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); /* Reset all RSR flags */ SET_BIT(RCC->RSR, RCC_RSR_RMVF); - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) + if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) { return HAL_ERROR; } -} + } return HAL_OK; } @@ -407,8 +407,8 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc uint32_t tickstart; uint32_t temp1_pllckcfg, temp2_pllckcfg; - /* Check Null pointer */ - if(RCC_OscInitStruct == NULL) + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) { return HAL_ERROR; } @@ -416,7 +416,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); @@ -424,9 +424,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); const uint32_t temp_pllckselr = RCC->PLLCKSELR; /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ - if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) + if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } @@ -437,15 +437,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) { - if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -457,9 +457,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) { - if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -468,7 +468,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) { /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); @@ -477,30 +477,30 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* When the HSI is used as system clock it will not be disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); const uint32_t temp_pllckselr = RCC->PLLCKSELR; - if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) + if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI))) { /* When HSI is used as system clock it will not be disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) { return HAL_ERROR; } /* Otherwise, only HSI division and calibration are allowed */ else { - /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ - __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */ + __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); - /* Get Start Tick*/ - tickstart = HAL_GetTick(); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + { + if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { - if((uint32_t) (HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } + } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); } @@ -509,18 +509,18 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc else { /* Check the HSI State */ - if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) { - /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ + /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState); /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -538,9 +538,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -549,7 +549,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } /*----------------------------- CSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) { /* Check the parameters */ assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState)); @@ -558,10 +558,10 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* When the CSI is used as system clock it will not disabled */ const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); const uint32_t temp_pllckselr = RCC->PLLCKSELR; - if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) + if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI))) { /* When CSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON)) { return HAL_ERROR; } @@ -575,7 +575,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc else { /* Check the CSI State */ - if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF) + if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF) { /* Enable the Internal High Speed oscillator (CSI). */ __HAL_RCC_CSI_ENABLE(); @@ -584,9 +584,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till CSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -604,9 +604,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till CSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) { - if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -615,13 +615,13 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ - if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); @@ -630,9 +630,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -647,9 +647,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -658,13 +658,13 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } /*------------------------------ HSI48 Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the HSI48 State */ - if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF) + if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF) { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); @@ -673,9 +673,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U) { - if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -690,9 +690,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U) { - if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -700,7 +700,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc } } /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); @@ -711,9 +711,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while((PWR->CR1 & PWR_CR1_DBP) == 0U) + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) { - if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -722,15 +722,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -742,9 +742,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -757,9 +757,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1) { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); @@ -779,9 +779,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -795,11 +795,11 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); - /* Disable PLLFRACN . */ - __HAL_RCC_PLLFRACN_DISABLE(); + /* Disable PLLFRACN . */ + __HAL_RCC_PLLFRACN_DISABLE(); - /* Configure PLL PLL1FRACN */ - __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + /* Configure PLL PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); /* Select PLL1 input reference frequency range: VCI */ __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ; @@ -808,16 +808,16 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ; /* Enable PLL System Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); /* Enable PLL1Q Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); /* Enable PLL1R Clock output. */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); /* Enable PLL1FRACN . */ - __HAL_RCC_PLLFRACN_ENABLE(); + __HAL_RCC_PLLFRACN_ENABLE(); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); @@ -826,9 +826,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -843,9 +843,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -857,16 +857,37 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Do not return HAL_ERROR if request repeats the current configuration */ temp1_pllckcfg = RCC->PLLCKSELR; temp2_pllckcfg = RCC->PLL1DIVR; - if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || - (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || - ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || - ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || - ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) || + ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U))) { return HAL_ERROR; } + else + { + /* Check if only fractional part needs to be updated */ + temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos); + if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN)); + /* Disable PLL1FRACEN */ + __HAL_RCC_PLLFRACN_DISABLE(); + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE) + { + } + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN); + /* Enable PLL1FRACEN to latch new value. */ + __HAL_RCC_PLLFRACN_ENABLE(); + } + } } } return HAL_OK; @@ -904,8 +925,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui uint32_t tickstart; uint32_t common_system_clock; - /* Check Null pointer */ - if(RCC_ClkInitStruct == NULL) + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) { return HAL_ERROR; } @@ -919,14 +940,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ - if(FLatency > __HAL_FLASH_GET_LATENCY()) + if (FLatency > __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) + if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } @@ -935,16 +956,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) { #if defined (RCC_D1CFGR_D1PPRE) - if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) { assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); } #else - if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) { assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); @@ -953,33 +974,33 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { #if defined (RCC_D2CFGR_D2PPRE1) - if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); } #else - if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) { assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); - } -#endif } +#endif + } /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { #if defined(RCC_D2CFGR_D2PPRE2) - if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); } #else - if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) { assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); @@ -988,35 +1009,35 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) { #if defined(RCC_D3CFGR_D3PPRE) - if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); - MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); } #else - if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) { assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); - MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); } #endif } - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { #if defined (RCC_D1CFGR_HPRE) - if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } #else - if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); @@ -1025,80 +1046,80 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif } - /*------------------------- SYSCLK Configuration -------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + /*------------------------- SYSCLK Configuration -------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_D1CFGR_D1CPRE) - MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider); #else - MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider); #endif - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - { - return HAL_ERROR; - } + return HAL_ERROR; } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - { - return HAL_ERROR; - } + return HAL_ERROR; } - /* CSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + } + /* CSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U) - { - return HAL_ERROR; - } + return HAL_ERROR; } - /* HSI is selected as System Clock Source */ - else + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - { - return HAL_ERROR; - } + return HAL_ERROR; } - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); + } + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } } - /* Decreasing the BUS frequency divider */ - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + } + + /* Decreasing the BUS frequency divider */ + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { #if defined(RCC_D1CFGR_HPRE) - if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); } #else - if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) + if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)) { /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); @@ -1108,102 +1129,102 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < __HAL_FLASH_GET_LATENCY()) + if (FLatency < __HAL_FLASH_GET_LATENCY()) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) + if (__HAL_FLASH_GET_LATENCY() != FLatency) { return HAL_ERROR; } - } + } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) - { + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) + { #if defined(RCC_D1CFGR_D1PPRE) - if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) - { - assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); - MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); - } + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) + { + assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider); + } #else - if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) - { - assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); - MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); - } + if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)) + { + assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider)); + MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider); + } #endif - } + } /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { #if defined(RCC_D2CFGR_D2PPRE1) - if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) - { - assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); - } + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } #else - if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) - { - assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); - } + if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)) + { + assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider)); + } #endif - } + } /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { #if defined (RCC_D2CFGR_D2PPRE2) - if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) - { - assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); - } + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } #else - if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) - { - assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); - } + if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)) + { + assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider)); + } #endif - } + } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) - { + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) + { #if defined(RCC_D3CFGR_D3PPRE) - if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) - { - assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); - MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); - } + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) + { + assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } #else - if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) - { - assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); - MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) ); - } + if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)) + { + assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider)); + MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider)); + } #endif - } + } /* Update the SystemCoreClock global variable */ #if defined(RCC_D1CFGR_D1CPRE) - common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); #else - common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif #if defined(DUAL_CORE) && defined(CORE_CM4) @@ -1213,7 +1234,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui #endif /* DUAL_CORE && CORE_CM4 */ /* Configure the source of time base considering new system clocks settings*/ - halstatus = HAL_InitTick (uwTickPrio); + halstatus = HAL_InitTick(uwTickPrio); return halstatus; } @@ -1222,7 +1243,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Group2 Peripheral Control functions +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim @@ -1269,7 +1290,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); /* RCC_MCO1 */ - if(RCC_MCOx == RCC_MCO1) + if (RCC_MCOx == RCC_MCO1) { assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); @@ -1374,78 +1395,78 @@ uint32_t HAL_RCC_GetSysClockFreq(void) switch (RCC->CFGR & RCC_CFGR_SWS) { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); + sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); } else { sysclockfreq = (uint32_t) HSI_VALUE; } - break; + break; - case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - sysclockfreq = CSI_VALUE; - break; + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + sysclockfreq = CSI_VALUE; + break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - sysclockfreq = HSE_VALUE; - break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + sysclockfreq = HSE_VALUE; + break; - case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; - pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ; + pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); - if (pllm != 0U) - { - switch (pllsource) + if (pllm != 0U) { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + switch (pllsource) { - hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - } - else - { - pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - } - break; + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; - default: - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ; + sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp); } - pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; - sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp); - } - else - { - sysclockfreq = 0U; - } - break; + else + { + sysclockfreq = 0U; + } + break; - default: - sysclockfreq = CSI_VALUE; - break; + default: + sysclockfreq = CSI_VALUE; + break; } return sysclockfreq; @@ -1463,18 +1484,18 @@ uint32_t HAL_RCC_GetSysClockFreq(void) */ uint32_t HAL_RCC_GetHCLKFreq(void) { -uint32_t common_system_clock; + uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) - common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); #else - common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif #if defined(RCC_D1CFGR_HPRE) - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif #if defined(DUAL_CORE) && defined(CORE_CM4) @@ -1497,16 +1518,16 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) { #if defined (RCC_D2CFGR_D2PPRE1) /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU)); #else - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU)); #endif } /** - * @brief Returns the PCLK2 frequency + * @brief Returns the D2 PCLK2 frequency * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency @@ -1515,9 +1536,9 @@ uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ #if defined(RCC_D2CFGR_D2PPRE2) - return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU)); #else - return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); + return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU)); #endif } @@ -1532,19 +1553,19 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48; + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; /* Get the HSE configuration -----------------------------------------------*/ #if defined(RCC_CR_HSEEXT) - if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) + if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) + else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL; } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1553,11 +1574,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSEState = RCC_HSE_OFF; } #else - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) { RCC_OscInitStruct->HSEState = RCC_HSE_ON; } @@ -1567,8 +1588,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } #endif /* RCC_CR_HSEEXT */ - /* Get the CSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION) + /* Get the CSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION) { RCC_OscInitStruct->CSIState = RCC_CSI_ON; } @@ -1578,7 +1599,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } #if defined(RCC_VER_X) - if(HAL_GetREVID() <= REV_ID_Y) + if (HAL_GetREVID() <= REV_ID_Y) { RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos); } @@ -1587,11 +1608,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); } #else - RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); + RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos); #endif /*RCC_VER_X*/ /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) { RCC_OscInitStruct->HSIState = RCC_HSI_ON; } @@ -1601,7 +1622,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } #if defined(RCC_VER_X) - if(HAL_GetREVID() <= REV_ID_Y) + if (HAL_GetREVID() <= REV_ID_Y) { RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos); } @@ -1610,20 +1631,20 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); } #else - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos); #endif /*RCC_VER_X*/ /* Get the LSE configuration -----------------------------------------------*/ #if defined(RCC_BDCR_LSEEXT) - if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) + if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) + else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL; } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -1632,11 +1653,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->LSEState = RCC_LSE_OFF; } #else - if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) { RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; } - else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { RCC_OscInitStruct->LSEState = RCC_LSE_ON; } @@ -1647,7 +1668,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) #endif /* RCC_BDCR_LSEEXT */ /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) { RCC_OscInitStruct->LSIState = RCC_LSI_ON; } @@ -1657,7 +1678,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the HSI48 configuration ---------------------------------------------*/ - if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) + if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON) { RCC_OscInitStruct->HSI48State = RCC_HSI48_ON; } @@ -1667,7 +1688,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) { RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; } @@ -1676,11 +1697,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; } RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U; - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U; - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U; - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U; + RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U; + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U; RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE)); RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos); RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos)); @@ -1753,10 +1774,10 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CCSCallback(); + HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); @@ -1767,10 +1788,10 @@ void HAL_RCC_NMI_IRQHandler(void) * @brief RCC Clock Security System interrupt callback * @retval none */ -__weak void HAL_RCC_CCSCallback(void) +__weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CCSCallback could be implemented in the user file + the HAL_RCC_CSSCallback could be implemented in the user file */ } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c index 96d7dd4410..96517ce083 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c @@ -111,42 +111,42 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*---------------------------- SPDIFRX configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) { - switch(PeriphClkInit->SpdifrxClockSelection) + switch (PeriphClkInit->SpdifrxClockSelection) { - case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ - /* Enable PLL1Q Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SPDIFRXCLKSOURCE_PLL: /* PLL is used as clock source for SPDIFRX*/ + /* Enable PLL1Q Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SPDIFRX clock source configuration done later after clock selection check */ - break; + /* SPDIFRX clock source configuration done later after clock selection check */ + break; - case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ + case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); - /* SPDIFRX clock source configuration done later after clock selection check */ - break; + /* SPDIFRX clock source configuration done later after clock selection check */ + break; - case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIFRX*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); - /* SPDIFRX clock source configuration done later after clock selection check */ - break; + /* SPDIFRX clock source configuration done later after clock selection check */ + break; - case RCC_SPDIFRXCLKSOURCE_HSI: - /* Internal OSC clock is used as source of SPDIFRX clock*/ - /* SPDIFRX clock source configuration done later after clock selection check */ - break; + case RCC_SPDIFRXCLKSOURCE_HSI: + /* Internal OSC clock is used as source of SPDIFRX clock*/ + /* SPDIFRX clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SPDIFRX clock*/ __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection); @@ -159,46 +159,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- SAI1 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) { - switch(PeriphClkInit->Sai1ClockSelection) + switch (PeriphClkInit->Sai1ClockSelection) { - case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ + case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI1CLKSOURCE_PIN: - /* External clock is used as source of SAI1 clock*/ - /* SAI1 clock source configuration done later after clock selection check */ - break; + case RCC_SAI1CLKSOURCE_PIN: + /* External clock is used as source of SAI1 clock*/ + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI1CLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ - /* SAI1 clock source configuration done later after clock selection check */ - break; + case RCC_SAI1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); @@ -212,46 +212,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(SAI3) /*---------------------------- SAI2/3 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23) { - switch(PeriphClkInit->Sai23ClockSelection) + switch (PeriphClkInit->Sai23ClockSelection) { - case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SAI23CLKSOURCE_PLL: /* PLL is used as clock source for SAI2/3 */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI2/3 clock source configuration done later after clock selection check */ - break; + /* SAI2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ + case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SAI2/3 clock source configuration done later after clock selection check */ - break; + /* SAI2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SAI2/3 clock source configuration done later after clock selection check */ - break; + /* SAI2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SAI23CLKSOURCE_PIN: - /* External clock is used as source of SAI2/3 clock*/ - /* SAI2/3 clock source configuration done later after clock selection check */ - break; + case RCC_SAI23CLKSOURCE_PIN: + /* External clock is used as source of SAI2/3 clock*/ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SAI23CLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ - /* SAI2/3 clock source configuration done later after clock selection check */ - break; + case RCC_SAI23CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */ + /* SAI2/3 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SAI2/3 clock*/ __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection); @@ -267,51 +267,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(RCC_CDCCIP1R_SAI2ASEL) /*---------------------------- SAI2A configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A) { - switch(PeriphClkInit->Sai2AClockSelection) + switch (PeriphClkInit->Sai2AClockSelection) { - case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ - /* Enable SAI2A Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SAI2ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2A */ + /* Enable SAI2A Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI2A clock source configuration done later after clock selection check */ - break; + /* SAI2A clock source configuration done later after clock selection check */ + break; - case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ + case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SAI2A clock source configuration done later after clock selection check */ - break; + /* SAI2A clock source configuration done later after clock selection check */ + break; - case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + case RCC_SAI2ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2A */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SAI2A clock source configuration done later after clock selection check */ - break; + /* SAI2A clock source configuration done later after clock selection check */ + break; - case RCC_SAI2ACLKSOURCE_PIN: - /* External clock is used as source of SAI2A clock*/ - /* SAI2A clock source configuration done later after clock selection check */ - break; + case RCC_SAI2ACLKSOURCE_PIN: + /* External clock is used as source of SAI2A clock*/ + /* SAI2A clock source configuration done later after clock selection check */ + break; - case RCC_SAI2ACLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ - /* SAI2A clock source configuration done later after clock selection check */ - break; + case RCC_SAI2ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; - case RCC_SAI2ACLKSOURCE_SPDIF: - /* SPDIF clock is used as source of SAI2A clock */ - /* SAI2A clock source configuration done later after clock selection check */ - break; + case RCC_SAI2ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2A clock */ + /* SAI2A clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SAI2A clock*/ __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection); @@ -327,51 +327,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(RCC_CDCCIP1R_SAI2BSEL) /*---------------------------- SAI2B configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B) { - switch(PeriphClkInit->Sai2BClockSelection) + switch (PeriphClkInit->Sai2BClockSelection) { - case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SAI2BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2B */ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI2B clock source configuration done later after clock selection check */ - break; + /* SAI2B clock source configuration done later after clock selection check */ + break; - case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ + case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SAI2B clock source configuration done later after clock selection check */ - break; + /* SAI2B clock source configuration done later after clock selection check */ + break; - case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + case RCC_SAI2BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2B */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SAI2B clock source configuration done later after clock selection check */ - break; + /* SAI2B clock source configuration done later after clock selection check */ + break; - case RCC_SAI2BCLKSOURCE_PIN: - /* External clock is used as source of SAI2B clock*/ - /* SAI2B clock source configuration done later after clock selection check */ - break; + case RCC_SAI2BCLKSOURCE_PIN: + /* External clock is used as source of SAI2B clock*/ + /* SAI2B clock source configuration done later after clock selection check */ + break; - case RCC_SAI2BCLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ - /* SAI2B clock source configuration done later after clock selection check */ - break; + case RCC_SAI2BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; - case RCC_SAI2BCLKSOURCE_SPDIF: - /* SPDIF clock is used as source of SAI2B clock */ - /* SAI2B clock source configuration done later after clock selection check */ - break; + case RCC_SAI2BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI2B clock */ + /* SAI2B clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SAI2B clock*/ __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection); @@ -386,53 +386,53 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(SAI4) /*---------------------------- SAI4A configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A) { - switch(PeriphClkInit->Sai4AClockSelection) + switch (PeriphClkInit->Sai4AClockSelection) { - case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SAI4ACLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SAI2 clock source configuration done later after clock selection check */ - break; + /* SAI2 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + case RCC_SAI4ACLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4ACLKSOURCE_PIN: - /* External clock is used as source of SAI2 clock*/ - /* SAI2 clock source configuration done later after clock selection check */ - break; + case RCC_SAI4ACLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4ACLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ - /* SAI1 clock source configuration done later after clock selection check */ - break; + case RCC_SAI4ACLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; #if defined(RCC_VER_3_0) - case RCC_SAI4ACLKSOURCE_SPDIF: - /* SPDIF clock is used as source of SAI4A clock */ - /* SAI4A clock source configuration done later after clock selection check */ - break; + case RCC_SAI4ACLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4A clock */ + /* SAI4A clock source configuration done later after clock selection check */ + break; #endif /* RCC_VER_3_0 */ - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SAI4A clock*/ __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection); @@ -444,53 +444,53 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } /*---------------------------- SAI4B configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B) { - switch(PeriphClkInit->Sai4BClockSelection) + switch (PeriphClkInit->Sai4BClockSelection) { - case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ - /* Enable SAI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SAI4BCLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/ + /* Enable SAI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ + case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SAI2 clock source configuration done later after clock selection check */ - break; + /* SAI2 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + case RCC_SAI4BCLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SAI1 clock source configuration done later after clock selection check */ - break; + /* SAI1 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4BCLKSOURCE_PIN: - /* External clock is used as source of SAI2 clock*/ - /* SAI2 clock source configuration done later after clock selection check */ - break; + case RCC_SAI4BCLKSOURCE_PIN: + /* External clock is used as source of SAI2 clock*/ + /* SAI2 clock source configuration done later after clock selection check */ + break; - case RCC_SAI4BCLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ - /* SAI1 clock source configuration done later after clock selection check */ - break; + case RCC_SAI4BCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */ + /* SAI1 clock source configuration done later after clock selection check */ + break; #if defined(RCC_VER_3_0) - case RCC_SAI4BCLKSOURCE_SPDIF: - /* SPDIF clock is used as source of SAI4B clock */ - /* SAI4B clock source configuration done later after clock selection check */ - break; + case RCC_SAI4BCLKSOURCE_SPDIF: + /* SPDIF clock is used as source of SAI4B clock */ + /* SAI4B clock source configuration done later after clock selection check */ + break; #endif /* RCC_VER_3_0 */ - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SAI4B clock*/ __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection); @@ -505,40 +505,40 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(QUADSPI) /*---------------------------- QSPI configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) { - switch(PeriphClkInit->QspiClockSelection) + switch (PeriphClkInit->QspiClockSelection) { - case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ - /* Enable QSPI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_QSPICLKSOURCE_PLL: /* PLL is used as clock source for QSPI*/ + /* Enable QSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* QSPI clock source configuration done later after clock selection check */ - break; + /* QSPI clock source configuration done later after clock selection check */ + break; - case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ + case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); - /* QSPI clock source configuration done later after clock selection check */ - break; + /* QSPI clock source configuration done later after clock selection check */ + break; - case RCC_QSPICLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ - /* QSPI clock source configuration done later after clock selection check */ - break; + case RCC_QSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */ + /* QSPI clock source configuration done later after clock selection check */ + break; - case RCC_QSPICLKSOURCE_D1HCLK: - /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ - break; + case RCC_QSPICLKSOURCE_D1HCLK: + /* Domain1 HCLK clock selected as QSPI kernel peripheral clock */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of QSPI clock*/ __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection); @@ -553,40 +553,40 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(OCTOSPI1) || defined(OCTOSPI2) /*---------------------------- OCTOSPI configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) { - switch(PeriphClkInit->OspiClockSelection) + switch (PeriphClkInit->OspiClockSelection) { - case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ - /* Enable OSPI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_OSPICLKSOURCE_PLL: /* PLL is used as clock source for OSPI*/ + /* Enable OSPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* OSPI clock source configuration done later after clock selection check */ - break; + /* OSPI clock source configuration done later after clock selection check */ + break; - case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ + case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); - /* OSPI clock source configuration done later after clock selection check */ - break; + /* OSPI clock source configuration done later after clock selection check */ + break; - case RCC_OSPICLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ - /* OSPI clock source configuration done later after clock selection check */ - break; + case RCC_OSPICLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */ + /* OSPI clock source configuration done later after clock selection check */ + break; - case RCC_OSPICLKSOURCE_HCLK: - /* HCLK clock selected as OSPI kernel peripheral clock */ - break; + case RCC_OSPICLKSOURCE_HCLK: + /* HCLK clock selected as OSPI kernel peripheral clock */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of OSPI clock*/ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); @@ -600,45 +600,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /*OCTOSPI*/ /*---------------------------- SPI1/2/3 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123) { - switch(PeriphClkInit->Spi123ClockSelection) + switch (PeriphClkInit->Spi123ClockSelection) { - case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ - /* Enable SPI Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SPI123CLKSOURCE_PLL: /* PLL is used as clock source for SPI1/2/3 */ + /* Enable SPI Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SPI1/2/3 clock source configuration done later after clock selection check */ - break; + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* SPI1/2/3 clock source configuration done later after clock selection check */ - break; + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE); + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI1/2/3 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); - /* SPI1/2/3 clock source configuration done later after clock selection check */ - break; + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SPI123CLKSOURCE_PIN: - /* External clock is used as source of SPI1/2/3 clock*/ - /* SPI1/2/3 clock source configuration done later after clock selection check */ - break; + case RCC_SPI123CLKSOURCE_PIN: + /* External clock is used as source of SPI1/2/3 clock*/ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; - case RCC_SPI123CLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ - /* SPI1/2/3 clock source configuration done later after clock selection check */ - break; + case RCC_SPI123CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */ + /* SPI1/2/3 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SPI1/2/3 clock*/ __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection); @@ -651,46 +651,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- SPI4/5 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45) { - switch(PeriphClkInit->Spi45ClockSelection) + switch (PeriphClkInit->Spi45ClockSelection) { - case RCC_SPI45CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for SPI4/5 */ - /* SPI4/5 clock source configuration done later after clock selection check */ - break; + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for SPI4/5 */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; - case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); - /* SPI4/5 clock source configuration done later after clock selection check */ - break; - case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); - /* SPI4/5 clock source configuration done later after clock selection check */ - break; + /* SPI4/5 clock source configuration done later after clock selection check */ + break; + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI4/5 clock source configuration done later after clock selection check */ + break; - case RCC_SPI45CLKSOURCE_HSI: - /* HSI oscillator clock is used as source of SPI4/5 clock*/ - /* SPI4/5 clock source configuration done later after clock selection check */ - break; + case RCC_SPI45CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI4/5 clock*/ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; - case RCC_SPI45CLKSOURCE_CSI: - /* CSI oscillator clock is used as source of SPI4/5 clock */ - /* SPI4/5 clock source configuration done later after clock selection check */ - break; + case RCC_SPI45CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; - case RCC_SPI45CLKSOURCE_HSE: - /* HSE, oscillator is used as source of SPI4/5 clock */ - /* SPI4/5 clock source configuration done later after clock selection check */ - break; + case RCC_SPI45CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI4/5 clock */ + /* SPI4/5 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SPI4/5 clock*/ __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection); @@ -703,52 +703,52 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- SPI6 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6) { - switch(PeriphClkInit->Spi6ClockSelection) + switch (PeriphClkInit->Spi6ClockSelection) { - case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ - /* SPI6 clock source configuration done later after clock selection check */ - break; + case RCC_SPI6CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; - case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ + case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); - /* SPI6 clock source configuration done later after clock selection check */ - break; - case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); - /* SPI6 clock source configuration done later after clock selection check */ - break; + /* SPI6 clock source configuration done later after clock selection check */ + break; + case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* SPI6 clock source configuration done later after clock selection check */ + break; - case RCC_SPI6CLKSOURCE_HSI: - /* HSI oscillator clock is used as source of SPI6 clock*/ - /* SPI6 clock source configuration done later after clock selection check */ - break; + case RCC_SPI6CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of SPI6 clock*/ + /* SPI6 clock source configuration done later after clock selection check */ + break; - case RCC_SPI6CLKSOURCE_CSI: - /* CSI oscillator clock is used as source of SPI6 clock */ - /* SPI6 clock source configuration done later after clock selection check */ - break; + case RCC_SPI6CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; - case RCC_SPI6CLKSOURCE_HSE: - /* HSE, oscillator is used as source of SPI6 clock */ - /* SPI6 clock source configuration done later after clock selection check */ - break; + case RCC_SPI6CLKSOURCE_HSE: + /* HSE, oscillator is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; #if defined(RCC_SPI6CLKSOURCE_PIN) - case RCC_SPI6CLKSOURCE_PIN: - /* 2S_CKIN is used as source of SPI6 clock */ - /* SPI6 clock source configuration done later after clock selection check */ - break; + case RCC_SPI6CLKSOURCE_PIN: + /* 2S_CKIN is used as source of SPI6 clock */ + /* SPI6 clock source configuration done later after clock selection check */ + break; #endif - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SPI6 clock*/ __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection); @@ -762,29 +762,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(DSI) /*---------------------------- DSI configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) { - switch(PeriphClkInit->DsiClockSelection) + switch (PeriphClkInit->DsiClockSelection) { - case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ + case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); - /* DSI clock source configuration done later after clock selection check */ - break; + /* DSI clock source configuration done later after clock selection check */ + break; - case RCC_DSICLKSOURCE_PHY: - /* PHY is used as clock source for DSI*/ - /* DSI clock source configuration done later after clock selection check */ - break; + case RCC_DSICLKSOURCE_PHY: + /* PHY is used as clock source for DSI*/ + /* DSI clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of DSI clock*/ __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection); @@ -799,35 +799,35 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(FDCAN1) || defined(FDCAN2) /*---------------------------- FDCAN configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) { - switch(PeriphClkInit->FdcanClockSelection) + switch (PeriphClkInit->FdcanClockSelection) { - case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ - /* Enable FDCAN Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_FDCANCLKSOURCE_PLL: /* PLL is used as clock source for FDCAN*/ + /* Enable FDCAN Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* FDCAN clock source configuration done later after clock selection check */ - break; + /* FDCAN clock source configuration done later after clock selection check */ + break; - case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); - /* FDCAN clock source configuration done later after clock selection check */ - break; + /* FDCAN clock source configuration done later after clock selection check */ + break; - case RCC_FDCANCLKSOURCE_HSE: - /* HSE is used as clock source for FDCAN*/ - /* FDCAN clock source configuration done later after clock selection check */ - break; + case RCC_FDCANCLKSOURCE_HSE: + /* HSE is used as clock source for FDCAN*/ + /* FDCAN clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of FDCAN clock*/ __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection); @@ -841,40 +841,40 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /*FDCAN1 || FDCAN2*/ /*---------------------------- FMC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC) { - switch(PeriphClkInit->FmcClockSelection) + switch (PeriphClkInit->FmcClockSelection) { - case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ - /* Enable FMC Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_FMCCLKSOURCE_PLL: /* PLL is used as clock source for FMC*/ + /* Enable FMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* FMC clock source configuration done later after clock selection check */ - break; + /* FMC clock source configuration done later after clock selection check */ + break; - case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ + case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); - /* FMC clock source configuration done later after clock selection check */ - break; + /* FMC clock source configuration done later after clock selection check */ + break; - case RCC_FMCCLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ - /* FMC clock source configuration done later after clock selection check */ - break; + case RCC_FMCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of FMC clock */ + /* FMC clock source configuration done later after clock selection check */ + break; - case RCC_FMCCLKSOURCE_HCLK: - /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ - break; + case RCC_FMCCLKSOURCE_HCLK: + /* D1/CD HCLK clock selected as FMC kernel peripheral clock */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of FMC clock*/ __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection); @@ -887,7 +887,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- RTC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) { /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); @@ -898,19 +898,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while((PWR->CR1 & PWR_CR1_DBP) == 0U) + while ((PWR->CR1 & PWR_CR1_DBP) == 0U) { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { ret = HAL_TIMEOUT; break; } } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) + if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)) { /* Store the content of BDCR register before the reset of Backup Domain */ tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); @@ -922,15 +922,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */ - if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) { - if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { ret = HAL_TIMEOUT; break; @@ -938,7 +938,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } - if(ret == HAL_OK) + if (ret == HAL_OK) { __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } @@ -957,45 +957,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*-------------------------- USART1/6 configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16) { - switch(PeriphClkInit->Usart16ClockSelection) + switch (PeriphClkInit->Usart16ClockSelection) { - case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ - /* USART1/6 clock source configuration done later after clock selection check */ - break; + case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; - case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); - /* USART1/6 clock source configuration done later after clock selection check */ - break; + case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; - case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); - /* USART1/6 clock source configuration done later after clock selection check */ - break; + case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART1/6 clock source configuration done later after clock selection check */ + break; - case RCC_USART16CLKSOURCE_HSI: - /* HSI oscillator clock is used as source of USART1/6 clock */ - /* USART1/6 clock source configuration done later after clock selection check */ - break; + case RCC_USART16CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; - case RCC_USART16CLKSOURCE_CSI: - /* CSI oscillator clock is used as source of USART1/6 clock */ - /* USART1/6 clock source configuration done later after clock selection check */ - break; + case RCC_USART16CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; - case RCC_USART16CLKSOURCE_LSE: - /* LSE, oscillator is used as source of USART1/6 clock */ - /* USART1/6 clock source configuration done later after clock selection check */ - break; + case RCC_USART16CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART1/6 clock */ + /* USART1/6 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of USART1/6 clock */ __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection); @@ -1008,45 +1008,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578) { - switch(PeriphClkInit->Usart234578ClockSelection) + switch (PeriphClkInit->Usart234578ClockSelection) { - case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ - /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ - break; + case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; - case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); - /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ - break; + case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; - case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); - /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ - break; + case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; - case RCC_USART234578CLKSOURCE_HSI: - /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ - /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ - break; + case RCC_USART234578CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; - case RCC_USART234578CLKSOURCE_CSI: - /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ - /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ - break; + case RCC_USART234578CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; - case RCC_USART234578CLKSOURCE_LSE: - /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ - /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ - break; + case RCC_USART234578CLKSOURCE_LSE: + /* LSE, oscillator is used as source of USART2/3/4/5/7/8 clock */ + /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of USART2/3/4/5/7/8 clock */ __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection); @@ -1059,45 +1059,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*-------------------------- LPUART1 Configuration -------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) { - switch(PeriphClkInit->Lpuart1ClockSelection) + switch (PeriphClkInit->Lpuart1ClockSelection) { - case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ - /* LPUART1 clock source configuration done later after clock selection check */ - break; + case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; - case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE); - /* LPUART1 clock source configuration done later after clock selection check */ - break; + case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; - case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); - /* LPUART1 clock source configuration done later after clock selection check */ - break; + case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + /* LPUART1 clock source configuration done later after clock selection check */ + break; - case RCC_LPUART1CLKSOURCE_HSI: - /* HSI oscillator clock is used as source of LPUART1 clock */ - /* LPUART1 clock source configuration done later after clock selection check */ - break; + case RCC_LPUART1CLKSOURCE_HSI: + /* HSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; - case RCC_LPUART1CLKSOURCE_CSI: - /* CSI oscillator clock is used as source of LPUART1 clock */ - /* LPUART1 clock source configuration done later after clock selection check */ - break; + case RCC_LPUART1CLKSOURCE_CSI: + /* CSI oscillator clock is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; - case RCC_LPUART1CLKSOURCE_LSE: - /* LSE, oscillator is used as source of LPUART1 clock */ - /* LPUART1 clock source configuration done later after clock selection check */ - break; + case RCC_LPUART1CLKSOURCE_LSE: + /* LSE, oscillator is used as source of LPUART1 clock */ + /* LPUART1 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of LPUART1 clock */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); @@ -1110,47 +1110,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- LPTIM1 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { - switch(PeriphClkInit->Lptim1ClockSelection) + switch (PeriphClkInit->Lptim1ClockSelection) { - case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ - /* LPTIM1 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM1CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for LPTIM1*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ + case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* LPTIM1 clock source configuration done later after clock selection check */ - break; + /* LPTIM1 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); - /* LPTIM1 clock source configuration done later after clock selection check */ - break; + /* LPTIM1 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM1CLKSOURCE_LSE: - /* External low speed OSC clock is used as source of LPTIM1 clock*/ - /* LPTIM1 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM1CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM1CLKSOURCE_LSI: - /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ - /* LPTIM1 clock source configuration done later after clock selection check */ - break; - case RCC_LPTIM1CLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ - /* LPTIM1 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM1CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM1 clock*/ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM1CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */ + /* LPTIM1 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of LPTIM1 clock*/ __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); @@ -1163,47 +1163,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- LPTIM2 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) { - switch(PeriphClkInit->Lptim2ClockSelection) + switch (PeriphClkInit->Lptim2ClockSelection) { - case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ - /* LPTIM2 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM2CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ + case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* LPTIM2 clock source configuration done later after clock selection check */ - break; + /* LPTIM2 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + case RCC_LPTIM2CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM2*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); - /* LPTIM2 clock source configuration done later after clock selection check */ - break; + /* LPTIM2 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM2CLKSOURCE_LSE: - /* External low speed OSC clock is used as source of LPTIM2 clock*/ - /* LPTIM2 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM2CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM2CLKSOURCE_LSI: - /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ - /* LPTIM2 clock source configuration done later after clock selection check */ - break; - case RCC_LPTIM2CLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ - /* LPTIM2 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM2CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM2 clock*/ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM2CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */ + /* LPTIM2 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of LPTIM2 clock*/ __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); @@ -1216,47 +1216,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*---------------------------- LPTIM345 configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345) { - switch(PeriphClkInit->Lptim345ClockSelection) + switch (PeriphClkInit->Lptim345ClockSelection) { - case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ - /* LPTIM3/4/5 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM345CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* LPTIM3/4/5 clock source configuration done later after clock selection check */ - break; + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + case RCC_LPTIM345CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM3/4/5 */ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); - /* LPTIM3/4/5 clock source configuration done later after clock selection check */ - break; + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM345CLKSOURCE_LSE: - /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ - /* LPTIM3/4/5 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM345CLKSOURCE_LSE: + /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; - case RCC_LPTIM345CLKSOURCE_LSI: - /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ - /* LPTIM3/4/5 clock source configuration done later after clock selection check */ - break; - case RCC_LPTIM345CLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ - /* LPTIM3/4/5 clock source configuration done later after clock selection check */ - break; + case RCC_LPTIM345CLKSOURCE_LSI: + /* Internal low speed OSC clock is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; + case RCC_LPTIM345CLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */ + /* LPTIM3/4/5 clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of LPTIM3/4/5 clock */ __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection); @@ -1270,89 +1270,89 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/ #if defined(I2C5) - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235) { /* Check the parameters */ assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection)); - if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 ) + if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3) { - if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) - { - status = HAL_ERROR; - } + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } } - __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); + __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection); } #else - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123) { /* Check the parameters */ assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection)); - if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 ) + if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3) { - if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) - { - status = HAL_ERROR; - } + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) + { + status = HAL_ERROR; + } } - __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); + __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection); } #endif /* I2C5 */ /*------------------------------ I2C4 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) { /* Check the parameters */ assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 ) + if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3) { - if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK) + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) { status = HAL_ERROR; } } - __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); } /*---------------------------- ADC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) { - switch(PeriphClkInit->AdcClockSelection) + switch (PeriphClkInit->AdcClockSelection) { - case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ + case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); - /* ADC clock source configuration done later after clock selection check */ - break; + /* ADC clock source configuration done later after clock selection check */ + break; - case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE); + case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC*/ + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); - /* ADC clock source configuration done later after clock selection check */ - break; + /* ADC clock source configuration done later after clock selection check */ + break; - case RCC_ADCCLKSOURCE_CLKP: - /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ - /* ADC clock source configuration done later after clock selection check */ - break; + case RCC_ADCCLKSOURCE_CLKP: + /* HSI, HSE, or CSI oscillator is used as source of ADC clock */ + /* ADC clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of ADC clock*/ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); @@ -1365,36 +1365,36 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*------------------------------ USB Configuration -------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) { - switch(PeriphClkInit->UsbClockSelection) + switch (PeriphClkInit->UsbClockSelection) { - case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ - /* Enable USB Clock output generated form System USB . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_USBCLKSOURCE_PLL: /* PLL is used as clock source for USB*/ + /* Enable USB Clock output generated form System USB . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* USB clock source configuration done later after clock selection check */ - break; + /* USB clock source configuration done later after clock selection check */ + break; - case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ + case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/ - ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE); + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); - /* USB clock source configuration done later after clock selection check */ - break; + /* USB clock source configuration done later after clock selection check */ + break; - case RCC_USBCLKSOURCE_HSI48: - /* HSI48 oscillator is used as source of USB clock */ - /* USB clock source configuration done later after clock selection check */ - break; + case RCC_USBCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of USB clock */ + /* USB clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of USB clock*/ __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); @@ -1408,33 +1408,33 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*------------------------------------- SDMMC Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC) { /* Check the parameters */ assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection)); - switch(PeriphClkInit->SdmmcClockSelection) + switch (PeriphClkInit->SdmmcClockSelection) { - case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ - /* Enable SDMMC Clock output generated form System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_SDMMCCLKSOURCE_PLL: /* PLL is used as clock source for SDMMC*/ + /* Enable SDMMC Clock output generated form System PLL . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* SDMMC clock source configuration done later after clock selection check */ - break; + /* SDMMC clock source configuration done later after clock selection check */ + break; - case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/ - ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE); + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); - /* SDMMC clock source configuration done later after clock selection check */ - break; + /* SDMMC clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of SDMMC clock*/ __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection); @@ -1448,48 +1448,48 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(LTDC) /*-------------------------------------- LTDC Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { - if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK) + if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK) { - status=HAL_ERROR; + status = HAL_ERROR; } } #endif /* LTDC */ /*------------------------------ RNG Configuration -------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) { - switch(PeriphClkInit->RngClockSelection) + switch (PeriphClkInit->RngClockSelection) { - case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ - /* Enable RNG Clock output generated form System RNG . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); + case RCC_RNGCLKSOURCE_PLL: /* PLL is used as clock source for RNG*/ + /* Enable RNG Clock output generated form System RNG . */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* RNG clock source configuration done later after clock selection check */ - break; + /* RNG clock source configuration done later after clock selection check */ + break; - case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ + case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/ - /* RNG clock source configuration done later after clock selection check */ - break; + /* RNG clock source configuration done later after clock selection check */ + break; - case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ + case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/ - /* RNG clock source configuration done later after clock selection check */ - break; - case RCC_RNGCLKSOURCE_HSI48: - /* HSI48 oscillator is used as source of RNG clock */ - /* RNG clock source configuration done later after clock selection check */ - break; + /* RNG clock source configuration done later after clock selection check */ + break; + case RCC_RNGCLKSOURCE_HSI48: + /* HSI48 oscillator is used as source of RNG clock */ + /* RNG clock source configuration done later after clock selection check */ + break; - default: - ret = HAL_ERROR; - break; + default: + ret = HAL_ERROR; + break; } - if(ret == HAL_OK) + if (ret == HAL_OK) { /* Set the source of RNG clock*/ __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); @@ -1503,7 +1503,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*------------------------------ SWPMI1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); @@ -1513,7 +1513,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #if defined(HRTIM1) /*------------------------------ HRTIM1 clock Configuration ----------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) { /* Check the parameters */ assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); @@ -1523,7 +1523,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } #endif /*HRTIM1*/ /*------------------------------ DFSDM1 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) { /* Check the parameters */ assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); @@ -1534,7 +1534,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #if defined(DFSDM2_BASE) /*------------------------------ DFSDM2 Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2) { /* Check the parameters */ assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection)); @@ -1545,7 +1545,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk #endif /* DFSDM2 */ /*------------------------------------ TIM configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) { /* Check the parameters */ assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); @@ -1555,7 +1555,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*------------------------------------ CKPER configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER) { /* Check the parameters */ assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection)); @@ -1565,7 +1565,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*------------------------------ CEC Configuration ------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) { /* Check the parameters */ assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); @@ -1574,6 +1574,103 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); } + /*---------------------------- PLL2 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR) + { + ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + /*---------------------------- PLL3 configuration -------------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + + + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR) + { + ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE); + + if (ret == HAL_OK) + { + /*Nothing to do*/ + } + else + { + /* set overall return value */ + status = ret; + } + } + if (status == HAL_OK) { return HAL_OK; @@ -1596,18 +1693,18 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = - RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | - RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | - RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | - RCC_PERIPHCLK_CKPER; + RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 | + RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM345 | + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | + RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | + RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM | + RCC_PERIPHCLK_CKPER; #if defined(I2C5) -PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235; #else -PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; + PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; #endif /*I2C5*/ #if defined(RCC_CDCCIP1R_SAI2ASEL) PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A; @@ -1642,20 +1739,20 @@ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; #endif /* DSI */ /* Get the PLL3 Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos); - PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U; - PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U; - PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U; - PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U; + PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos); + PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U; + PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U; PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos); PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos); /* Get the PLL2 Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos); - PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U; - PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U; - PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U; - PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U; + PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos); + PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U; + PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U; PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos); PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos); @@ -1781,7 +1878,7 @@ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123; * * (*) : Available on some STM32H7 lines only. */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) { PLL1_ClocksTypeDef pll1_clocks; PLL2_ClocksTypeDef pll2_clocks; @@ -1795,924 +1892,1004 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) uint32_t srcclk; if (PeriphClk == RCC_PERIPHCLK_SAI1) - { + { - saiclocksource= __HAL_RCC_GET_SAI1_SOURCE(); + saiclocksource = __HAL_RCC_GET_SAI1_SOURCE(); - switch (saiclocksource) - { + switch (saiclocksource) + { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; + frequency = 0; } + break; + } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/ - { + { - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } - - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } - break; + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; } - case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; } - default : + + else { + /* In Case the CKPER is disabled*/ frequency = 0; - break; } + + break; + } + + case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; } } + } #if defined(SAI3) else if (PeriphClk == RCC_PERIPHCLK_SAI23) - { + { - saiclocksource= __HAL_RCC_GET_SAI23_SOURCE(); + saiclocksource = __HAL_RCC_GET_SAI23_SOURCE(); - switch (saiclocksource) - { + switch (saiclocksource) + { case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; } - - case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ + else { + frequency = 0; + } + break; + } - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } + case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */ + { - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } - break; + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; } - case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; } - default : + + else { + /* In Case the CKPER is disabled*/ frequency = 0; - break; } + + break; + } + + case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; } } + } #endif /* SAI3 */ #if defined(RCC_CDCCIP1R_SAI2ASEL) - else if (PeriphClk == RCC_PERIPHCLK_SAI2A) - { - saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE(); + else if (PeriphClk == RCC_PERIPHCLK_SAI2A) + { + saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE(); - switch (saiclocksource) - { + switch (saiclocksource) + { case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; } - - case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + else { + frequency = 0; + } + break; + } - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } + case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A */ + { - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } - break; + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; } - case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; } - default : + else { + /* In Case the CKPER is disabled*/ frequency = 0; - break; } + + break; + } + + case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; } + default : + { + frequency = 0; + break; + } } + + } #endif #if defined(RCC_CDCCIP1R_SAI2BSEL_0) else if (PeriphClk == RCC_PERIPHCLK_SAI2B) - { + { - saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE(); + saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE(); - switch (saiclocksource) - { + switch (saiclocksource) + { case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; } - - case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + else { + frequency = 0; + } + break; + } - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } + case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/ + { - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } - break; + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; } - case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; } - default : + else { + /* In Case the CKPER is disabled*/ frequency = 0; - break; } + break; + } + + case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; } } + } #endif #if defined(SAI4) else if (PeriphClk == RCC_PERIPHCLK_SAI4A) - { + { - saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE(); + saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE(); - switch (saiclocksource) - { + switch (saiclocksource) + { case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; } - - case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ + else { + frequency = 0; + } + break; + } - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } + case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ + { - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } - break; + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; } - case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; } - default : + else { + /* In Case the CKPER is disabled*/ frequency = 0; - break; } + + break; + } + + case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; } } + } else if (PeriphClk == RCC_PERIPHCLK_SAI4B) - { + { - saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE(); + saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE(); - switch (saiclocksource) - { + switch (saiclocksource) + { case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + + default : + { + frequency = 0; + break; + } + } + } +#endif /*SAI4*/ + else if (PeriphClk == RCC_PERIPHCLK_SPI123) + { + /* Get SPI1/2/3 clock source */ + srcclk = __HAL_RCC_GET_SPI123_SOURCE(); + + switch (srcclk) + { + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; } - - case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ + else + { + frequency = 0; + } + break; + } + + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ + { + + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); + + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } + + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; + } + + else + { + /* In Case the CKPER is disabled*/ + frequency = 0; + } + + break; + } + + case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SPI45) + { + /* Get SPI45 clock source */ + srcclk = __HAL_RCC_GET_SPI45_SOURCE(); + switch (srcclk) + { + case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */ + { + frequency = HAL_RCC_GetPCLK1Freq(); + break; + } + case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else { - - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } - - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } - - break; + frequency = 0; } - - case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ + break; + } + case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); + frequency = pll3_clocks.PLL3_Q_Frequency; } - - default : + else { frequency = 0; - break; } + break; } - } -#endif /*SAI4*/ - else if (PeriphClk == RCC_PERIPHCLK_SPI123) - { - /* Get SPI1/2/3 clock source */ - srcclk= __HAL_RCC_GET_SPI123_SOURCE(); - - switch (srcclk) + case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */ { - case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { - frequency = 0; - } - break; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); } - case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ + else { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; + frequency = 0; } - - case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ + break; + } + case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - } - else - { - frequency = 0; - } - break; + frequency = CSI_VALUE; } - - case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ + else { - - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } - - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } - - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } - - break; + frequency = 0; } - - case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */ + break; + } + case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { - frequency = EXTERNAL_CLOCK_VALUE; - break; + frequency = HSE_VALUE; } - default : + else { frequency = 0; - break; } + break; + } + default : + { + frequency = 0; + break; } } + } else if (PeriphClk == RCC_PERIPHCLK_ADC) - { - /* Get ADC clock source */ - srcclk= __HAL_RCC_GET_ADC_SOURCE(); + { + /* Get ADC clock source */ + srcclk = __HAL_RCC_GET_ADC_SOURCE(); - switch (srcclk) - { + switch (srcclk) + { case RCC_ADCCLKSOURCE_PLL2: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_ADCCLKSOURCE_PLL3: + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_R_Frequency; - } - else - { - frequency = 0; - } - break; } - - case RCC_ADCCLKSOURCE_CLKP: + else { + frequency = 0; + } + break; + } - ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) - { - /* In Case the CKPER Source is HSI */ - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } + case RCC_ADCCLKSOURCE_CLKP: + { - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) - { - /* In Case the CKPER Source is CSI */ - frequency = CSI_VALUE; - } + ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE(); - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) - { - /* In Case the CKPER Source is HSE */ - frequency = HSE_VALUE; - } + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) + { + /* In Case the CKPER Source is HSI */ + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } - else - { - /* In Case the CKPER is disabled*/ - frequency = 0; - } + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) + { + /* In Case the CKPER Source is CSI */ + frequency = CSI_VALUE; + } - break; + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) + { + /* In Case the CKPER Source is HSE */ + frequency = HSE_VALUE; } - default : + else { + /* In Case the CKPER is disabled*/ frequency = 0; - break; } + + break; + } + + default : + { + frequency = 0; + break; } } + } else if (PeriphClk == RCC_PERIPHCLK_SDMMC) - { - /* Get SDMMC clock source */ - srcclk= __HAL_RCC_GET_SDMMC_SOURCE(); + { + /* Get SDMMC clock source */ + srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); - switch (srcclk) - { + switch (srcclk) + { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { + } + else + { frequency = 0; - } - break; } + break; + } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_R_Frequency; - } - else - { - frequency = 0; - } - break; } - - default : + else { frequency = 0; - break; } + break; + } + + default : + { + frequency = 0; + break; } } + } else if (PeriphClk == RCC_PERIPHCLK_SPI6) - { - /* Get SPI6 clock source */ - srcclk= __HAL_RCC_GET_SPI6_SOURCE(); + { + /* Get SPI6 clock source */ + srcclk = __HAL_RCC_GET_SPI6_SOURCE(); - switch (srcclk) - { + switch (srcclk) + { case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */ - { - frequency = HAL_RCCEx_GetD3PCLK1Freq(); - break; - } + { + frequency = HAL_RCCEx_GetD3PCLK1Freq(); + break; + } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_Q_Frequency; - } - else - { + } + else + { frequency = 0; - } - break; } + break; + } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) - { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_Q_Frequency; - } - else - { + } + else + { frequency = 0; - } - break; } + break; + } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + } + else { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - } - else - { frequency = 0; - } - break; } + break; + } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) - { frequency = CSI_VALUE; - } - else - { - frequency = 0; - } - break; } + else + { + frequency = 0; + } + break; + } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - { frequency = HSE_VALUE; - } - else - { + } + else + { frequency = 0; - } - break; } + break; + } #if defined(RCC_SPI6CLKSOURCE_PIN) case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */ - { - frequency = EXTERNAL_CLOCK_VALUE; - break; - } + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } #endif /* RCC_SPI6CLKSOURCE_PIN */ default : - { - frequency = 0; - break; - } + { + frequency = 0; + break; } } + } else if (PeriphClk == RCC_PERIPHCLK_FDCAN) - { - /* Get FDCAN clock source */ - srcclk= __HAL_RCC_GET_FDCAN_SOURCE(); + { + /* Get FDCAN clock source */ + srcclk = __HAL_RCC_GET_FDCAN_SOURCE(); - switch (srcclk) - { + switch (srcclk) + { case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - { frequency = HSE_VALUE; - } - else - { + } + else + { frequency = 0; - } - break; } + break; + } case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) - { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; - } - else - { + } + else + { frequency = 0; - } - break; } + break; + } case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) - { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_Q_Frequency; - } - else - { - frequency = 0; - } - break; } - default : + else { frequency = 0; - break; } + break; + } + default : + { + frequency = 0; + break; } } + } else - { - frequency = 0; - } + { + frequency = 0; + } return frequency; } @@ -2728,10 +2905,10 @@ uint32_t HAL_RCCEx_GetD1PCLK1Freq(void) { #if defined(RCC_D1CFGR_D1PPRE) /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU)); #else -/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); + /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU)); #endif } @@ -2745,10 +2922,10 @@ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) { #if defined(RCC_D3CFGR_D3PPRE) /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU)); #else /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); + return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU)); #endif } /** @@ -2765,7 +2942,7 @@ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void) * @param PLL2_Clocks structure. * @retval None */ -void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) +void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) { uint32_t pllsource, pll2m, pll2fracen, hsivalue; float_t fracn2, pll2vco; @@ -2774,43 +2951,43 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) PLL2xCLK = PLL2_VCO / PLL2x */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12); + pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12); pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos; - fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3)); + fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3)); if (pll2m != 0U) { switch (pllsource) { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); - } - else - { - pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); - } - break; + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + else + { + pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + } + break; - case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ - pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; - default: - pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 ); - break; + default: + pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1); + break; } - PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9) + (float_t)1 )) ; - PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ; - PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ; + PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ; + PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ; + PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ; } else { @@ -2834,7 +3011,7 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks) * @param PLL3_Clocks structure. * @retval None */ -void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) +void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) { uint32_t pllsource, pll3m, pll3fracen, hsivalue; float_t fracn3, pll3vco; @@ -2843,41 +3020,41 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) PLL3xCLK = PLL3_VCO / PLLxR */ pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20) ; + pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ; pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos; - fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3)); + fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3)); if (pll3m != 0U) { switch (pllsource) { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); - } - else - { - pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); - } - break; - case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ - pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); - break; + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + else + { + pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; - default: - pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 ); - break; + default: + pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1); + break; } - PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9) + (float_t)1 )) ; - PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ; - PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ; + PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ; + PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ; + PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ; } else { @@ -2902,49 +3079,49 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks) * @param PLL1_Clocks structure. * @retval None */ -void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) +void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) { uint32_t pllsource, pll1m, pll1fracen, hsivalue; float_t fracn1, pll1vco; pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4); + pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; - fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); if (pll1m != 0U) { switch (pllsource) { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); - pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - } - else - { - pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - } - break; - case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ - pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) + { + hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3)); + pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + else + { + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + } + break; + case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */ + pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; - default: - pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + default: + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1); + break; } - PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + (float_t)1 )) ; - PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ; - PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ; + PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ; + PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ; + PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ; } else { @@ -2965,19 +3142,19 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) */ uint32_t HAL_RCCEx_GetD1SysClockFreq(void) { -uint32_t common_system_clock; + uint32_t common_system_clock; #if defined(RCC_D1CFGR_D1CPRE) - common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU); #else - common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); + common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU); #endif /* Update the SystemD2Clock global variable */ #if defined(RCC_D1CFGR_HPRE) - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); #else - SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); + SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); #endif #if defined(DUAL_CORE) && defined(CORE_CM4) @@ -3306,15 +3483,15 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) /* Wait for CRS flag or time-out detection */ do { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { crsstatus = RCC_CRS_TIMEOUT; } } /* Check CRS SYNCOK flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) { /* CRS SYNC event OK */ crsstatus |= RCC_CRS_SYNCOK; @@ -3324,7 +3501,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) } /* Check CRS SYNCWARN flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) { /* CRS SYNC warning */ crsstatus |= RCC_CRS_SYNCWARN; @@ -3334,7 +3511,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) } /* Check CRS TRIM overflow flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_TRIMOVF; @@ -3344,7 +3521,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) } /* Check CRS Error flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) { /* CRS SYNC Error */ crsstatus |= RCC_CRS_SYNCERR; @@ -3354,7 +3531,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) } /* Check CRS SYNC Missed flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) { /* CRS SYNC Missed */ crsstatus |= RCC_CRS_SYNCMISS; @@ -3364,12 +3541,13 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) } /* Check CRS Expected SYNC flag */ - if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) + if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) { /* frequency error counter reached a zero value */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } - } while(RCC_CRS_NONE == crsstatus); + } + while (RCC_CRS_NONE == crsstatus); return crsstatus; } @@ -3386,7 +3564,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) uint32_t itsources = READ_REG(CRS->CR); /* Check CRS SYNCOK flag */ - if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) + if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) { /* Clear CRS SYNC event OK flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); @@ -3395,7 +3573,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) HAL_RCCEx_CRS_SyncOkCallback(); } /* Check CRS SYNCWARN flag */ - else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) + else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) { /* Clear CRS SYNCWARN flag */ WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); @@ -3404,7 +3582,7 @@ void HAL_RCCEx_CRS_IRQHandler(void) HAL_RCCEx_CRS_SyncWarnCallback(); } /* Check CRS Expected SYNC flag */ - else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) + else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) { /* frequency error counter reached a zero value */ WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); @@ -3415,17 +3593,17 @@ void HAL_RCCEx_CRS_IRQHandler(void) /* Check CRS Error flags */ else { - if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) + if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) { - if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) + if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) { crserror |= RCC_CRS_SYNCERR; } - if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) + if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) { crserror |= RCC_CRS_SYNCMISS; } - if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) + if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) { crserror |= RCC_CRS_TRIMOVF; } @@ -3527,7 +3705,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN)); /* Check that PLL2 OSC clock source is already set */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) { return HAL_ERROR; } @@ -3542,9 +3720,9 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) { - if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -3573,11 +3751,11 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D __HAL_RCC_PLL2FRACN_ENABLE(); /* Enable the PLL2 clock output */ - if(Divider == DIVIDER_P_UPDATE) + if (Divider == DIVIDER_P_UPDATE) { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP); } - else if(Divider == DIVIDER_Q_UPDATE) + else if (Divider == DIVIDER_Q_UPDATE) { __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ); } @@ -3593,9 +3771,9 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D tickstart = HAL_GetTick(); /* Wait till PLL2 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) { - if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -3631,7 +3809,7 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN)); /* Check that PLL3 OSC clock source is already set */ - if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE) { return HAL_ERROR; } @@ -3645,9 +3823,9 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL3 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) { - if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -3676,11 +3854,11 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D __HAL_RCC_PLL3FRACN_ENABLE(); /* Enable the PLL3 clock output */ - if(Divider == DIVIDER_P_UPDATE) + if (Divider == DIVIDER_P_UPDATE) { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP); } - else if(Divider == DIVIDER_Q_UPDATE) + else if (Divider == DIVIDER_Q_UPDATE) { __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ); } @@ -3696,9 +3874,9 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D tickstart = HAL_GetTick(); /* Wait till PLL3 is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) { - if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -3717,7 +3895,7 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D void HAL_RCCEx_LSECSS_IRQHandler(void) { /* Check RCC LSE CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) + if (__HAL_RCC_GET_IT(RCC_IT_LSECSS)) { /* Clear RCC LSE CSS pending bit */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c index 105fd26d0d..76d1601f2d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng.c @@ -417,8 +417,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -472,8 +470,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -492,8 +488,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hrng); if (HAL_RNG_STATE_READY == hrng->State) { @@ -547,8 +541,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hrng); return status; } @@ -714,8 +706,9 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t be used as it may not have enough entropy */ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { - /* Update the error code */ + /* Update the error code and status */ hrng->ErrorCode = HAL_RNG_ERROR_SEED; + status = HAL_ERROR; /* Clear bit DRDY */ CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c index a063df7772..97190acc25 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rng_ex.c @@ -54,7 +54,7 @@ */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNGEx Private Constants +/** @addtogroup RNG_Ex_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c index 467387345d..833854bddf 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc.c @@ -239,9 +239,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); -#if defined(RTC_CR_TAMPALRM_PU) +#if defined(TAMP) assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); -#endif /* RTC_CR_TAMPALRM_PU */ +#endif /* TAMP */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) if(hrtc->State == HAL_RTC_STATE_RESET) @@ -257,27 +257,15 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback; -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback; -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; -#endif /* TAMP_CR1_ITAMP8E */ +#endif /* TAMP */ if(hrtc->MspInitCallback == NULL) @@ -306,45 +294,53 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - if (status == HAL_OK) + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { -#if defined(RTC_CR_TAMPOE) - /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */ - hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE); -#else /* RTC_CR_TAMPOE */ - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL); -#endif /* RTC_CR_TAMPOE */ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { +#if defined(TAMP) + /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */ + hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE); +#else + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL); +#endif /* TAMP */ - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos); + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } if(status == HAL_OK) { -#if defined(RTC_CR_TAMPALRM_PU) && defined(RTC_CR_TAMPALRM_TYPE) && defined(RTC_CR_OUT2EN) +#if defined(TAMP) hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN); hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); -#endif /* RTC_CR_TAMPALRM_TYPE && RTC_CR_OUT2EN && RTC_CR_TAMPALRM_PU */ - -#if defined(RTC_OR_ALARMOUTTYPE) && defined(RTC_OR_OUT_RMP) +#else hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); -#endif /* ALARMOUTTYPE && RTC_OR_OUT_RMP */ +#endif /* TAMP */ } - } + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + } + if (status == HAL_OK) { /* Set RTC state */ @@ -378,72 +374,75 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Enter Initialization mode */ status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) { /* Reset TR, DR and CR registers */ hrtc->Instance->TR = 0x00000000U; hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= RTC_CR_WUCKSEL; + /* Reset All CR bits except CR[2:0] (which cannot be written before bit + WUTE of CR is cleared) */ + hrtc->Instance->CR = 0x00000000U; + + /* Wait till WUTWF is set (to be able to reset CR[2:0] and WUTR) and if + timeout is reached exit */ tickstart = HAL_GetTick(); - /* Wait till WUTWF flag is set and if Time out is reached exit */ -#if defined(RTC_ICSR_WUTWF) +#if defined(TAMP) while ((((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) && (status != HAL_TIMEOUT)) -#endif /* RTC_ICSR_WUTWF */ -#if defined(RTC_ISR_WUTWF) - while ((((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) && (status != HAL_TIMEOUT)) -#endif /* RTC_ISR_WUTWF */ +#else + while ((((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) && (status != HAL_TIMEOUT)) +#endif /* TAMP */ + { + if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - status = HAL_TIMEOUT; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; - } } + } + } + + if (status == HAL_OK) + { + /* Reset RTC CR register bits [2:0] */ + hrtc->Instance->CR = 0x00000000U; + + /* Reset other RTC registers */ + hrtc->Instance->WUTR = RTC_WUTR_WUT; + hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); + hrtc->Instance->ALRMAR = 0x00000000U; + hrtc->Instance->ALRMBR = 0x00000000U; + hrtc->Instance->SHIFTR = 0x00000000U; + hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->ALRMASSR = 0x00000000U; + hrtc->Instance->ALRMBSSR = 0x00000000U; /* Exit initialization mode */ status = RTC_ExitInitMode(hrtc); - if (status == HAL_OK) - { - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= 0x00000000U; - - /* Reset other RTC registers */ - hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU)); - hrtc->Instance->ALRMAR = 0x00000000U; - hrtc->Instance->ALRMBR = 0x00000000U; - hrtc->Instance->SHIFTR = 0x00000000U; - hrtc->Instance->CALR = 0x00000000U; - hrtc->Instance->ALRMASSR = 0x00000000U; - hrtc->Instance->ALRMBSSR = 0x00000000U; - -#if defined(RTC_ISR_INIT) - /* Reset Tamper configuration register */ - hrtc->Instance->TAMPCR = 0x00000000U; - - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000U; -#endif /* RTC_ISR_INIT */ - } } if(status == HAL_OK) { -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) /* Reset TAMP registers */ ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->CR1 = 0xFFFF0000U; ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->CR2 = 0x00000000U; -#endif /* TAMP_CR1_TAMP1E */ +#else + /* Reset Tamper configuration register */ + hrtc->Instance->TAMPCR = 0x00000000U; + + /* Reset Option register */ + hrtc->Instance->OR = 0x00000000U; +#endif /* TAMP */ /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -542,47 +541,35 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call hrtc->Tamper3EventCallback = pCallback; break; -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : hrtc->InternalTamper1EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : hrtc->InternalTamper2EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : hrtc->InternalTamper3EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : hrtc->InternalTamper4EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : hrtc->InternalTamper5EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : hrtc->InternalTamper6EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : hrtc->InternalTamper8EventCallback = pCallback; break; -#endif /* TAMP_CR1_ITAMP8E */ +#endif /* TAMP */ case HAL_RTC_MSPINIT_CB_ID : hrtc->MspInitCallback = pCallback; @@ -630,7 +617,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call /** * @brief Unregister an RTC Callback - * RTC callabck is redirected to the weak predefined callback + * RTC callback is redirected to the weak predefined callback * @param hrtc RTC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -691,47 +678,35 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ break; -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID : hrtc->InternalTamper1EventCallback = HAL_RTCEx_InternalTamper1EventCallback; break; -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID : hrtc->InternalTamper2EventCallback = HAL_RTCEx_InternalTamper2EventCallback; break; -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; break; -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID : hrtc->InternalTamper4EventCallback = HAL_RTCEx_InternalTamper4EventCallback; break; -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; break; -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; break; -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; break; -#endif /* TAMP_CR1_ITAMP8E */ +#endif /* TAMP */ case HAL_RTC_MSPINIT_CB_ID : hrtc->MspInitCallback = HAL_RTC_MspInit; @@ -1233,13 +1208,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - #if defined(RTC_ICSR_ALRAWF) + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ +#if defined(TAMP) while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U) - #endif /* RTC_ICSR_ALRAWF */ - #if defined(RTC_ISR_ALRAWF) - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - #endif /* RTC_ISR_ALRAWF */ +#else + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1271,13 +1245,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - #if defined(RTC_ICSR_ALRBWF) + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ +#if defined(TAMP) while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U) - #endif /* RTC_ICSR_ALRBWF */ - #if defined(RTC_ISR_ALRBWF) - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) - #endif /* RTC_ISR_ALRBWF */ +#else + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1425,13 +1398,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - #if defined(RTC_ICSR_ALRAWF) + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ +#if defined(TAMP) while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U) - #endif /* RTC_ICSR_ALRAWF */ - #if defined(RTC_ISR_ALRAWF) - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - #endif /* RTC_ISR_ALRAWF */ +#else + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1464,13 +1436,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ -#if defined(RTC_ICSR_ALRBWF) + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ +#if defined(TAMP) while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U) -#endif /* RTC_ICSR_ALRBWF */ -#if defined(RTC_ISR_ALRBWF) - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) -#endif /* RTC_ISR_ALRBWF */ +#else + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1556,13 +1527,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ -#if defined(RTC_ICSR_ALRAWF) + /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ +#if defined(TAMP) while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U) -#endif /* RTC_ICSR_ALRAWF */ -#if defined(RTC_ISR_ALRAWF) - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) -#endif /* RTC_ISR_ALRAWF */ +#else + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1588,13 +1558,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ -#if defined(RTC_ICSR_ALRBWF) + /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ +#if defined(TAMP) while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U) -#endif /* RTC_ICSR_ALRBWF */ -#if defined(RTC_ISR_ALRBWF) - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) -#endif /* RTC_ISR_ALRBWF */ +#else + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1712,40 +1681,36 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); #endif /* DUAL_CORE */ -#if defined(RTC_MISR_ALRAMF) +#if defined(TAMP) /* Get interrupt status */ uint32_t tmp = hrtc->Instance->MISR; - if((tmp & RTC_MISR_ALRAMF) != 0u) + if((tmp & RTC_FLAG_ALRAF) != 0u) { /* Clear the AlarmA interrupt pending bit */ - hrtc->Instance->SCR = RTC_SCR_CALRAF; + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + /* Call Alarm A Callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Compare Match registered Callback */ hrtc->AlarmAEventCallback(hrtc); #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ HAL_RTC_AlarmAEventCallback(hrtc); #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } -#endif /* RTC_MISR_ALRAMF */ -#if defined(RTC_MISR_ALRBMF) if((tmp & RTC_MISR_ALRBMF) != 0u) { /* Clear the AlarmB interrupt pending bit */ hrtc->Instance->SCR = RTC_SCR_CALRBF; + /* Call Alarm B Callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Compare Match registered Callback */ hrtc->AlarmBEventCallback(hrtc); #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ HAL_RTCEx_AlarmBEventCallback(hrtc); #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } -#endif /* RTC_MISR_ALRBMF */ - -#if defined(RTC_ISR_ALRAF) +#else /* Get the AlarmA interrupt source enable status */ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) { @@ -1762,9 +1727,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } -#endif /* RTC_ISR_ALRAF */ -#if defined(RTC_ISR_ALRBF) /* Get the AlarmB interrupt source enable status */ if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) { @@ -1782,7 +1745,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } -#endif /* RTC_ISR_ALRBF */ +#endif /* TAMP */ /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1872,23 +1835,21 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart; - /* Clear RSF flag */ -#if defined(RTC_ICSR_RSF) - hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK; -#endif /* RTC_ICSR_RSF */ -#if defined(RTC_ISR_RSF) - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; -#endif /* RTC_ISR_RSF */ + /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ +#if defined(TAMP) + hrtc->Instance->ICSR = ((uint32_t)(RTC_RSF_MASK & RTC_ICSR_RESERVED_MASK)); +#else + hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); +#endif /* TAMP */ tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ -#if defined(RTC_ICSR_RSF) +#if defined(TAMP) while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U) -#endif /* RTC_ICSR_RSF */ -#if defined(RTC_ISR_RSF) +#else while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) -#endif /* RTC_ISR_RSF */ +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1951,33 +1912,27 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) uint32_t tickstart; HAL_StatusTypeDef status = HAL_OK; /* Check if the Initialization mode is set */ -#if defined(RTC_ICSR_INITF) - if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) +#if defined(TAMP) + if ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) { /* Set the Initialization mode */ SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT); tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ + + /* Wait till RTC is in INIT state and if timeout is reached exit */ while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) - { - if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - hrtc->State = HAL_RTC_STATE_TIMEOUT; - } - } - } -#endif /* RTC_ICSR_INITF */ -#if defined(RTC_ISR_INITF) - if((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) +#else + if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) { /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ + + /* Wait till RTC is in INIT state and if timeout is reached exit */ while (((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT)) +#endif /* TAMP */ { if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -1986,7 +1941,6 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) } } } -#endif /* RTC_ISR_INITF */ return status; } @@ -2001,17 +1955,14 @@ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) HAL_StatusTypeDef status = HAL_OK; /* Check if the Initialization mode is set */ -#if defined(RTC_ICSR_INITF) /* Exit Initialization mode */ +#if defined(TAMP) CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); - -#elif defined(RTC_ISR_INITF) - - /* Exit Initialization mode */ +#else CLEAR_BIT(RTC->ISR, RTC_ISR_INITF); +#endif /* TAMP */ -#endif /* RTC_ISR_INITF */ /* If CR_BYPSHAD bit = 0, wait for synchro */ if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c index ba820c6b25..252dce91b8 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rtc_ex.c @@ -462,7 +462,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe * @{ */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) /** * @brief Set Tamper * @param hrtc RTC handle @@ -529,8 +529,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe return HAL_OK; } -#endif /* TAMP_CR1_TAMP1E */ -#if defined (RTC_TAMPCR_TAMP1E) +#else /** * @brief Set Tamper. * @note By calling this API we disable the tamper interrupt for all tampers. @@ -580,89 +579,65 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe /* Configure the tamper backup registers erasure bit */ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE); } -#endif /* RTC_TAMPCR_TAMP3E */ } else { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); } -#endif /* RTC_TAMPCR_TAMP3E */ } /* Configure the tamper flags masking bit */ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF); } -#endif /* RTC_TAMPCR_TAMP3E */ } else { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); } -#endif /* RTC_TAMPCR_TAMP3E */ } /* Clearing remaining fields before setting them */ @@ -687,9 +662,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe return HAL_OK; } -#endif /* RTC_TAMPCR_TAMP1E */ +#endif /* TAMP */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) /** * @brief Set Tamper with interrupt. * @param hrtc RTC handle @@ -765,8 +740,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp return HAL_OK; } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP1E) +#else /** * @brief Set Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. @@ -817,89 +791,65 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp /* Configure the tamper backup registers erasure bit */ if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE); } -#endif /* RTC_TAMPCR_TAMP3E */ } else { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); } -#endif /* RTC_TAMPCR_TAMP3E */ } /* Configure the tamper flags masking bit */ if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF); } -#endif /* RTC_TAMPCR_TAMP3E */ } else { -#if defined(RTC_TAMPCR_TAMP1E) if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) { tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); } -#endif /* RTC_TAMPCR_TAMP3E */ } /* Clearing remaining fields before setting them */ @@ -943,9 +893,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp return HAL_OK; } -#endif /* RTC_TAMPCR_TAMP1E */ +#endif /* TAMP */ -#if defined(TAMP_CR1_TAMP1E) +#if defined(TAMP) /** * @brief Deactivate Tamper. * @param hrtc RTC handle @@ -976,8 +926,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t return HAL_OK; } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP1E) +#else /** * @brief Deactivate Tamper. * @param hrtc RTC handle @@ -1001,24 +950,20 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); /* Disable the selected Tamper interrupt */ -#if defined(RTC_TAMPCR_TAMP1E) if ((Tamper & RTC_TAMPER_1) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) + if ((Tamper & RTC_TAMPER_2) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) + if ((Tamper & RTC_TAMPER_3) != 0U) { hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); } -#endif /* RTC_TAMPCR_TAMP3E */ hrtc->State = HAL_RTC_STATE_READY; @@ -1027,9 +972,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t return HAL_OK; } -#endif /* RTC_TAMPCR_TAMP1E */ +#endif /* TAMP */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) /** * @brief Set Internal Tamper * @param hrtc RTC handle @@ -1111,9 +1056,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui return HAL_OK; } -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_ATCR1_TAMP1AM) /** * @brief Set all active Tampers at the same time. * @param hrtc RTC handle @@ -1129,11 +1072,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active { assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase)); assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag)); - /* Mask flag only supported by TAMPER 1, 2 and 3 */ + /* Mask flag only supported by TAMPER 1, 2, and 3 */ assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3))); } + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection)); -#endif /* #ifdef USE_FULL_ASSERT */ +#endif /* USE_FULL_ASSERT */ /* Active Tampers must not be already enabled */ if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U) @@ -1213,7 +1157,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]); } - /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + /* Wait till RTC SEEDF flag is set and if timeout is reached exit */ tickstart = HAL_GetTick(); while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0u) { @@ -1226,9 +1170,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active return HAL_OK; } -#endif /* TAMP_ATCR1_TAMP1AM */ -#if defined(TAMP_ATSEEDR_SEED) /** * @brief Write a new seed. Active tamper must be enabled. * @param hrtc RTC handle @@ -1250,7 +1192,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe WRITE_REG(TAMP->ATSEEDR, pSeed[i]); } - /* Wait till RTC SEEDF flag is set and if Time out is reached exit */ + /* Wait till RTC SEEDF flag is set and if timeout is reached exit */ tickstart = HAL_GetTick(); while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) { @@ -1263,9 +1205,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe return HAL_OK; } -#endif /* TAMP_ATSEEDR_SEED */ -#if defined(TAMP_ATCR1_TAMP1AM) /** * @brief Deactivate all Active Tampers at the same time. * @param hrtc RTC handle @@ -1298,7 +1238,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) return HAL_OK; } -#endif /* TAMP_ATCR1_TAMP1AM */ +#endif /* TAMP */ /** * @} @@ -1311,11 +1251,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) */ /** - * @brief Handle TimeStamp interrupt request. + * @brief Handle Tamper and TimeStamp interrupt request. * @param hrtc RTC handle * @retval None */ -#if defined(RTC_MISR_TSMF) +#if defined(TAMP) void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { @@ -1343,151 +1283,130 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) /* Immediately clear flags */ tamp->SCR = tmp; -#if defined(TAMP_CR1_TAMP1E) - /* Check Tamper1 status */ + /* Check Tamper 1 status */ if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call Tamper 1 Event registered Callback */ hrtc->Tamper1EventCallback(hrtc); #else - /* Tamper1 callback */ + /* Tamper 1 callback */ HAL_RTCEx_Tamper1EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_TAMP1E */ -#if defined(TAMP_CR1_TAMP2E) - /* Check Tamper2 status */ + /* Check Tamper 2 status */ if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call Tamper 2 Event registered Callback */ hrtc->Tamper2EventCallback(hrtc); #else - /* Tamper2 callback */ + /* Tamper 2 callback */ HAL_RTCEx_Tamper2EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_TAMP2E */ -#if defined(TAMP_CR1_TAMP3E) - /* Check Tamper3 status */ + /* Check Tamper 3 status */ if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /* Call Tamper 3 Event registered Callback */ hrtc->Tamper3EventCallback(hrtc); #else - /* Tamper3 callback */ + /* Tamper 3 callback */ HAL_RTCEx_Tamper3EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_TAMP3E */ -#if defined(TAMP_CR1_ITAMP1E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 1 status */ if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 1 Event registered callback */ hrtc->InternalTamper1EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 1 Event by-default callback */ HAL_RTCEx_InternalTamper1EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP1E */ -#if defined(TAMP_CR1_ITAMP2E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 2 status */ if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 2 Event registered callback */ hrtc->InternalTamper2EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 2 Event by-default callback */ HAL_RTCEx_InternalTamper2EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP2E */ -#if defined(TAMP_CR1_ITAMP3E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 3 status */ if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 3 Event registered callback */ hrtc->InternalTamper3EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 3 Event by-default callback */ HAL_RTCEx_InternalTamper3EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP3E */ -#if defined(TAMP_CR1_ITAMP4E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 4 status */ if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 4 Event registered callback */ hrtc->InternalTamper4EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 4 Event by-default callback */ HAL_RTCEx_InternalTamper4EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP4E */ -#if defined(TAMP_CR1_ITAMP5E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 5 status */ if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 5 Event registered callback */ hrtc->InternalTamper5EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 5 Event by-default callback */ HAL_RTCEx_InternalTamper5EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP5E */ -#if defined(TAMP_CR1_ITAMP6E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 6 status */ if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 6 Event registered callback */ hrtc->InternalTamper6EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 6 Event by-default callback */ HAL_RTCEx_InternalTamper6EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP6E */ -#if defined(TAMP_CR1_ITAMP8E) - /* Check Internal Tamper status */ + /* Check Internal Tamper 8 status */ if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) { #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - /* Call Internal Tamper Event registered callback */ + /* Call Internal Tamper 8 Event registered callback */ hrtc->InternalTamper8EventCallback(hrtc); #else - /* Call Internal Tamper Event by-default callback */ + /* Call Internal Tamper 8 Event by-default callback */ HAL_RTCEx_InternalTamper8EventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* TAMP_CR1_ITAMP8E */ /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#endif /* RTC_MISR_TSMF */ -#if defined(RTC_ISR_TSF) +#else void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ @@ -1522,17 +1441,16 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } } -#if defined(RTC_TAMPCR_TAMP1E) - /* Get the Tamper1 interrupt source enable status */ + /* Get the Tamper 1 interrupt source enable status */ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) { - /* Get the pending status of the Tamper1 Interrupt */ + /* Get the pending status of the Tamper 1 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) { - /* Clear the Tamper1 interrupt pending bit */ + /* Clear the Tamper 1 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - /* Tamper1 callback */ + /* Tamper 1 callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper1EventCallback(hrtc); #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ @@ -1540,19 +1458,17 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_TAMPCR_TAMP2E) - /* Get the Tamper2 interrupt source enable status */ + /* Get the Tamper 2 interrupt source enable status */ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) { - /* Get the pending status of the Tamper2 Interrupt */ + /* Get the pending status of the Tamper 2 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) { - /* Clear the Tamper2 interrupt pending bit */ + /* Clear the Tamper 2 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - /* Tamper2 callback */ + /* Tamper 2 callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper2EventCallback(hrtc); #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ @@ -1560,19 +1476,17 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } -#endif /* RTC_TAMPCR_TAMP2E */ -#if defined(RTC_TAMPCR_TAMP3E) - /* Get the Tamper3 interrupts source enable status */ + /* Get the Tamper 3 interrupts source enable status */ if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) { - /* Get the pending status of the Tamper3 Interrupt */ + /* Get the pending status of the Tamper 3 Interrupt */ if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) { - /* Clear the Tamper3 interrupt pending bit */ + /* Clear the Tamper 3 interrupt pending bit */ __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - /* Tamper3 callback */ + /* Tamper 3 callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->Tamper3EventCallback(hrtc); #else /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ @@ -1580,12 +1494,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */ } } -#endif /* RTC_TAMPCR_TAMP3E */ /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; } -#endif /* RTC_ISR_TSF */ +#endif /* TAMP */ /** * @brief TimeStamp callback. @@ -1612,7 +1525,6 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) * @{ */ -#if defined(RTC_TAMPER_1) /** * @brief Tamper 1 callback. * @param hrtc RTC handle @@ -1627,9 +1539,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef * hrtc) the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file */ } -#endif /* RTC_TAMPER_1 */ -#if defined(RTC_TAMPER_2) /** * @brief Tamper 2 callback. * @param hrtc RTC handle @@ -1644,9 +1554,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef * hrtc) the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } -#endif /* RTC_TAMPER_2 */ -#if defined(RTC_TAMPER_3) /** * @brief Tamper 3 callback. * @param hrtc RTC handle @@ -1661,8 +1569,8 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef * hrtc) the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file */ } -#endif /* RTC_TAMPER_3 */ +#if defined(TAMP) /** * @brief Internal Tamper 1 callback. * @param hrtc RTC handle @@ -1767,6 +1675,8 @@ __weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file */ } +#endif /* TAMP */ + /** * @} */ @@ -1826,7 +1736,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 * @{ */ -#if defined(RTC_TAMPER_1) /** * @brief Handle Tamper1 Polling. * @param hrtc RTC handle @@ -1858,9 +1767,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } -#endif /* RTC_TAMPER_1 */ -#if defined(RTC_TAMPER_2) /** * @brief Handle Tamper2 Polling. * @param hrtc RTC handle @@ -1892,9 +1799,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } -#endif /* RTC_TAMPER_2 */ -#if defined(RTC_TAMPER_3) /** * @brief Handle Tamper3 Polling. * @param hrtc RTC handle @@ -1926,9 +1831,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef * hrtc, uint32 return HAL_OK; } -#endif /* RTC_TAMPER_3 */ -#if defined(TAMP_CR1_ITAMP1E) +#if defined(TAMP) /** * @brief Internal Tamper event polling. * @param hrtc RTC handle @@ -1961,7 +1865,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, return HAL_OK; } -#endif /* TAMP_CR1_ITAMP1E */ +#endif /* TAMP */ /** * @} @@ -2010,36 +1914,34 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Poll WUTWF until it is set in RTC_ICSR / RTC_ISR to make sure the access to wakeup autoreload counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in calendar initialization mode. */ -#if defined(RTC_ISR_INITF) +#if defined(TAMP) + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + + while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U) +#else if (READ_BIT(RTC->ISR, RTC_ISR_INITF) == 0U) -#endif /* RTC_ISR_INITF */ -#if defined(RTC_ICSR_INITF) - if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) -#endif /* RTC_ICSR_INITF */ + { + tickstart = HAL_GetTick(); + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) +#endif /* TAMP */ { - tickstart = HAL_GetTick(); - -#if defined(RTC_ICSR_WUTWF) - while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U) -#endif /* RTC_ICSR_WUTWF */ -#if defined(RTC_ISR_WUTWF) - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) -#endif /* RTC_ISR_WUTWF */ - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } } + } /* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */ uint32_t CR_tmp = hrtc->Instance->CR; @@ -2093,36 +1995,34 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in calendar initialization mode. */ -#if defined(RTC_ISR_INITF) +#if defined(TAMP) + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + + while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U) +#else if (READ_BIT(RTC->ISR, RTC_ISR_INITF) == 0U) -#endif /* RTC_ISR_INITF */ -#if defined(RTC_ICSR_INITF) - if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) -#endif /* RTC_ICSR_INITF */ + { + tickstart = HAL_GetTick(); + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) +#endif /* TAMP */ { - tickstart = HAL_GetTick(); - -#if defined(RTC_ICSR_WUTWF) - while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U) -#endif /* RTC_ICSR_WUTWF */ -#if defined(RTC_ISR_WUTWF) - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) -#endif /* RTC_ISR_WUTWF */ - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } } + } /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; @@ -2192,13 +2092,12 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - #if defined(RTC_ICSR_WUTWF) - while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U) - #endif /* RTC_ICSR_WUTWF */ - #if defined(RTC_ISR_WUTWF) - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - #endif /* RTC_ISR_WUTWF */ + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ +#if defined(TAMP) + while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U) +#else + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) +#endif /* TAMP */ { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -2257,7 +2156,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); #endif /* DUAL_CORE */ -#if defined(RTC_MISR_WUTMF) +#if defined(TAMP) /* Get the pending status of the WAKEUPTIMER Interrupt */ if ((hrtc->Instance->MISR & RTC_MISR_WUTMF) != 0u) { @@ -2272,8 +2171,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* RTC_MISR_WUTMF */ -#if defined(RTC_ISR_WUTF) +#else /* Get the pending status of the WAKEUPTIMER Interrupt */ if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) { @@ -2288,7 +2186,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ } -#endif /* RTC_ISR_WUTF */ +#endif /* TAMP */ /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -2383,12 +2281,11 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint assert_param(IS_RTC_BKP(BackupRegister)); /* Point on address of first backup register */ -#if defined(TAMP_BKP0R) +#if defined(TAMP) tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); -#endif /* TAMP_BKP0R */ -#if defined(RTC_BKP0R) +#else tmp = (uint32_t) & (hrtc->Instance->BKP0R); -#endif /* RTC_BKP0R */ +#endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2413,12 +2310,11 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister) assert_param(IS_RTC_BKP(BackupRegister)); /* Point on address of first backup register */ -#if defined(TAMP_BKP0R) +#if defined(TAMP) tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R); -#endif /* TAMP_BKP0R */ -#if defined(RTC_BKP0R) +#else tmp = (uint32_t) & (hrtc->Instance->BKP0R); -#endif /* RTC_BKP0R */ +#endif /* TAMP */ tmp += (BackupRegister * 4U); @@ -2494,39 +2390,39 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef * hrtc, uint32_t Sm /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); +#if defined(TAMP) /* check if a calibration operation is pending */ -#if defined(RTC_ICSR_RECALPF) if ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) -#endif /* RTC_ICSR_RECALPF */ -#if defined(RTC_ISR_RECALPF) - if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) -#endif /* RTC_ISR_RECALPF */ + { + tickstart = HAL_GetTick(); + + /* Wait for pending calibration operation to finish */ + while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) +#else + /* check if a calibration operation is pending */ + if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) + { + tickstart = HAL_GetTick(); + + /* Wait for pending calibration operation to finish */ + while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) +#endif /* TAMP */ { - tickstart = HAL_GetTick(); - - /* Wait for pending calibration operation to finish */ -#if defined(RTC_ICSR_RECALPF) - while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U) -#endif /* RTC_ICSR_RECALPF */ -#if defined(RTC_ISR_RECALPF) - while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) -#endif /* RTC_ISR_RECALPF */ - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } } + } /* Configure the Smooth calibration settings */ MODIFY_REG(hrtc->Instance->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); @@ -2574,12 +2470,11 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef * hrtc, uint32_t S tickstart = HAL_GetTick(); /* Wait until the shift is completed */ -#if defined(RTC_ICSR_SHPF) +#if defined(TAMP) while ((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U) -#endif /* RTC_ICSR_SHPF */ -#if defined(RTC_ISR_SHPF) +#else while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) -#endif /* RTC_ISR_SHPF */ +#endif /* TAMP */ { if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { @@ -2860,7 +2755,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef * hrtc) return HAL_OK; } -#if defined(TAMP_COUNTR) +#if defined(TAMP) /** * @brief Increment Monotonic counter. * @param hrtc RTC handle @@ -2899,7 +2794,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_ return HAL_OK; } -#endif /* TAMP_COUNTR */ +#endif /* TAMP */ /** * @} diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c index dfa1450a36..f83f50eeea 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai.c @@ -245,6 +245,8 @@ typedef enum */ #define SAI_DEFAULT_TIMEOUT 4U #define SAI_LONG_TIMEOUT 1000U +#define SAI_SPDIF_FRAME_LENGTH 64U +#define SAI_AC97_FRAME_LENGTH 256U /** * @} */ @@ -620,12 +622,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) { /* For SPDIF protocol, frame length is set by hardware to 64 */ - tmpframelength = 64U; + tmpframelength = SAI_SPDIF_FRAME_LENGTH; } else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) { /* For AC97 protocol, frame length is set by hardware to 256 */ - tmpframelength = 256U; + tmpframelength = SAI_AC97_FRAME_LENGTH; } else { @@ -2248,7 +2250,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval HAL state */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) { return hsai->State; } @@ -2259,7 +2261,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) * the configuration information for the specified SAI Block. * @retval SAI Error Code */ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c index 0567c0442f..702e1309de 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sai_ex.c @@ -67,7 +67,8 @@ * @param pdmMicDelay Microphone delays configuration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) { HAL_StatusTypeDef status = HAL_OK; uint32_t offset; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c index fc13c076f3..fea0680856 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sd.c @@ -300,9 +300,9 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); static void SD_PowerOFF(SD_HandleTypeDef *hsd); static void SD_Write_IT(SD_HandleTypeDef *hsd); static void SD_Read_IT(SD_HandleTypeDef *hsd); -static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode); #if (USE_SD_TRANSCEIVER != 0U) -static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode); static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ /** @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; SD_InitTypeDef Init; - uint32_t sdmmc_clk = 0U; + uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; @@ -509,8 +509,15 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ - sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); - HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + if (Init.ClockDiv != 0U) + { + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + } + + if (sdmmc_clk != 0U) + { + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); + } /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); @@ -847,8 +854,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -857,7 +864,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint uint32_t data; uint32_t dataremaining; uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; + const uint8_t *tempbuff = pData; if (NULL == pData) { @@ -1129,7 +1136,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1325,7 +1332,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; @@ -1854,6 +1861,9 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) /** * @brief Register a User SD Callback * To be used instead of the weak (surcharged) predefined callback + * @note The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in + * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID + * and HAL_SD_MSP_DEINIT_CB_ID. * @param hsd : SD handle * @param CallbackID : ID of the callback to be registered * This parameter can be one of the following values: @@ -1882,9 +1892,6 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsd); - if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) @@ -1953,14 +1960,15 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsd); return status; } /** * @brief Unregister a User SD Callback * SD Callback is redirected to the weak (surcharged) predefined callback + * @note The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in + * HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID + * and HAL_SD_MSP_DEINIT_CB_ID. * @param hsd : SD handle * @param CallbackID : ID of the callback to be unregistered * This parameter can be one of the following values: @@ -1980,9 +1988,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsd); - if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) @@ -2051,8 +2056,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsd); return status; } @@ -2400,7 +2403,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { SDMMC_InitTypeDef Init; uint32_t errorstate; - uint32_t sdmmc_clk = 0U; + uint32_t sdmmc_clk; HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2435,7 +2438,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - /* MMC Card does not support this feature */ + /* SD Card does not support this feature */ hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } @@ -2583,9 +2586,9 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t { hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; /* Enable Ultra High Speed */ - if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2595,7 +2598,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2607,13 +2610,33 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_ULTRA: + case SDMMC_SPEED_MODE_ULTRA_SDR104: + { + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable UltraHigh Speed */ + if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_ULTRA_SDR50: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable UltraHigh Speed */ - if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2654,7 +2677,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2668,7 +2691,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t break; } case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; status = HAL_ERROR; @@ -2686,7 +2718,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2705,7 +2737,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2719,7 +2751,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t break; } case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; @@ -2737,7 +2778,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2756,7 +2797,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; @@ -2770,7 +2811,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t break; } case SDMMC_SPEED_MODE_DEFAULT: + { + /* Switch to default Speed */ + if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; @@ -2836,35 +2886,94 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypeDef CardState; + uint32_t error_code; + uint32_t tickstart; - /* DIsable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + if (hsd->State == HAL_SD_STATE_BUSY) + { + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + /*we will send the CMD12 in all cases in order to stop the data transfers*/ + /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/ + /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/ + /*Other scenario will return HAL_ERROR*/ - /* If IDMA Context, disable Internal DMA */ - hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + error_code = hsd->ErrorCode; + if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT)) + { + return HAL_ERROR; + } - hsd->State = HAL_SD_STATE_READY; + tickstart = HAL_GetTick(); + if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD) + { + if (hsd->ErrorCode == HAL_SD_ERROR_NONE) + { + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } - /* Initialize the SD operation */ - hsd->Context = SD_CONTEXT_NONE; + if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT) + { + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + } + else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC) + { + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + } + else + { + /* Nothing to do*/ + } - CardState = HAL_SD_GetCardState(hsd); - if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); - } - if (hsd->ErrorCode != HAL_SD_ERROR_NONE) - { - return HAL_ERROR; + /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear + the appropriate flags that will be set depending of the abort/non abort of the memory */ + /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared + and will result in next SDMMC read/write operation to fail */ + + /*SDMMC ready for clear data flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + /* If IDMA Context, disable Internal DMA */ + hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; + + hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; } return HAL_OK; } + /** * @brief Abort the current transfer and disable the SD (IT mode). * @param hsd: pointer to a SD_HandleTypeDef structure that contains @@ -3571,7 +3680,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) { uint32_t count; uint32_t data; - uint8_t *tmp; + const uint8_t *tmp; tmp = hsd->pTxBuffPtr; @@ -3600,11 +3709,12 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) * @brief Switches the SD card to High Speed mode. * This API must be used after "Transfer State" * @note This operation should be followed by the configuration - * of PLL to have SDMMCCK clock between 50 and 120 MHz + * of PLL to have SDMMCCK clock between 25 and 50 MHz * @param hsd: SD handle + * @param SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN) * @retval SD Card error state */ -uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) +uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode) { uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -3619,7 +3729,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3641,7 +3751,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); + errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; @@ -3715,9 +3825,10 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) * @note This operation should be followed by the configuration * of PLL to have SDMMCCK clock between 50 and 120 MHz * @param hsd: SD handle + * @param UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN) * @retval SD Card error state */ -static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode) { uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; @@ -3756,7 +3867,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); } - errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN); + errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode); if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c index 34c5cfbfff..ee80daceac 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c @@ -131,9 +131,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma); static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma); static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions @@ -1231,6 +1237,9 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) * @} */ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ /** * @brief MDMA SDRAM process complete callback. * @param hmdma : MDMA handle @@ -1297,6 +1306,9 @@ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c index 8d5e999a38..c248622f1d 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smartcard.c @@ -468,6 +468,9 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) /** * @brief Register a User SMARTCARD Callback * To be used instead of the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -497,8 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmartcard); if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) { @@ -584,15 +585,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } /** * @brief Unregister an SMARTCARD callback * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID * @param hsmartcard smartcard handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -613,9 +614,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmartcard); - if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) { switch (CallbackID) @@ -701,9 +699,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmartcard); - return status; } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2276,7 +2271,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ uint32_t temp1; @@ -2293,7 +2288,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar * the configuration information for the specified SMARTCARD module. * @retval SMARTCARD handle Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) { return hsmartcard->ErrorCode; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c index 0504c2aaaf..376d485031 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_smbus.c @@ -584,6 +584,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /** * @brief Register a User SMBUS Callback * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be registered @@ -613,9 +616,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -691,14 +691,15 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } /** * @brief Unregister an SMBUS Callback * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. * @param CallbackID ID of the callback to be unregistered @@ -719,9 +720,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { switch (CallbackID) @@ -797,8 +795,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -822,8 +818,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(hsmbus); if (HAL_SMBUS_STATE_READY == hsmbus->State) { @@ -838,8 +832,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } @@ -854,9 +846,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(hsmbus); - if (HAL_SMBUS_STATE_READY == hsmbus->State) { hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ @@ -870,8 +859,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(hsmbus); return status; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c index 1cbe0679bb..162b08a36e 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c @@ -70,6 +70,7 @@ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (+) ErrorCallback : SPI Error callback (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback (+) MspInitCallback : SPI Msp Init callback (+) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID @@ -89,6 +90,7 @@ (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (+) ErrorCallback : SPI Error callback (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback (+) MspInitCallback : SPI Msp Init callback (+) MspDeInitCallback : SPI Msp DeInit callback @@ -113,6 +115,10 @@ not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. [..] Circular mode restriction: @@ -332,6 +338,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ if (hspi->MspInitCallback == NULL) { @@ -369,6 +376,16 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); } + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + /* SPIx CFG1 Configuration */ WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | hspi->Init.FifoThreshold | hspi->Init.DataSize)); @@ -590,6 +607,10 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call hspi->AbortCpltCallback = pCallback; break; + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + case HAL_SPI_MSPINIT_CB_ID : hspi->MspInitCallback = pCallback; break; @@ -693,6 +714,10 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + case HAL_SPI_MSPINIT_CB_ID : hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ break; @@ -791,7 +816,7 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); @@ -826,7 +851,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -842,6 +867,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -864,7 +893,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXP flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount--; } @@ -897,16 +926,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount -= (uint16_t)2UL; } else { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -940,23 +969,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount -= (uint16_t)4UL; } else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= (uint16_t)2UL; } else { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; } @@ -981,7 +1010,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint } /* Wait for Tx (and CRC) data to be sent */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK) + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } @@ -1021,13 +1050,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -1067,6 +1089,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1182,7 +1208,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait for crc data to be received */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK) + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } @@ -1214,10 +1240,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); @@ -1225,7 +1250,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* __GNUC__ */ uint32_t tickstart; - uint32_t tmp_mode; uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1240,13 +1264,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD initial_TxXferCount = Size; initial_RxXferCount = Size; - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1260,18 +1279,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1279,6 +1293,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxISR = NULL; hspi->TxISR = NULL; + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1298,7 +1315,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount --; initial_TxXferCount = hspi->TxXferCount; @@ -1337,9 +1354,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL)) { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1382,7 +1399,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check the TXP flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL)) { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; initial_TxXferCount = hspi->TxXferCount; @@ -1414,7 +1431,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Wait for Tx/Rx (and CRC) data to be sent/received */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK) + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } @@ -1442,7 +1459,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -1469,7 +1486,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1498,6 +1515,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1533,13 +1554,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -1589,6 +1603,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current @@ -1623,33 +1641,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui * @param Size : amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; - uint32_t max_fifo_length = 0UL; uint32_t tmp_TxXferCount; #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); #endif /* __GNUC__ */ - uint32_t tmp_mode; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Lock the process */ __HAL_LOCK(hspi); - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -1663,15 +1671,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1696,6 +1699,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->TxISR = SPI_TxISR_8BIT; } + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Set the number of data at current transfer */ MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); @@ -1705,75 +1711,33 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Fill in the TxFIFO */ while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) { - if (max_fifo_length < MAX_FIFO_LENGTH) + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* Transmit data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - /* Transmit data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else - { -#if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - /* Transmit data in 8 Bit mode */ - else - { - if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { #if defined (__GNUC__) - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - tmp_TxXferCount = hspi->TxXferCount; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - - max_fifo_length++; + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; } + /* Transmit data in 8 Bit mode */ else { - errorcode = HAL_BUSY; - __HAL_UNLOCK(hspi); - return errorcode; + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; } } @@ -1801,7 +1765,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; HAL_SPI_StateTypeDef tmp_state; @@ -1831,7 +1795,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->Reload.Requested = 1UL; - hspi->Reload.pTxBuffPtr = (uint8_t *)pData; + hspi->Reload.pTxBuffPtr = (const uint8_t *)pData; hspi->Reload.TxXferSize = Size; tmp_state = hspi->State; @@ -1934,7 +1898,8 @@ HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pD * @param Size : amount of data to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, + uint8_t *pRxData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; HAL_SPI_StateTypeDef tmp_state; @@ -1964,7 +1929,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin /* Set the transaction information */ hspi->Reload.Requested = 1UL; - hspi->Reload.pTxBuffPtr = (uint8_t *)pTxData; + hspi->Reload.pTxBuffPtr = (const uint8_t *)pTxData; hspi->Reload.TxXferSize = Size; hspi->Reload.pRxBuffPtr = (uint8_t *)pRxData; hspi->Reload.RxXferSize = Size; @@ -2001,7 +1966,7 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin * @param Size : amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { HAL_StatusTypeDef errorcode = HAL_OK; @@ -2028,7 +1993,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -2044,6 +2009,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { SPI_1LINE_TX(hspi); } + else + { + SPI_2LINES_TX(hspi); + } /* Packing mode management is enabled by the DMA settings */ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ @@ -2156,13 +2125,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); - } - /* Lock the process */ __HAL_LOCK(hspi); @@ -2198,6 +2160,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { SPI_1LINE_RX(hspi); } + else + { + SPI_2LINES_RX(hspi); + } /* Packing mode management is enabled by the DMA settings */ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \ @@ -2304,28 +2270,18 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u * @note When the CRC feature is enabled the pRxData Length must be Size + 1 * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; - uint32_t tmp_mode; - /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); /* Lock the process */ __HAL_LOCK(hspi); - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && \ - (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + if (hspi->State != HAL_SPI_STATE_READY) { errorcode = HAL_BUSY; __HAL_UNLOCK(hspi); @@ -2339,15 +2295,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * return errorcode; } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2358,6 +2309,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->RxISR = NULL; hspi->TxISR = NULL; + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + /* Reset the Tx/Rx DMA bits */ CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); @@ -2409,19 +2363,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Adjustment done */ } - /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ - if (hspi->State == HAL_SPI_STATE_BUSY_RX) - { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - } - else - { - /* Set the SPI Tx/Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; @@ -2451,9 +2395,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; hspi->hdmatx->XferCpltCallback = NULL; - hspi->hdmatx->XferErrorCallback = NULL; hspi->hdmatx->XferAbortCallback = NULL; + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + /* Enable the Tx DMA Stream/Channel */ if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount)) @@ -2530,6 +2476,20 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) /* If master communication on going, make sure current frame is done before closing the connection */ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); do { @@ -2541,6 +2501,19 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* Disable the SPI DMA Tx request if enabled */ @@ -2585,7 +2558,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) SPI_AbortTransfer(hspi); /* Check error during Abort procedure */ - if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) { /* return HAL_Error in case of error during Abort procedure */ errorcode = HAL_ERROR; @@ -2637,6 +2610,20 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) /* If master communication on going, make sure current frame is done before closing the connection */ if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); do { @@ -2648,6 +2635,19 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) } } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } + while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); } /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized @@ -2710,7 +2710,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) SPI_AbortTransfer(hspi); /* Check error during Abort procedure */ - if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) { /* return HAL_Error in case of error during Abort procedure */ errorcode = HAL_ERROR; @@ -2799,6 +2799,20 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); #endif /* __GNUC__ */ + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } /* SPI in mode Transmitter and Receiver ------------------------------------*/ if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ @@ -2934,14 +2948,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) return; } - if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) - { - /* Abort on going, clear SUSP flag to avoid infinite looping */ - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - - return; - } - /* SPI in Error Treatment --------------------------------------------------*/ if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) { @@ -3158,6 +3164,21 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) */ } +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -3183,7 +3204,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3195,7 +3216,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3597,7 +3618,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 8 Bit mode */ - *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint8_t); hspi->TxXferCount--; @@ -3636,9 +3657,9 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) #if defined (__GNUC__) __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); #else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); #endif /* __GNUC__ */ hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3675,7 +3696,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) { /* Transmit data in 32 Bit mode */ - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint32_t); hspi->TxXferCount--; @@ -3825,7 +3846,7 @@ static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) + uint32_t Timeout, uint32_t Tickstart) { /* Wait until flag is set */ while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c index 963b85b7b9..7cf5fb343f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c @@ -72,7 +72,7 @@ * the configuration information for the specified SPI module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) { uint8_t count = 0; uint32_t itflag = hspi->Instance->SR; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c index 8e1bbddcb2..d7732109ce 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c @@ -132,9 +132,15 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma); static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma); static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma); +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ @@ -1033,6 +1039,10 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ +/** @addtogroup SRAM_Private_Functions SRAM Private Functions + * @{ + */ + /** * @brief MDMA SRAM process complete callback. * @param hmdma : MDMA handle @@ -1099,6 +1109,10 @@ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } +/** + * @} + */ + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c index a1edfa78c2..eab578f872 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c @@ -205,11 +205,11 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -225,7 +225,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -278,6 +278,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -525,7 +526,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -539,7 +540,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if (htim->State == HAL_TIM_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -661,6 +662,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1050,7 +1052,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1065,7 +1068,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1328,6 +1331,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -1717,7 +1721,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1732,7 +1737,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1994,6 +1999,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -2387,7 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -2643,6 +2649,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) @@ -3046,6 +3053,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) { @@ -3555,7 +3563,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData1 == NULL) && (Length > 0U)) + if ((pData1 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3580,7 +3588,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData2 == NULL) && (Length > 0U)) + if ((pData2 == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -3609,7 +3617,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) { return HAL_ERROR; } @@ -4054,7 +4062,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4152,7 +4160,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4254,7 +4262,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -4557,7 +4565,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) { HAL_StatusTypeDef status; @@ -4616,7 +4624,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { HAL_StatusTypeDef status = HAL_OK; @@ -5273,7 +5281,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -5430,7 +5438,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -5621,7 +5629,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5662,7 +5670,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5704,7 +5712,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -5979,8 +5987,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call { return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(htim); if (htim->State == HAL_TIM_STATE_READY) { @@ -6176,9 +6182,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } @@ -6222,9 +6225,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(htim); - if (htim->State == HAL_TIM_STATE_READY) { switch (CallbackID) @@ -6461,9 +6461,6 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(htim); - return status; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -6492,7 +6489,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6502,7 +6499,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6512,7 +6509,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6522,7 +6519,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6532,7 +6529,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6542,7 +6539,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6552,7 +6549,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6570,7 +6567,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6587,7 +6584,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -6930,7 +6927,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -6978,7 +6975,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7053,7 +7050,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7129,7 +7126,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7203,7 +7200,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7264,7 +7261,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7317,7 +7314,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - TIM_OC_InitTypeDef *OC_Config) + const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -7371,7 +7368,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c index a1aeeb4520..ad4cbeec78 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c @@ -149,7 +149,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -165,6 +165,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -515,7 +516,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -880,7 +881,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -895,7 +897,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1361,7 +1363,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; @@ -1376,7 +1379,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if ((pData == NULL) && (Length > 0U)) + if ((pData == NULL) || (Length == 0U)) { return HAL_ERROR; } @@ -1988,7 +1991,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -2061,7 +2064,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2149,7 +2152,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) { HAL_StatusTypeDef status = HAL_OK; @@ -2731,7 +2734,7 @@ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -2746,7 +2749,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c index d657af88e5..016d5684da 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c @@ -656,6 +656,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -696,6 +697,9 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) /** * @brief Register a User UART Callback * To be used instead of the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -727,8 +731,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ return HAL_ERROR; } - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_READY) { switch (CallbackID) @@ -818,14 +820,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } /** * @brief Unregister an UART Callback * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID * @param huart uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -848,8 +851,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - __HAL_LOCK(huart); - if (HAL_UART_STATE_READY == huart->gState) { switch (CallbackID) @@ -941,8 +942,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR status = HAL_ERROR; } - __HAL_UNLOCK(huart); - return status; } @@ -1132,8 +1131,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1155,12 +1152,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD pdata16bits = NULL; } - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { + + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1178,6 +1176,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { + huart->gState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } @@ -1222,8 +1222,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1250,13 +1248,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* as long as data have to be received */ while (huart->RxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { + huart->RxState = HAL_UART_STATE_READY; + return HAL_TIMEOUT; } if (pdata8bits == NULL) @@ -1303,8 +1301,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1326,8 +1322,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the TX FIFO threshold interrupt */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); } @@ -1343,8 +1337,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t huart->TxISR = UART_TxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the Transmit Data Register Empty interrupt */ ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); } @@ -1377,8 +1369,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1420,8 +1410,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1449,8 +1437,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->gState to ready */ huart->gState = HAL_UART_STATE_READY; @@ -1460,8 +1446,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -1496,8 +1480,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1529,8 +1511,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - __HAL_LOCK(huart); - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { @@ -1548,8 +1528,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1560,8 +1538,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - __HAL_LOCK(huart); - if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ @@ -1583,8 +1559,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -2441,6 +2415,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); @@ -2474,6 +2453,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxISR = NULL; ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); @@ -2958,7 +2942,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1; uint32_t temp2; @@ -2974,7 +2958,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -3374,6 +3358,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3385,6 +3376,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + /* Timeout occurred */ return HAL_TIMEOUT; } @@ -3394,6 +3394,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; __HAL_UNLOCK(huart); @@ -3421,35 +3422,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); return HAL_TIMEOUT; } if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; /* Process Unlocked */ @@ -3503,8 +3508,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) { @@ -3524,8 +3527,6 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->RxISR = UART_RxISR_8BIT; } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) { @@ -3578,15 +3579,12 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - __HAL_UNLOCK(huart); - /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; return HAL_ERROR; } } - __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) @@ -3731,6 +3729,10 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -3765,6 +3767,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4225,6 +4231,19 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4240,6 +4259,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4304,6 +4324,19 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4319,6 +4352,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4434,6 +4468,19 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4449,6 +4496,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -4584,6 +4632,19 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) @@ -4599,6 +4660,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear IDLE Flag */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c index e2ca48d584..2bba9dc2f7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c @@ -724,11 +724,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -752,8 +751,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -770,6 +767,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -845,10 +843,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_IT(huart, pData, Size); @@ -907,10 +904,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -940,6 +936,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } } +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + /** * @} */ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c index 4dbf0483cd..bed9d165bb 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_usart.c @@ -407,6 +407,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) /** * @brief Register a User USART Callback * To be used instead of the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -436,8 +438,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(husart); if (husart->State == HAL_USART_STATE_READY) { @@ -526,15 +526,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } /** * @brief Unregister an USART Callback * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -555,9 +554,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(husart); - if (HAL_USART_STATE_READY == husart->State) { switch (CallbackID) @@ -645,9 +641,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(husart); - return status; } #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -2486,7 +2479,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2497,7 +2490,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART handle Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } @@ -2957,7 +2950,8 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) case USART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), + husart->Init.BaudRate, husart->Init.ClockPrescaler)); } else { diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c index 6c96f9d85b..ce0edd7750 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_adc.c @@ -207,6 +207,7 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC group injected */ +#if defined(STM32H745xx) || defined(STM32H745xG) || defined(STM32H742xx) || defined(STM32H743xx) || defined(STM32H747xG) || defined(STM32H747xx) || defined(STM32H750xx) || defined(STM32H753xx) || defined(STM32H755xx) || defined(STM32H757xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ @@ -231,6 +232,30 @@ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \ ) +#else +#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \ + ) +#endif #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c index 3854c63514..ceb3247647 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_cordic.c @@ -58,7 +58,7 @@ * - SUCCESS: CORDIC registers are de-initialized * - ERROR: CORDIC registers are not de-initialized */ -ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx) +ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c index 792a3c0d34..0ad6a461b2 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_delayblock.c @@ -63,7 +63,13 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup DelayBlock_LL_Private_Defines Delay Block Low Layer Private Defines + * @{ + */ #define DLYB_TIMEOUT 0xFFU +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c index a2a870da34..7c119806f7 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lptim.c @@ -163,7 +163,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ @@ -313,8 +313,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_ARROK(LPTIMx); } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c index 335dc181ea..739cb1a632 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_lpuart.c @@ -44,6 +44,9 @@ * @{ */ +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + /** * @} */ @@ -126,7 +129,7 @@ * - SUCCESS: LPUART registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) { ErrorStatus status = SUCCESS; @@ -164,7 +167,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content * - ERROR: Problem occurred during LPUART Registers initialization */ -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk; @@ -253,7 +256,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) { /* Set LPUART_InitStruct fields to default values */ LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; - LPUART_InitStruct->BaudRate = 9600U; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c index 9643dcd32d..e7b85d92d6 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rcc.c @@ -20,9 +20,9 @@ #include "stm32h7xx_ll_rcc.h" #include "stm32h7xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32H7xx_LL_Driver @@ -37,7 +37,14 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Variables + * @{ + */ const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCC_LL_Private_Macros @@ -117,8 +124,8 @@ static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency); */ void LL_RCC_DeInit(void) { - /* Increasing the CPU frequency */ - if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + /* Increasing the CPU frequency */ + if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); @@ -128,26 +135,26 @@ void LL_RCC_DeInit(void) SET_BIT(RCC->CR, RCC_CR_HSION); /* Wait for HSI READY bit */ - while(LL_RCC_HSI_IsReady() == 0U) + while (LL_RCC_HSI_IsReady() == 0U) {} /* Reset CFGR register */ CLEAR_REG(RCC->CFGR); /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \ - |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON \ + | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); /* Wait for PLL1 READY bit to be reset */ - while(LL_RCC_PLL1_IsReady() != 0U) + while (LL_RCC_PLL1_IsReady() != 0U) {} /* Wait for PLL2 READY bit to be reset */ - while(LL_RCC_PLL2_IsReady() != 0U) + while (LL_RCC_PLL2_IsReady() != 0U) {} /* Wait for PLL3 READY bit to be reset */ - while(LL_RCC_PLL3_IsReady() != 0U) + while (LL_RCC_PLL3_IsReady() != 0U) {} #if defined(RCC_D1CFGR_HPRE) @@ -172,7 +179,7 @@ void LL_RCC_DeInit(void) #endif /* RCC_D1CFGR_HPRE */ /* Reset PLLCKSELR register to default value */ - RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5; + RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5; /* Reset PLLCFGR register to default value */ LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U); @@ -203,14 +210,14 @@ void LL_RCC_DeInit(void) /* Clear all interrupts */ SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC - | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC - | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC); + | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC + | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC); /* Clear reset source flags */ SET_BIT(RCC->RSR, RCC_RSR_RMVF); - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); @@ -296,7 +303,7 @@ void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) case LL_RCC_PLLSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -370,7 +377,7 @@ void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) case LL_RCC_PLLSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -444,7 +451,7 @@ void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks) case LL_RCC_PLLSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -514,9 +521,9 @@ uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, { float_t freq; - freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000)); + freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000)); - freq = freq/(float_t)PQR; + freq = freq / (float_t)PQR; return (uint32_t)freq; } @@ -540,11 +547,11 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) switch (LL_RCC_GetUSARTClockSource(USARTxSource)) { case LL_RCC_USART16_CLKSOURCE_PCLK2: - usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_USART234578_CLKSOURCE_PCLK1: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_USART16_CLKSOURCE_PLL2Q: @@ -569,7 +576,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) case LL_RCC_USART234578_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -612,7 +619,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) { case LL_RCC_LPUART1_CLKSOURCE_PCLK4: - lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_LPUART1_CLKSOURCE_PLL2Q: @@ -634,7 +641,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) case LL_RCC_LPUART1_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -679,11 +686,11 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) switch (LL_RCC_GetI2CClockSource(I2CxSource)) { case LL_RCC_I2C123_CLKSOURCE_PCLK1: - i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_I2C4_CLKSOURCE_PCLK4: - i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_I2C123_CLKSOURCE_PLL3R: @@ -699,7 +706,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) case LL_RCC_I2C4_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -739,12 +746,12 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) { case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: - lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_LPTIM2_CLKSOURCE_PCLK4: case LL_RCC_LPTIM345_CLKSOURCE_PCLK4: - lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_LPTIM1_CLKSOURCE_PLL2P: @@ -1155,7 +1162,7 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) break; case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: - dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; default: @@ -1187,7 +1194,7 @@ uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource) break; case LL_RCC_DFSDM2_CLKSOURCE_PCLK4: - dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; default: @@ -1277,7 +1284,7 @@ uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource) case LL_RCC_SPDIF_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -1344,11 +1351,11 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) break; case LL_RCC_SPI45_CLKSOURCE_PCLK2: - spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_SPI6_CLKSOURCE_PCLK4: - spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_SPI45_CLKSOURCE_PLL2Q: @@ -1373,7 +1380,7 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) case LL_RCC_SPI6_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -1415,13 +1422,13 @@ uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource) switch (LL_RCC_GetSWPClockSource(SWPxSource)) { case LL_RCC_SWP_CLKSOURCE_PCLK1: - swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()))); + swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()))); break; case LL_RCC_SWP_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -1493,7 +1500,7 @@ uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource) switch (LL_RCC_GetFMCClockSource(FMCxSource)) { case LL_RCC_FMC_CLKSOURCE_HCLK: - fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())); + fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); break; case LL_RCC_FMC_CLKSOURCE_PLL1Q: @@ -1540,7 +1547,7 @@ uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource) switch (LL_RCC_GetQSPIClockSource(QSPIxSource)) { case LL_RCC_QSPI_CLKSOURCE_HCLK: - qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())); + qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); break; case LL_RCC_QSPI_CLKSOURCE_PLL1Q: @@ -1589,7 +1596,7 @@ uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource) switch (LL_RCC_GetOSPIClockSource(OSPIxSource)) { case LL_RCC_OSPI_CLKSOURCE_HCLK: - ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())); + ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())); break; case LL_RCC_OSPI_CLKSOURCE_PLL1Q: @@ -1637,7 +1644,7 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource) case LL_RCC_CLKP_CLKSOURCE_HSI: if (LL_RCC_HSI_IsReady() != 0U) { - clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); } break; @@ -1689,7 +1696,7 @@ static uint32_t RCC_GetSystemClockFreq(void) { /* No check on Ready: Won't be selected by hardware if not */ case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: - frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos); + frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos); break; case LL_RCC_SYS_CLKSOURCE_STATUS_CSI: diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c index 515fe424dd..0e516e75d1 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_rtc.c @@ -163,24 +163,19 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); -#if defined(RTC_ICSR_ALRAWF) +#if defined(TAMP) /* Reset ICSR register and exit initialization mode */ - LL_RTC_WriteReg(RTCx, ICSR, 0x00000000U); -#endif /* RTC_ICSR_ALRAWF */ -#if defined(RTC_ISR_ALRAWF) + LL_RTC_WriteReg(RTCx, ICSR, 0x00000000U); +#else /* Reset ISR register and exit initialization mode */ - LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); -#endif /* RTC_ISR_ALRAWF */ + LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); -#if defined(RTC_TAMPCR_TAMP1E) /* Reset Tamper and alternate functions configuration register */ LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U); -#endif /* RTC_TAMPCR_TAMP1E */ -#if defined(RTC_OR_ALARMOUTTYPE) /* Reset Option register */ - LL_RTC_WriteReg(RTCx, OR, 0x00000000U); -#endif /* RTC_OR_ALARMOUTTYPE */ + LL_RTC_WriteReg(RTCx, OR, 0x00000000U); +#endif /* TAMP */ /* Wait till the RTC RSF flag is set */ status = LL_RTC_WaitForSynchro(RTCx); @@ -189,14 +184,14 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) /* Enable the write protection for RTC registers */ LL_RTC_EnableWriteProtection(RTCx); -#if defined (TAMP_CR1_TAMP1E) +#if defined(TAMP) /* DeInitialization of the TAMP */ LL_RTC_WriteReg(TAMP, CR1, 0xFFFF0000U); LL_RTC_WriteReg(TAMP, FLTCR, 0x00000000U); LL_RTC_WriteReg(TAMP, ATCR1, 0x00000000U); LL_RTC_WriteReg(TAMP, IER, 0x00000000U); LL_RTC_WriteReg(TAMP, SCR, 0xFFFFFFFFU); -#endif /* TAMP_CR1_TAMP1E */ +#endif /* TAMP */ return status; } diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c index 9076a3838f..d78aaf0333 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_spi.c @@ -21,9 +21,6 @@ #include "stm32h7xx_ll_spi.h" #include "stm32h7xx_ll_bus.h" #include "stm32h7xx_ll_rcc.h" -#ifdef GENERATOR_I2S_PRESENT -#include "stm32h7xx_ll_rcc.h" -#endif /* GENERATOR_I2S_PRESENT*/ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else @@ -575,7 +572,7 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) uint32_t packetlength = 1UL; uint32_t ispcm = 0UL; uint32_t tmp; - uint32_t sourceclock = 0UL; + uint32_t sourceclock; ErrorStatus status = ERROR; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c index 0d7e018249..2af393648f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_tim.c @@ -193,16 +193,16 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -359,7 +359,7 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -440,7 +440,7 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -501,7 +501,7 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -555,7 +555,7 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -648,7 +648,7 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -766,7 +766,7 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -792,19 +792,13 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); #if defined(TIM_BDTR_BKBID) - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); - } + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); #else - if (IS_TIM_ADVANCED_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - } + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); #endif /*TIM_BDTR_BKBID */ if (IS_TIM_BKIN2_INSTANCE(TIMx)) @@ -850,7 +844,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -929,7 +923,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -1008,7 +1002,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1087,7 +1081,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1157,7 +1151,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1218,7 +1212,7 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr3; uint32_t tmpccer; @@ -1278,7 +1272,7 @@ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1311,7 +1305,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1344,7 +1338,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1377,7 +1371,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c index da9dfa8e46..d4b8d2880f 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usart.c @@ -31,7 +31,8 @@ * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10) +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10) /** @addtogroup USART_LL * @{ @@ -40,6 +41,17 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ @@ -125,7 +137,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -238,7 +250,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -378,7 +390,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) { /* Set USART_InitStruct fields to default values */ USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; - USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; USART_InitStruct->StopBits = LL_USART_STOPBITS_1; USART_InitStruct->Parity = LL_USART_PARITY_NONE ; @@ -401,7 +413,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c index e32c56ea43..85d0136023 100644 --- a/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c +++ b/system/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c @@ -27,7 +27,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. (#) Call USB_CoreInit() API to initialize the USB Core peripheral. @@ -768,8 +768,21 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); @@ -839,18 +852,34 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - if (ep->xfer_len == 0U) + if (epnum == 0U) { - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); } else { - pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - ep->xfer_size = ep->maxpacket * pktcnt; + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } } if (dma == 1U) @@ -879,106 +908,6 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef return HAL_OK; } -/** - * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - } - - if (dma == 1U) - { - if ((uint32_t)ep->dma_addr != 0U) - { - USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else - { - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0U) - { - USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); - } - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (ep->xfer_len > 0U) - { - ep->xfer_len = ep->maxpacket; - } - - /* Store transfer size, for EP0 this is equal to endpoint max packet size */ - ep->xfer_size = ep->maxpacket; - - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - - if (dma == 1U) - { - if ((uint32_t)ep->xfer_buff != 0U) - { - USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - } - - /* EP enable */ - USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - - return HAL_OK; -} - /** * @brief USB_EPStoptXfer Stop transfer on an EP @@ -1224,7 +1153,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) * This parameter can be a value from 0 to 255 * @retval HAL status */ -HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) +HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1239,7 +1168,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1256,7 +1185,7 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1271,9 +1200,9 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadInterrupts: return the global USB interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Global Interrupt status */ -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) { uint32_t tmpreg; @@ -1283,10 +1212,27 @@ uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx) return tmpreg; } +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + /** * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device OUT EP interrupt status */ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { @@ -1302,7 +1248,7 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx) /** * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status * @param USBx Selected device - * @retval HAL status + * @retval USB Device IN EP interrupt status */ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx) { @@ -1384,7 +1330,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) * @param USBx Selected device * @retval HAL status */ -HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) +HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1528,7 +1474,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) { - USBx_HC(i)->HCINT = 0xFFFFFFFFU; + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; USBx_HC(i)->HCINTMSK = 0U; } @@ -1536,7 +1482,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx->GINTMSK = 0U; /* Clear any pending interrupts */ - USBx->GINTSTS = 0xFFFFFFFFU; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; if ((USBx->CID & (0x1U << 8)) != 0U) { @@ -1586,15 +1532,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) if (freq == HCFG_48_MHZ) { - USBx_HOST->HFIR = 48000U; + USBx_HOST->HFIR = HFIR_48_MHZ; } else if (freq == HCFG_6_MHZ) { - USBx_HOST->HFIR = 6000U; + USBx_HOST->HFIR = HFIR_6_MHZ; } else { - /* ... */ + return HAL_ERROR; } return HAL_OK; @@ -1720,7 +1666,7 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ - USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; /* Enable channel interrupts required for this transfer. */ switch (ep_type) @@ -1815,7 +1761,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | - ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { @@ -1843,7 +1790,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe uint8_t is_oddframe; uint16_t len_words; uint16_t num_packets; - uint16_t max_hc_pkt_count = 256U; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) { @@ -2139,8 +2086,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) } /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = 0xFFFFFFFFU; - USBx->GINTSTS = 0xFFFFFFFFU; + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; (void)USB_EnableGlobalInt(USBx); @@ -2181,7 +2128,6 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) } #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /** * @} */ diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index e4bd7f6ed8..23b5c8e70f 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.3.0 * STM32G0: 1.4.4 * STM32G4: 1.2.2 - * STM32H7: 1.11.0 + * STM32H7: 1.11.1 * STM32L0: 1.10.5 * STM32L1: 1.4.4 * STM32L4: 1.13.3 From ff5c948c65321611b816cc9eb5698cb124bc9c57 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 8 Dec 2022 11:45:40 +0100 Subject: [PATCH 2/2] system(H7): update STM32H7xx CMSIS Drivers to v1.10.3 Included in STM32CubeH7 FW v1.11.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32H7xx/Include/stm32h723xx.h | 518 ++++++++-------- .../Device/ST/STM32H7xx/Include/stm32h725xx.h | 518 ++++++++-------- .../Device/ST/STM32H7xx/Include/stm32h730xx.h | 522 ++++++++-------- .../ST/STM32H7xx/Include/stm32h730xxq.h | 522 ++++++++-------- .../Device/ST/STM32H7xx/Include/stm32h733xx.h | 522 ++++++++-------- .../Device/ST/STM32H7xx/Include/stm32h735xx.h | 522 ++++++++-------- .../Device/ST/STM32H7xx/Include/stm32h742xx.h | 555 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h743xx.h | 555 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h745xg.h | 555 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h745xx.h | 555 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h747xg.h | 579 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h747xx.h | 579 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h750xx.h | 559 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h753xx.h | 559 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h755xx.h | 559 ++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h757xx.h | 583 +++++++++--------- .../Device/ST/STM32H7xx/Include/stm32h7a3xx.h | 382 ++++++------ .../ST/STM32H7xx/Include/stm32h7a3xxq.h | 382 ++++++------ .../Device/ST/STM32H7xx/Include/stm32h7b0xx.h | 386 ++++++------ .../ST/STM32H7xx/Include/stm32h7b0xxq.h | 386 ++++++------ .../Device/ST/STM32H7xx/Include/stm32h7b3xx.h | 386 ++++++------ .../ST/STM32H7xx/Include/stm32h7b3xxq.h | 386 ++++++------ .../Device/ST/STM32H7xx/Include/stm32h7xx.h | 4 +- .../CMSIS/Device/ST/STM32H7xx/License.md | 228 ++++++- .../CMSIS/Device/ST/STM32H7xx/README.md | 11 +- .../Device/ST/STM32H7xx/Release_Notes.html | 41 +- .../Source/Templates/system_stm32h7xx.c | 16 +- .../system_stm32h7xx_dualcore_boot_cm4_cm7.c | 16 +- ...stem_stm32h7xx_dualcore_bootcm4_cm7gated.c | 16 +- ...stem_stm32h7xx_dualcore_bootcm7_cm4gated.c | 16 +- .../Templates/system_stm32h7xx_singlecore.c | 8 +- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 32 files changed, 5807 insertions(+), 5621 deletions(-) diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h index 65529a4d38..dfe7f0f6b6 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h @@ -4131,7 +4131,7 @@ typedef struct #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */ #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*! - + @@ -30,11 +30,22 @@

                Release Notes for  STM32H7xx C

                Update History

                - +

                Main Changes

                • General updates to fix known defects and implementation enhancements
                  • +
                • Update system_stm32h7xx_*.c template files to fix typo in comment: the VTOR offset value is multiple of 0x400.
                  • +
                • Adjust QUADSPI FIFO level threshold bits mask definition on 5 bits instead of 4bits.
                  • +
                +
                +
                +
                + +
                +

                Main Changes

                +
                  +
                • General updates to fix known defects and implementation enhancements
                • Add support for ADC LDO output voltage ready bit.
                • Remove useless OCTOSPI_DCR1_CKCSHT definition: alignment with the reference manual
                • All system_stm32h7xx.c template files @@ -47,7 +58,7 @@

                  Main Changes

                  -

                  Main Changes

                  +

                  Main Changes

                  • General updates to fix known defects and implementation enhancements
                  • All source files: update disclaimer to add reference to the new license agreement.
                    • @@ -73,7 +84,7 @@

                    Main Changes

                    -

                    Main Changes

                    +

                    Main Changes

                    • Fix minor issues related to English typo in comments of registers and fields description
                    • Update STM32H7 devices header files to add GPV registers definition, base address and instance
                      • @@ -91,7 +102,7 @@

                      Main Changes

                      -

                      Main Changes

                      +

                      Main Changes

                      • Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
                          @@ -149,7 +160,7 @@

                          Main Changes

                          -

                          Main Changes

                          +

                          Main Changes

                          • General updates to align Bits and registers definitions with the STM32H7 reference manual
                          • Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero
                            • @@ -170,7 +181,7 @@

                            Main Changes

                            -

                            Main Changes

                            +

                            Main Changes

                            • General updates to align Bit and registers definition with the STM32H7 reference manual

                            • Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices: @@ -200,7 +211,7 @@

                              Main Changes

                              -

                              Main Changes

                              +

                              Main Changes

                              • Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices
                              • Add definition of “ART” instance: pointer to “ART_TypeDef” structure
                                • @@ -215,7 +226,7 @@

                                Main Changes

                                -

                                Main Changes

                                +

                                Main Changes

                                • General updates to align Bit and registers definition with the STM32H7 reference manual
                                • Updates to aligned with STM32H7xx rev.V devices
                                  • @@ -279,7 +290,7 @@

                                  Main Changes

                                  -

                                  Main Changes

                                  +

                                  Main Changes

                                  • Patch Release on top of V1.3.0
                                  • Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files: @@ -292,7 +303,7 @@

                                    Main Changes

                                    -

                                    Main Changes

                                    +

                                    Main Changes

                                    • STM32H7xx include files:
                                        @@ -337,7 +348,7 @@

                                        Main Changes

                                        -

                                        Main Changes

                                        +

                                        Main Changes

                                        • Add support for stm32h750xx value line devices:
                                            @@ -350,7 +361,7 @@

                                            Main Changes

                                            -

                                            Main Changes

                                            +

                                            Main Changes

                                            • Update FDCAN bit definition
                                            • Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access
                                              • @@ -360,7 +371,7 @@

                                              Main Changes

                                              -

                                              Main Changes

                                              +

                                              Main Changes

                                              • Update USB OTG bit definition
                                              • Adjust PLL fractional computation
                                                • @@ -370,7 +381,7 @@

                                                Main Changes

                                                -

                                                Main Changes

                                                +

                                                Main Changes

                                                • First official release for STM32H743xx/753xx devices
                                                diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c index c99a7b1dbf..86e678475c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c @@ -94,14 +94,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else /*!< Uncomment the following line if you need to relocate your vector Table @@ -109,14 +109,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #endif /* DUAL_CORE && CORE_CM4 */ #endif /* USER_VECT_TAB_ADDRESS */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 4af82c9e68..2d0b59ead1 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -94,14 +94,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table @@ -109,14 +109,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7 diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c index bf6bfcd310..dc86d254a9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm4_cm7gated.c @@ -97,14 +97,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table @@ -112,14 +112,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7 diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c index c6c1c8e45f..f3f3406415 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_dualcore_bootcm7_cm4gated.c @@ -97,14 +97,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D2_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK2_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #elif defined(CORE_CM7) /*!< Uncomment the following line if you need to relocate your vector Table @@ -112,14 +112,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x300. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #else #error Please #define CORE_CM4 or CORE_CM7 diff --git a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c index de86fc3765..6ab8cc2de9 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c +++ b/system/Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx_singlecore.c @@ -95,14 +95,14 @@ /* #define VECT_TAB_SRAM */ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS D1_AXISRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BANK1_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ + This value must be a multiple of 0x400. */ #endif /* VECT_TAB_SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index cbd1defe26..35e362fa57 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -8,7 +8,7 @@ * STM32F7: 1.2.8 * STM32G0: 1.4.3 * STM32G4: 1.2.2 - * STM32H7: 1.10.2 + * STM32H7: 1.10.3 * STM32L0: 1.9.2 * STM32L1: 2.3.2 * STM32L4: 1.7.2