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Commit f599fd6

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ridhaosWi6labsVVESTM
ridhaosWi6labs
authored and
VVESTM
committed
Update Stm8s for Cosmic compatibility.
Make some modification to make SPL compatible with C++.
1 parent 480f0a9 commit f599fd6

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2 files changed

+51
-36
lines changed

2 files changed

+51
-36
lines changed

‎system/Drivers/STM8S_StdPeriph_Driver/inc/stm8s.h

Lines changed: 23 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -207,10 +207,13 @@
207207
#define __O volatile /*!< defines 'write only' permissions */
208208
#define __IO volatile /*!< defines 'read / write' permissions */
209209

210-
/*!< Signed integer types */
211-
typedef signed char int8_t;
212-
typedef signed short int16_t;
213-
typedef signed long int32_t;
210+
#if defined(__ICCSTM8__) || defined(__CSMC__)
211+
#include <stdint.h>
212+
#else
213+
/*!< Signed integer types */
214+
typedef signed char int8_t;
215+
typedef signed short int16_t;
216+
typedef signed long int32_t;
214217

215218
/*!< Unsigned integer types */
216219
typedef unsigned char uint8_t;
@@ -228,7 +231,10 @@ typedef uint16_t u16;
228231
typedef uint8_t u8;
229232

230233

231-
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
234+
#ifndef __cplusplus
235+
typedef enum {FALSE = 0, TRUE = !FALSE} bool;
236+
#endif
237+
#endif
232238

233239
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction;
234240

@@ -2745,8 +2751,13 @@ CFG_TypeDef;
27452751
/*============================== Interrupt vector Handling ========================*/
27462752

27472753
#ifdef _COSMIC_
2748-
#define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void)
2749-
#define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void)
2754+
#ifdef __cplusplus
2755+
#define INTERRUPT_HANDLER(a,b) void a(void)
2756+
#define INTERRUPT_HANDLER_TRAP(a) void a(void)
2757+
#else
2758+
#define INTERRUPT_HANDLER(a,b) @interrupt @svlreg void a(void)
2759+
#define INTERRUPT_HANDLER_TRAP(a) @interrupt void a(void)
2760+
#endif
27502761
#endif /* _COSMIC_ */
27512762

27522763
#ifdef _RAISONANCE_
@@ -2767,7 +2778,11 @@ CFG_TypeDef;
27672778

27682779
/*============================== Interrupt Handler declaration ========================*/
27692780
#ifdef _COSMIC_
2770-
#define INTERRUPT @far @interrupt
2781+
#ifdef __cplusplus
2782+
#define INTERRUPT
2783+
#else
2784+
#define INTERRUPT @interrupt
2785+
#endif
27712786
#elif defined(_IAR_)
27722787
#define INTERRUPT __interrupt
27732788
#endif /* _COSMIC_ */

‎system/Drivers/STM8S_StdPeriph_Driver/src/stm8s_itc.c

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@
1616
*
1717
* http://www.st.com/software_license_agreement_liberty_v2
1818
*
19-
* Unless required by applicable law or agreed to in writing, software
20-
* distributed under the License is distributed on an "AS IS" BASIS,
19+
* Unless required by applicable law or agreed to in writing, software
20+
* distributed under the License is distributed on an "AS IS" BASIS,
2121
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
2222
* See the License for the specific language governing permissions and
2323
* limitations under the License.
@@ -52,7 +52,7 @@ uint8_t ITC_GetCPUCC(void)
5252
#ifdef _COSMIC_
5353
_asm("push cc");
5454
_asm("pop a");
55-
return; /* Ignore compiler warning, the returned value is in A register */
55+
// return; /* Ignore compiler warning, the returned value is in A register */
5656
#elif defined _RAISONANCE_ /* _RAISONANCE_ */
5757
return _getCC_();
5858
#else /* _IAR_ */
@@ -108,13 +108,13 @@ ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
108108
{
109109
uint8_t Value = 0;
110110
uint8_t Mask = 0;
111-
111+
112112
/* Check function parameters */
113113
assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
114-
114+
115115
/* Define the mask corresponding to the bits position in the SPR register */
116116
Mask = (uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U));
117-
117+
118118
switch (IrqNum)
119119
{
120120
case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */
@@ -160,7 +160,7 @@ ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
160160
defined(STM8S003) ||defined(STM8S001) || defined (STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
161161
case ITC_IRQ_UART1_TX:
162162
case ITC_IRQ_UART1_RX:
163-
#endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
163+
#endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
164164
#if defined(STM8AF622x)
165165
case ITC_IRQ_UART4_TX:
166166
case ITC_IRQ_UART4_RX:
@@ -198,9 +198,9 @@ ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum)
198198
default:
199199
break;
200200
}
201-
201+
202202
Value >>= (uint8_t)(((uint8_t)IrqNum % 4u) * 2u);
203-
203+
204204
return((ITC_PriorityLevel_TypeDef)Value);
205205
}
206206

@@ -221,21 +221,21 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
221221
{
222222
uint8_t Mask = 0;
223223
uint8_t NewPriority = 0;
224-
224+
225225
/* Check function parameters */
226226
assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum));
227227
assert_param(IS_ITC_PRIORITY_OK(PriorityValue));
228-
228+
229229
/* Check if interrupts are disabled */
230230
assert_param(IS_ITC_INTERRUPTS_DISABLED);
231-
231+
232232
/* Define the mask corresponding to the bits position in the SPR register */
233233
/* The mask is reversed in order to clear the 2 bits after more easily */
234234
Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U)));
235-
235+
236236
/* Define the new priority to write */
237237
NewPriority = (uint8_t)((uint8_t)(PriorityValue) << (((uint8_t)IrqNum % 4U) * 2U));
238-
238+
239239
switch (IrqNum)
240240
{
241241
case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */
@@ -245,15 +245,15 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
245245
ITC->ISPR1 &= Mask;
246246
ITC->ISPR1 |= NewPriority;
247247
break;
248-
248+
249249
case ITC_IRQ_PORTB:
250250
case ITC_IRQ_PORTC:
251251
case ITC_IRQ_PORTD:
252252
case ITC_IRQ_PORTE:
253253
ITC->ISPR2 &= Mask;
254254
ITC->ISPR2 |= NewPriority;
255255
break;
256-
256+
257257
#if defined(STM8S208) || defined(STM8AF52Ax)
258258
case ITC_IRQ_CAN_RX:
259259
case ITC_IRQ_CAN_TX:
@@ -266,9 +266,9 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
266266
ITC->ISPR3 &= Mask;
267267
ITC->ISPR3 |= NewPriority;
268268
break;
269-
269+
270270
case ITC_IRQ_TIM1_CAPCOM:
271-
#if defined(STM8S903) || defined(STM8AF622x)
271+
#if defined(STM8S903) || defined(STM8AF622x)
272272
case ITC_IRQ_TIM5_OVFTRI:
273273
case ITC_IRQ_TIM5_CAPCOM:
274274
#else
@@ -279,13 +279,13 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
279279
ITC->ISPR4 &= Mask;
280280
ITC->ISPR4 |= NewPriority;
281281
break;
282-
282+
283283
case ITC_IRQ_TIM3_CAPCOM:
284284
#if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \
285285
defined(STM8S001) ||defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
286286
case ITC_IRQ_UART1_TX:
287287
case ITC_IRQ_UART1_RX:
288-
#endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
288+
#endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF52Ax or STM8AF62Ax */
289289
#if defined(STM8AF622x)
290290
case ITC_IRQ_UART4_TX:
291291
case ITC_IRQ_UART4_RX:
@@ -294,24 +294,24 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
294294
ITC->ISPR5 &= Mask;
295295
ITC->ISPR5 |= NewPriority;
296296
break;
297-
297+
298298
#if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x)
299299
case ITC_IRQ_UART2_TX:
300300
case ITC_IRQ_UART2_RX:
301301
#endif /*STM8S105 or STM8AF626x */
302-
302+
303303
#if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \
304304
defined(STM8AF62Ax)
305305
case ITC_IRQ_UART3_TX:
306306
case ITC_IRQ_UART3_RX:
307307
case ITC_IRQ_ADC2:
308308
#endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */
309-
309+
310310
#if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \
311311
defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined (STM8AF622x)
312312
case ITC_IRQ_ADC1:
313313
#endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF626x or STM8AF622x */
314-
314+
315315
#if defined (STM8S903) || defined (STM8AF622x)
316316
case ITC_IRQ_TIM6_OVFTRI:
317317
#else
@@ -320,12 +320,12 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
320320
ITC->ISPR6 &= Mask;
321321
ITC->ISPR6 |= NewPriority;
322322
break;
323-
323+
324324
case ITC_IRQ_EEPROM_EEC:
325325
ITC->ISPR7 &= Mask;
326326
ITC->ISPR7 |= NewPriority;
327327
break;
328-
328+
329329
default:
330330
break;
331331
}
@@ -334,10 +334,10 @@ void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef P
334334
/**
335335
* @}
336336
*/
337-
337+
338338
/**
339339
* @}
340340
*/
341-
341+
342342

343343
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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